JPH04178995A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable a differential amplifier to perform differential amplification at a high speed in its ordinary operating status and at high sensitivity in a standby status by supplying the amplifier with large current in the ordinary operating status and a small current in the standby status. CONSTITUTION:This semiconductor storage device is provided with a differential amplifier 1 which differentially amplifies very low potential between bit lines 4 and 4 and a differential amplifier drive circuit 2 which supplies an electric current to the amplifier 1 through a differential amplifier driving signal line 3 to operate the amplifier 1. The circuit 2 inputs a differential amplifier activating signal 5 and a signal 6 indicating the operating status of the amplifier 1 and is provided with a switching circuit which switches the electric current flowing to the amplifier 1 to a large current in the ordinary operating status and small current in the standby status in accordance with the signal 6. Therefore, the refreshing time interval of the amplifier can be prolonged and the amplifier can make differential amplification at a sufficiently high speed in the ordinary operating status.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor memory device that requires a refresh operation, and mainly relates to a dynamic type semiconductor memory device (hereinafter referred to as rDRAMJ), a ψ-like Nutatinok type semiconductor This relates to a storage device (hereinafter referred to as "pseudo SRAMJ").

<Prior art> Figure 3 shows the conventional DRAM or pseudo SRAM.
A configuration diagram of a bit line, a differential amplifier, and a differential amplifier drive circuit is shown. In Figure 3, 1 is a differential amplifier, 2 is a differential amplifier drive circuit, 3 is a differential amplifier drive signal line, 4 is a bit line, 11 is an N-channel transistor, 12 is a P-channel transistor, and 13 is a delay Shows the circuit.

Next, the order of operation in the circuit configuration shown in FIG. 3 will be described. First, when the differential amplifier activation signal 5 is input to the differential amplifier drive circuit 2, the N-channel transistor II in the differential amplifier drive circuit 2 sends a pull-down signal to the differential amplifier drive signal line 3. Output. Furthermore, the P-channel transistor 12 outputs a pull-up signal to the differential amplifier drive signal line 3 after a delay time caused by the delay circuit 13. Many of these devices (which are becoming more and more popular) use storage batteries as their power source.For portability reasons, it is desirable that storage batteries can be used for long periods of time, but in order to do so, it is necessary to reduce the current consumption. Also, because the internal resistance of the storage battery is high,
Reduction of peak current is also required. In particular, when the computer is waiting with data stored in RAM, the RAM accounts for most of the computer's current consumption.
It is even more desirable that the standby current consumption and peak current of the RAM be small. DRAM or pseudo SRA,
The current consumption of M in the standby state is inversely proportional to the refresh time interval. Therefore, DRAM or pseudo SRAM
Now, we will increase the refresh time interval in the normal operating state where data is input/output to the outside, while in the standby state where data is only held without data input/output to the outside. The current consumption was reduced. This was possible because the leakage current of the memory cell became sufficiently small.

By the way, as a means to extend the refresh time interval, in addition to reducing the leakage current of the memory 7, it is also effective to increase the sensitivity of the differential amplification. If the differential amplification sensitivity is
The larger the current driving the differential amplifier is, the lower the difference is, and the smaller the current is, the same as above. Therefore, in order to make the refresh time interval longer, it is possible to reduce the current that drives the differential amplifier and improve the sensitivity of the differential amplifier. Another advantage is that by reducing the current that drives the differential amplifier, the peak current can also be reduced. However, if the current that drives the differential amplifier is simply reduced, the time required for differential amplification becomes longer under normal operating conditions.

Therefore, the present invention provides a semiconductor memory device that can extend the refresh time interval by improving the differential amplification sensitivity in differential amplification in a standby state, and can perform differential amplification at a sufficiently high speed in a normal operating state. It provides:

<Means for solving the problem> FIG. 1 shows a conceptual diagram of the configuration of the present invention. The semiconductor memory device of the present invention includes a differential amplifier 1 that differentially amplifies the minute potential between the bin lines 4 and 4, and a differential amplifier drive signal for operating the differential amplifier 1. Differential amplifier 1 via line 3
and a differential amplifier drive circuit 2 that supplies current to the differential amplifier. A differential amplifier activation signal 5 and a signal 6 representing the operating state are input to the differential amplifier drive circuit 2.
The present invention is characterized by having a switching circuit that increases the current flowing through the differential amplifier in a normal operating state and decreases it in a standby state.

<Operation> By using the above-described present invention, the differential amplifier drive circuit 2
However, in a normal operating state, a relatively large current is supplied to the differential amplifier l, and in a standby state, a relatively small current is supplied to the differential amplifier l. Therefore, differential amplification is performed quickly in normal operating conditions, and in standby conditions,
It becomes possible to perform differential amplification with high sensitivity.

Example Hereinafter, the present invention will be described in detail based on Examples.

FIG. 2 shows a circuit configuration diagram of an embodiment in a pseudo SRAM. In FIG. 2, l is a differential amplifier that differentially amplifies the minute potential between bit lines 4 and 4, and 2 supplies current to the differential amplifier in order to operate the differential amplifier l. A differential amplifier drive circuit, 3 is a differential amplifier drive signal line, 5 is a differential amplifier activation signal, 6 is a signal indicating whether or not the standby state is healthy, 10 and II are N-channel transistors, 12 is a P-channel transistor, 13.14 shows a delay circuit.

FIG. 6 shows a circuit for generating the signal 6 in the pseudo SRAM, and FIG. 7 shows a signal waveform diagram of each part of the circuit in FIG. When the RFSH transitions to the "H#" state when the CE is in the H-state, the timer 7 is started, and the signal 6 becomes "H" level after a certain period of time has elapsed. Also, RFSH is
'' level, the signal 6 becomes ''L'' level. However, the N-channel transistors 10 and 11 output a pull-down signal to the differential amplifier drive signal line 3, but their driving ability is lower than that of the N-channel transistor 11. , is getting smaller.

Next, the circuit operation under normal operating conditions will be described. Under normal operating conditions, signal 6 is II L #
become the level. At this time, the differential amplifier drive circuit 3 operates at the same timing as the differential amplifier drive circuit 2 in the conventional DRAM shown in FIG. It is assumed that the N-channel transistor 11 in FIG. 2 and the N-channel transistor 11 in FIG. 3 have the same driving capability. A conceptual diagram of the operating waveforms is shown in FIG. When differential amplifier activation signal 5 reaches H# level, N
Channel transistor 11 outputs a differential amplifier drive signal, and after a delay time by delay circuit 13, P-channel transistor 12 generates a differential amplifier drive signal.

Next, the circuit operation in the standby state will be described. In the standby state, the signal 6 goes to the "H" level. When the differential amplifier activation signal 5 goes to the "H" level, the N-channel transistor 10 outputs a differential amplifier drive signal. At this time, since the driving capability of the N-channel transinutor OI''i is smaller than that of the N-channel transistor 11, the differential amplifier drive signal current i4 is smaller than the normal operating state.The operating waveform in the standby state is shown in FIG. A conceptual diagram is shown.

After a delay time by delay circuit 14, N-channel transistor 11 is activated. After the delay time by the delay circuit 13,
P-channel transistor 12 generates the differential amplifier drive signal.

As mentioned above, the differential amplifier drive current (in the standby state (■) is smaller than the differential amplifier drive current in the normal operating state. Therefore, in the normal operating state (■), differential amplification cannot be performed at high speed. , in the standby state, differential amplification can be performed with high sensitivity.

FIG. 8 shows the signal 60 generating circuit in the case of a DRAM. Further, FIG. 9 shows a signal waveform diagram of each part of the circuit of FIG. 8.

In RAS before CAS refresh mode, C
If the RAS signal does not fall within a predetermined time (time set in the timer 7) after the AS signal falls, a standby state is entered and the signal 6 becomes V″H″ level.

Further, due to the presence of the CA and S signals, the standby state of the axis ends and the signal returns to the +j6 level.

Furthermore, although the explanation so far has been about changing the magnitude of the differential amplifier drive current for pull-down operation, it is also applicable to pull-up operation.

<Effects of the Invention> As described above in detail, the present invention allows the refresh time interval to be lengthened by improving the differential amplification sensitivity in the standby state, and also enables sufficiently high-speed differential amplification in the normal operating state. Amplification can be performed. When compared with a conventional semiconductor memory device at the same current consumption, an optimal state can be obtained in which differential amplification is faster in normal operating conditions and differential amplification sensitivity is better in standby conditions.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of the configuration of the present invention. FIG. 2 is a circuit configuration diagram of an embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional example. FIG. 4 is a conceptual diagram of operating waveforms in normal operating state 1. FIG. 5 is a conceptual diagram of operating waveforms in standby state 1. FIG. 7 is a diagram showing a circuit for generating signal 6. FIG. 7 is a signal waveform diagram of each part of the circuit in FIG. 6. FIG. 8 is a diagram showing a circuit for generating signal 6 in the case of a DRAM. 9 is a signal waveform diagram of each part of the circuit in FIG. 8. Explanation of symbols 1: Differential amplifier, 2: Differential amplifier drive circuit, 3: Differential amplifier drive signal line, 4: Bit line, 5: Differential amplifier activation signal, 6: Signal indicating standby state,
7: Timer, ]0°+1: N-channel transistor, +2: P-channel transistor, 13.
14: Delay circuit. Agent Patent Attorney Ume 1) Katsu (2 others) Figure 3 Stone 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. It has a differential amplifier that differentially amplifies the minute potential between the bit lines, and a differential amplifier drive circuit that supplies current to the differential amplifier in order to operate the differential amplifier, and has at least an external connection. In a semiconductor memory device that has two states, a normal operating state in which data is input/output and a standby state in which only data is held, the current for driving the differential amplifier is controlled by a signal representing the operating state. 1. A semiconductor memory device comprising a switching circuit that is large in a normal operating state and small in a standby state.