JPH04177470A - Logic circuit developing system - Google Patents

Abstract

PURPOSE:To speed up processing by utilizing the fact that circuit developing processing can be separated to two processing of compilation and linkage when circuit description data is developed to the data structure of logic circuit information required for logic simulation. CONSTITUTION:A compilation scheduler 2 allocates circuit information to be compiled to compilation/linkage processors 7 by using a compilation/linkage execution processing information storage means 1. A linkage scheduler 3 also allocates the circuit information to be linked to the processors 7 by using the compilation/linkage execution storage means 1. Compilation and linkage information are rewritten by the compilation scheduler 2 and the linkage scheduler 3 via a bus 4. When a processor which performs the compilation and the linkage is allocated, the processing is executed by the compilation/linkage processor 7. When the processing is executed, memory 8 owned by every processor is used in the storage of data in a part in charge, and shared memory 6 is used in the storage of control information via a bus 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic circuit development method, particularly a logic circuit for developing circuit description data such as a circuit diagram into a data structure of logic circuit information required for logic simulation. Regarding the deployment method.

[Conventional technology]

Conventionally, this type of logic circuit development method includes a method in which a logic circuit is developed using a single processor and a method in which a logic circuit is developed using multiple processors.

[Problem to be solved by the invention]

The above-described conventional logic circuit development method has a problem in that when a single processor develops a logic circuit, as circuit information increases, the processing speed decreases accordingly. Furthermore, when a logic circuit is developed using a plurality of processors, there is a problem in that the processing speed cannot be achieved in accordance with the number of processors because there is no special consideration for the processing order.

[Means to solve the problem]

The logic circuit expansion method of the present invention is a logic circuit expansion method for expanding circuit description data such as a circuit diagram into a data structure of logic circuit information required for logic simulation. a compile/link execution information storage means for storing circuit data for each node with a level attached thereto; a compile/link judgment information storage means for storing processing status of circuit data compiling processing and linking processing for each node; a compile scheduler that selects an empty processor among the processors of the lower level circuit data and executes the compile process from the circuit data at the lower level, and updates the memory of the processing status according to the execution; a link scheduler that is activated when the computer moves to a higher level, selects an empty processor among the plurality of processors to execute link processing of the circuit data that has been compiled, and updates the memory of the processing status according to the execution; It is constituted by having.

The above configuration utilizes the fact that the circuit expansion process is divided into two processes, compiling and linking, and can speed up the processing by executing each process in parallel.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The compile scheduler 2 uses the compile/link execution information storage means 1 to allocate circuit information to be compiled to the compile/link processing processor 7. The link scheduler 3 also uses the compile/link execution information storage means 1 to allocate circuit information to be linked to the processor 7. Compilation and link information is rewritten via bus 4 by compile scheduler 2 and link scheduler 3. When a processor for compiling and linking is allocated, the compiling/linking processor 7 executes the processing. When processing is executed, the memory 8 owned by each processor is used to store data for the assigned portion, and the shared memory 6 is used via the bus 5 to store control information, and circuit information is expanded.

Figure 2(a) is a diagram showing an example of circuit information, and Figure 2(b) is a diagram showing an example of circuit information.
) is a diagram showing a data format in which the circuit information of FIG. 2(a) is developed into a tree shape. The number at the top right of the circle (hereinafter referred to as node) in Figure 2(b) is information indicating the depth of the hierarchy (hereinafter referred to as level), and compile scheduler 2 and link scheduler 3 use this number to determine the execution order. .

FIG. 3 is a diagram showing compile/link determination information for determining the processing status of compilation and linking, which is held in each node and stored in the compile/link execution information storage means 1 of FIG. 1. It is. This information is used when searching for a node to perform compile or link processing.

FIG. 4 is a diagram showing data representing the usage status of each processor of the compile Φ link processing processor 7, which is stored in the compile/link execution information storage means 1 of FIG. 1. Used to find free processors for parallel execution of compilation and linking.

FIG. 5(a) is a flow diagram of the processing of the compile scheduler 2. The compilation scheduler 2 first checks the completion flag of the compilation determination information of each node to determine whether the compilation has been completed (step AI). If all compilations have been completed, the process ends. If there are nodes that have not been compiled yet, please refer to Figure 2 (
The level of each node shown in b) is checked, and nodes are extracted in descending order of level number (step A2). Check whether the extracted node has finished compilation processing (
Step A3). If the process has finished, step A
Return to 1. If the processing has not been completed, the data showing the usage status of the processor shown in FIG. 4 is checked, and if there is a free processor, this processor is allocated (step A4).
), the processor usage status is updated (step A5).

The process is then divided into two parts and executed in parallel. One is to return to step AI and search for nodes for which compilation has not been completed. The other step is to proceed to compile execution processing (step A6). When the compilation is completed, update the compilation judgment information of the compiled node (step A7)
. Next, referring to FIG. 2(b), update the compilation completion status of the lower node in the link determination information of the upper node of the node that has completed the compilation process (step A8).
. Next, update the processor usage status (step A9)
.

FIG. 5(b) is a flow diagram of the processing of the link scheduler 3. The link scheduler 3 is activated immediately after the compilation scheduler 2 performs the update in step A8, and first checks the end flag of the link determination information of each node to determine whether the link has ended (step B1). If all links have been completed, the process ends. If there are nodes that have not yet been linked, please refer to Figure 2 (b).
Check the level of each node indicated by and extract the nodes in descending order of level (step B2). Check whether the extracted node has completed link processing. Also, it is checked whether the compiling and linking processes of the lower nodes have been completed and linkage is possible (step B3). If the processing has ended, the process returns to step B1. If the processing has not been completed, check the data indicating the processor usage shown in FIG. 4, and if there is a free processor, allocate this processor (step B4) and update the processor usage (step B5). . The process is then divided into two parts and executed in parallel. One is to return to step B1 and search for a node for which the link has not ended. The other step is to proceed to link execution processing (step BS). When the link ends, link determination information of the linked node is updated (step B7).
.

Next, referring to FIG. 2(b), the link termination status of the lower node in the link determination information of the upper node of the node that has completed the link processing is updated (step B8). Next, the processor usage status is updated (step B9).

FIG. 6(a) is a diagram showing a method of allocation to processors when a single node is connected to the output terminal side of a node (hereinafter referred to as a subsequent node). In the case of a single node, subsequent nodes are allocated to the same processor. This is to avoid increasing communication between processors when allocated to different processors since the connections are dense.

FIG. 6(b) is a diagram showing a method for allocating processors when a plurality of nodes are connected to a subsequent node. In the case of multiple nodes, one node in the latter stage is allocated to the same processor, and the rest are allocated to different processors. This allows parallel execution during simulation.

〔Effect of the invention〕

As explained above, the logic circuit expansion method of the present invention has the effect that processing can be performed faster than conventional methods because some link processing can be executed in parallel before all compilation processing is completed. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2(a) is a diagram showing an example of circuit information, and FIG. 2(b) is a diagram showing the circuit information of FIG. 2(a) as tree-shaped data. 3 is a diagram showing the compile/link judgment information, FIG. 4 is a diagram showing data representing the usage status of the processor, and FIG. 5(a) is a diagram showing the processing of the compile scheduler. Flowchart, FIG. 5(b) is a flowchart of the processing of the link scheduler, FIG. 6(a) is a diagram showing the method of allocation to processors when there is a single 7-word in the subsequent stage, and FIG. b) is a diagram showing a method for allocating processors when there are a plurality of subsequent nodes. 1...Compile/link execution information storage means, 2...
・Compile scheduler, 3... Link scheduler
La, 4.5...Bus, 6...Shared memory, 7...
Compilation/link processing processor, 8...memory.

Claims (1)

[Claims] In the logic circuit expansion method for expanding circuit description data such as circuit diagrams into a data structure of logic circuit information required for logic simulation, a level is attached to the circuit data for each node of the circuit description data expanded in a tree shape. a compile/link execution information storage means for storing compile/link execution information for each node; a compile/link determination information storage means for storing the processing status of circuit data compilation processing and link processing for each node; a compile scheduler that selects and executes a compile process from the circuit data at a lower level and updates the memory of the process status according to the execution; and a compile scheduler that is activated when the compile process moves from the lower level to the upper level under the control of this compile scheduler. , a link scheduler that selects an empty processor among the plurality of processors to execute link processing of the circuit data that has been compiled, and updates the memory of the processing status according to the execution. Deployment method.