JPH04171951A - Structure of semiconductor device - Google Patents

Structure of semiconductor device

Info

Publication number
JPH04171951A
JPH04171951A JP30088790A JP30088790A JPH04171951A JP H04171951 A JPH04171951 A JP H04171951A JP 30088790 A JP30088790 A JP 30088790A JP 30088790 A JP30088790 A JP 30088790A JP H04171951 A JPH04171951 A JP H04171951A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
pattern
resin
projections
substrate
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30088790A
Other versions
JP2956199B2 (en )
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

PURPOSE:To lower unnecessary radiation to a low level and, at the same time, to prevent the occurrence of malfunctions by providing a film of the same material as that of a wiring pattern on the wiring pattern forming surface, at a portion except the wiring pattern, of an insulating substrate facing the active element forming surface of a semiconductor element. CONSTITUTION:A wiring pattern 2 is formed on a substrate 1 so that part of the pattern 2 can face metallic projections 3 and the projections 3 electrically connect electrodes on a semiconductor element 6 to the pattern 2 on the substrate 1. An insulating resin 5 has such a property that the resin 5 is hardened or becomes to have an adhesive strength when the resin 5 is subject to external energy, such as light, etc., and when the projections 3 on the element 6 are pressed against the pattern 2 on the substrate 1, the resin put between them is pushed out and the projections 3 are electrically connected to the pattern 2. When the resin 5 is pushed out, the external energy is applied to the resin 5. At the same time, an electromagnetic shield film 7 is formed of the same material as that of at least one layer of the pattern 2.
JP30088790A 1990-11-06 1990-11-06 The structure of the semiconductor device Expired - Fee Related JP2956199B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30088790A JP2956199B2 (en) 1990-11-06 1990-11-06 The structure of the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30088790A JP2956199B2 (en) 1990-11-06 1990-11-06 The structure of the semiconductor device

Publications (2)

Publication Number Publication Date
JPH04171951A true true JPH04171951A (en) 1992-06-19
JP2956199B2 JP2956199B2 (en) 1999-10-04

Family

ID=17890317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30088790A Expired - Fee Related JP2956199B2 (en) 1990-11-06 1990-11-06 The structure of the semiconductor device

Country Status (1)

Country Link
JP (1) JP2956199B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0969503A3 (en) * 1998-06-30 2002-03-20 Seiko Instruments Inc. Electronic circuit device
US6486412B2 (en) 2000-09-13 2002-11-26 Seiko Epson Corporation Wiring board, method for producing same, display device, and electronic device
US6617521B1 (en) 1998-12-21 2003-09-09 Seiko Epson Corporation Circuit board and display device using the same and electronic equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0969503A3 (en) * 1998-06-30 2002-03-20 Seiko Instruments Inc. Electronic circuit device
US6528889B1 (en) 1998-06-30 2003-03-04 Seiko Instruments Inc. Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
US6617521B1 (en) 1998-12-21 2003-09-09 Seiko Epson Corporation Circuit board and display device using the same and electronic equipment
US6486412B2 (en) 2000-09-13 2002-11-26 Seiko Epson Corporation Wiring board, method for producing same, display device, and electronic device

Also Published As

Publication number Publication date Type
JP2956199B2 (en) 1999-10-04 grant

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