JPH04167732A - Packet composing equipment - Google Patents

Abstract

PURPOSE:To reduce the packet storage capacity by allowing a packet storage section to write information to an optional address from which recorded information is read at the very moment when the information is read therefrom and using the addresses circulatingly to avoid information in excess of bit number of a packet from being inputted. CONSTITUTION:Information is written to an optional address from which recorded information is read in a RAM 30 of a packet storage section 25 at the very moment when the information is read therefrom, storage areas of the RAM 30 are used circulatingly so that the information in excess of M-bits is not inputted to the RAM 30. Thus, the capacity of the RAM 30 is enough to be M bits at minimum. Thus, the capacity of the packet storage section 25 is made small and the component cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet assembling device for packetizing an input information string in a voice packet switching device or the like.

[Prior Art] In general, a 4fl stand device that packetizes audio information etc. input from a plurality of channels is known as shown in FIG.

A1 to AN in the figure are n packet buffers provided in parallel, and each packet buffer A1-8 is inputted with the first to Nth audio information, and when the specified number of bytes is reached, the selection circuit B A request to send a packet is issued. Then, in the selection circuit B, packets are sequentially input from each of the packet buffers A1 to AN, starting with the request for transmission, and
It is multiplexed and sent out over the line.

[Problems to be Solved by the Invention] By the way, in the bucket I/assembly device having the above configuration, when each packet buffer A, ~AN completes the setting of the bucket, a sending request is issued, but each bucket buffer A1 ~AN Since there is no correlation and each operates independently, buckets can be stored at the same time in multiple bucket buffers) )Jl
1. Standing may be completed.

However, in selection circuit B, each packet is
Since it is possible to input only one by one, it takes a certain amount of time to input all of the information, and there is a problem that it takes a long time from the completion of packet assembly to the sending of the packet to the line.

Furthermore, when multiple packet assemblies are completed at the same time,
It takes a certain amount of time to send a packet, but during that time information strings are sequentially input to each bucket buffer A1 to AN to assemble the next packet.
To allow this, an additional bite capacity is required, which raises the problem of increased component costs.

This invention was made in order to solve the above-mentioned problems, and enables efficient packet transmission by shortening the time from completion of packet assembly to packet transmission to the line, thereby improving overall efficiency. It is an object of the present invention to provide a packet assembling device that reduces buffer capacity and costs.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a plurality of buckets for assembling input information strings into packets with a predetermined number of pits, an If rising circuit, and a packet forming circuit from each packet morning rising circuit. This method is applied to a bucket device consisting of a packet multiplexing circuit that multiplexes transmitted packets.

In such a packet assembling device, the packet multiplexing circuit performs packet transmission synchronization, which sequentially transmits a packet transmission synchronization signal to each bucket i-■ vertical circuit at regular intervals while the input information string reaches a predetermined number of bits. a signal generating section, a synchronizing signal distribution section that sequentially distributes the signal from this synchronizing signal sending section to each packet issuing circuit, and each bucket)
, a packet sending unit that multiplexes and sends out packets from the Vfl rising circuit, and each of the packet assembling circuits includes a packet storage unit that stores input information strings until a predetermined number of pits is reached, and a packet storage unit that stores input information strings until a predetermined number of pits is reached. The present invention is characterized by comprising a storage control section that uses the storage area cyclically and controls the readout of packets that have accumulated to a predetermined number of hits in the packet storage section based on the bucket I/transmission synchronization signal.

[Operation] With the above configuration, continuously inputted information strings are sequentially stored in the packet storage section of each packet assembly circuit. The packet transmission synchronization signal generating section outputs a synchronization signal at regular intervals, and the synchronization signal distribution section sends out the synchronization signal 1110 times to the storage control section of each packet assembling circuit.

Upon receiving the synchronization signal, the storage control section controls the packet storage section and sends the packets processed by the packet storage section to the packet transmission section, and the packet transmission section receives the packets I from each packet storage section. It is multiplexed and sent out on the line. Then, the synchronization signal goes around until the packet is assembled in the packet storage unit, and the synchronization signal that went through the cycle is output again when the next packet is assembled to the packet storage unit from which the packet I was sent. Ru. The synchronization signal is sequentially sent out to the packet storage section of each packet morning circuit, and the packets are sent out continuously via the bucket I sending section.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to FIGS. 1 and 3.

First, the overall configuration of the packet lgJl stand-up apparatus of this embodiment will be explained based on FIG.

The packet assembling device of this embodiment assembles information strings inputted from N channels at a transmission rate of 1/sec into buckets P each having a predetermined number of bits. 11.4, and the buckets output from each packet morning circuit 111 to 11N.
-P and a packet multiplexing circuit 12 that multiplexes and sends the multiplexed packets to the line.

The packet multiplexing circuit 12 includes a packet sending synchronizing signal generating section 15 that sends out a synchronizing signal at regular intervals, and a signal from this sending section 15 that is sequentially transmitted to each packet assembling circuit 111 to 1.
Synchronous signal distribution unit 16 that distributes to 1N and each bucket) 4
and a packet sending unit 17 that multiplexes and sends out packets P from the No. 11 circuits 111 to 11N.

The packet transmission synchronization signal generating section 15 generates a signal from each packet assembling circuit 1 while the information string input to the packet storage section 25 (to be described later) reaches a predetermined number of bits (in this embodiment, the number of M pits).
A synchronizing signal is sequentially sent to 11 to IIN at regular intervals t@. This fixed interval t is a time interval determined by t=M/ (V When the synchronization signal is sent to the assembly circuit 11 again, an M-bit packet P has been assembled in the packet storage section 25.

The synchronization signal distribution section 16 is a packet transmission synchronization signal generation section 15.
The synchronization signals that are sequentially sent out at regular intervals t are sequentially distributed from the packet assembling circuit 111 to the assembling circuit 11N. Specifically, a synchronization signal is received from the packet transmission synchronization signal generation section 15, counted in N-ary system, and the synchronization signal is sent to each packet assembling circuit 11. ~111. N-ary counter 1 that sends out a decode signal specifying which of J
8, and a decoder 19 that selects a destination based on the decoded signal sent from the N-ary counter 18 and sends out a synchronizing signal.

The packet sending unit 17 sends a packet to the packet storage unit 25)
It consists of a selection circuit 20 that selectively connects the assembled packet assembly circuits 11 to 11N to the line side, and a FiFo 21 that buffers the packets P from this selection circuit 20 and sends them out to the line. .

Further, each of the packet assembling circuits 111 to 11N has a packet storage section 25 that stores the information strings input thereto until the number of hits reaches M, controls writing of the information strings to this packet storage section 25, and controls the writing of the information strings to the packet storage section 25. The storage control section 26 controls the readout of the packets P assembled in the packet storage section 25 in response to a packet transmission synchronization signal.

The packet storage section 25 is composed of a RAM 30, and its storage area has the same capacity as the packet P, M bits. The information stored in M pits in the packet storage section 25 may be written to the addresses that make up the storage area from the middle. In this case, if you go from the beginning of the writing to the end of the writing order, the first By returning and writing up to the writing head, information for M pits is written. That is, the storage area of the packet storage section 25 is used cyclically. Furthermore, RAM
30 is provided with a circuit (not shown) for adding a header to the packet P.

The storage control unit 26 includes a read/write control 33 that issues write and read commands to the RAM 30 in response to a synchronization signal from the decoder 19, and a read address counter 34 that counts read addresses based on a pit clock that is constantly inputted in response to a synchronization signal. , a write address counter 35 that counts write addresses based on the pit clock.
, a selection circuit 36 that selectively outputs address signals from each address counter 34 and 35 to the RAM 30, and the read address counter 34 and write address counter 35.
The writing header is specified by the signal from The subtraction circuit 37 controls the read address counter 34 so as to address the packet P. Note that the hit clock input to the read address counter 34 is N times faster than the pit clock input to the write address counter 35, and the R
The write time of AM30 is Nt, and the read time is t. Then, the packet P is sent to the packet sending unit 17 (VXN
) is transmitted at a speed of

Next, the operation of the packet assembling apparatus having the above configuration will be explained based on FIGS. 1 and 3.

Information strings are input to the packet storage sections 25 of each of the packet assembly circuits 111 to 11.4 at a speed of V bits per second, and each information string is sequentially written to each address of the RAM 30 by the write address counter 35. It can be done. Additionally, a header is added.

On the other hand, in the packet transmission synchronization signal generating section 15, a synchronization signal is transmitted at the regular intervals (Fig. 3(a), (
al) to (aN)) are input to the N-ary counter 18 and the decoder 19. The N-adic counter 18 counts each synchronizing signal one by one, and the decoder 19 sequentially changes the allocation from the packet assembling circuit 111 to the circuit 11N.

When each bucket 14 vertical circuit 111 to 11N receives a synchronization signal, the read/write control 33
outputs a read command signal to the RAM 30 and at the same time starts a read address counter 34. At this time, the read address counter 34 controlled by the subtraction circuit 37 specifies the write head and sequentially specifies the addresses of the M pits from the first written information. As a result, a bucket) P to which M bits of J\tsuda are added from the beginning of the write is assembled and output to the packet sending unit 17. Furthermore, when information is read out sequentially from the beginning of writing,
New information is sequentially written from the read portion. That is, the storage area of the RAM 30 is used cyclically for reading and writing.

bucket), If rising circuit] 1, perform the above operation here, or each packet assembling circuit 11. The operation start point of ~11N is controlled by a synchronizing signal B outputted to a constant amount 5a t @.

Then, the synchronization signal is sequentially outputted from the packet assembly circuit 111 to the assembly circuit 11N at regular intervals, and after the synchronization signal is output to one packet assembly circuit 11, the output is N7 until the synchronization signal is output again. Time passes. During this time, M bits of information are accumulated in the RAM 30.

Roughly speaking, the synchronization signal is outputted to one of the packet morning rising circuits 11 at regular intervals, and in the sending section 17, the synchronizing signal is outputted from the 4ff rising circuit 11 to a bucket with a width of read time t. -P is input at regular intervals (Fig. 3 (1) +) to (bN)), temporarily huffer-linked by the FiFo 21, and continuously sent to the line (Fig. 3 (C)).

Here, to give an example of specific numerical values for each part, if the number of channels N = 10, the transmission speed V = 64 kb/s, and the packet length M = 128 bytes, then t = M/ (VXN
) (128xB) = =1.6m5 (64X 1
03X10), and a synchronization signal is output at a fixed interval], 6mS@.

As described above, in the RAM 30 of the packet storage unit 25, information recorded from an arbitrary address is written to the part read out at the next moment of reading, and the storage area of the RAM 30 is used cyclically to write more than M bits or more. information is RA
Since no input is made to M30, the capacity of this RAM30 only needs to be at least M hits. For this reason,
The packet storage section 25 can be configured with a small capacity component, and component costs can be reduced.

In addition, since the synchronization signal for controlling the packet sending timing is outputted at regular intervals in each packet morning rising circuit 111 to 11N, the packets are simultaneously output from the plurality of packet storage sections 25).
It is possible to efficiently send out the bucket P by eliminating the sending waiting time and shortening the time from the completion of packet assembling to sending the packet to the line without sending out the packet.

[Effects of the Invention] As described above in detail, the present invention has the following effects.

In the packet storage section, the part where information recorded from an arbitrary address is read is written at the moment after reading it, and it is used cyclically to avoid inputting more information than the number of hits in the packet. Therefore, it is possible to suppress the capacity of the packet t[edge part to approximately the same number of hits as the packet. Therefore, the packet storage section can be configured with a small capacity component, and component costs can be reduced.

In addition, since the synchronization signal that controls the bucket I/transmission timing is output at regular intervals in each bucket I-■ vertical circuit, buckets are not sent out from multiple packet storage units at the same time, eliminating transmission waiting time. By doing so, the time from the completion of packet assembly to sending the packet to the line can be shortened, and the packet can be sent efficiently.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the bucket of the present invention) 8fl standing device, Fig. 2 is a schematic configuration diagram showing a conventional packet assembling device, and Fig. β is the packet shown in Fig. 1) Packet sending synchronization signal in the 4J1 standing device This is a time chart of the packets sent. 111-11N...Packet assembly circuit, 12...Packet multiplexing circuit, 15...Packet sending synchronization signal generation section, 16...Synchronization signal distribution section, 17...Packet sending section, 25... Packet accumulation unit, 26... accumulation control unit.

Claims (1)

[Scope of Claims] A packet assembling device comprising a plurality of packet assembling circuits that assemble input information strings into packets of a predetermined number of bits, and a packet multiplexing circuit that multiplexes packets sent out from each packet assembling circuit, The packet multiplexing circuit includes a packet transmission synchronization signal generating section that sequentially transmits a packet transmission synchronization signal to each packet assembly circuit at regular intervals while the input information string reaches a predetermined number of bits, and a packet transmission synchronization signal generating section that sequentially transmits a packet transmission synchronization signal to each packet assembly circuit at regular intervals, and from this synchronization signal transmission section. a synchronous signal distribution unit that sequentially distributes the signal to each packet assembly circuit;
It consists of a packet sending section that multiplexes and sends out packets from each packet assembling circuit, and each packet assembling circuit has a packet storage section that stores an input information string until it reaches a predetermined number of bits; 1. A packet assembling device comprising: a storage control section that uses a storage area cyclically and controls readout of packets assembled into a predetermined number of bits in the packet storage section according to the packet transmission synchronization signal.