JPH04165877A - Picture processor - Google Patents

Abstract

PURPOSE:To easily obtain an appropriate slave screen picture by extending and contracting the cycle of a clock signal for reading out picture data in a horizontal direction in order to correct the distortion of the expansion and contraction of a vertical direction of the slave screen picture generated in the picture-in-picture processing of an video signal between different system. CONSTITUTION:At the time of reading out the picture data of a slave screen put in to a master screen from a picture memory 8, the cycle of a reading clock signal in the scanning direction is changed into a value in proportion to the ratio of the number of the scanning lines of an effective screen: 1/1.2, so that the horizontal direction of the slave screen picture can be reduced, and the distortion due to the reduction of the vertical direction can be corrected. Thus, an above mentioned clock signal CR is prepared by a reading controlling circuit 21 in order to correct the horizontal direction, based on the output of a master and slave field discriminating circuit 22.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device for parent-child display that performs picture-in-picture processing in which a child screen is inserted into a part of a parent screen;
In particular, the present invention relates to an image processing apparatus suitable for multi-system video tape recorders and color TV receivers.

[Prior Art] FIG. 4 is a block diagram showing an example of an image processing device PO for parent-child display applied to a conventional color image receiver.

In the figure, for example, a PAL system composite video signal is input as a composite video signal S1 for the main screen, a video signal S3 for the child screen is inserted by a switch 3, and a composite video signal S4 is output via a buffer 4. be done.

On the other hand, the composite video signal of the same <PAL system is input as the composite video signal S2 for the child screen, and the Y/C separation circuit 5
The chroma signal C is separated into a luminance signal Y and a chroma signal C by the chroma demodulation circuit 6.
-Y. Iw degree signal Y and color difference signal R-Y
, B-Y are sampled by the A/D conversion circuit 7 and written into the image memory 8 as digital data.

The synchronization separation circuit 12 generates a composite video signal S2 for the child screen.
The synchronization signal extracted from the write synchronization signal is sent to the write control circuit 13 and the parent-child display control circuit 15 and used as a write synchronization signal. Based on the control of the parent and child display control circuit 15 that controls on/off of the tR child display mode and the size and position of the child screen, the image memory 8 stores digital data obtained by sampling and sampling of the A/D conversion circuit 7. Writing to is controlled by a write control circuit 13.

The synchronization signal extracted from the composite video signal S1 for the main screen by the synchronization a circuit 1 is sent to the readout control circuit 14 and the parent-child display control circuit 15, and is used as a readout synchronization signal. Reading of digital data from the image memory 8 and D/A conversion of the read digital data [luminance signal Y by 181W89, color difference signal RY,
The conversion to B-Y is performed in the readout control circuit F? under the control of the parent-child display control circuit 15. 114.

The output of the APC (automatic phase control) circuit #I2, which generates chroma subcarriers that are synchronized with the composite video signal S1 for the main screen and whose phase is synchronized with the chroma signal, is output from the D/A conversion circuit R9. The chroma signal C is modulated by the color difference signals R-Y and B-Y, and sent to the chroma modulation circuit 1 as a chroma signal C.
Output from 0.

The chroma signal C and the luminance signal Y output from the D/A conversion circuit 9 are synthesized by the Y/C synthesis circuit 11, and then inserted into a predetermined position of the composite video signal S1 for the main screen by the switch 3. Composite IPII via buffer 4
It is output as an image signal S4.

FIG. 5 is an example of a parent-child display screen in, for example, a color TV receiver to which the conventional image processing apparatus illustrated in FIG. 4 is applied.

As shown, the embedded child screen has the same PA as the parent screen.
Since it is the L method, the sub-screen image is normal and the sphere is displayed as a circle. This means that both the parent screen and child screen are NT.
The same applies to the SC method.

[The 811fl that the invention attempts to solve] Recently, multi-system video tape recorders have become popular, and while playing a European souvenir PAL video tape as the main screen, it is possible to watch currently airing TV programs (NTSC system). There are times when you want to monitor on a sub screen.

In that case, a PAL composite video signal is input for the main screen, and an NTSC composite video signal is input for the child screen. A display example of the parent-child display screen at this time is shown in the sixth section.
In this case, the child screen is reduced vertically and the sphere is displayed as a horizontally elongated ellipse, as shown in FIG. 0 in FIG.

When a PAL system sub-screen is inserted into an NTSC system main screen, the screen becomes as shown in No. 61(b).

In this case, the child screen will be stretched vertically, and the sphere will be displayed as a vertically long ellipse.

This is because the effective screen scanning lines per field are approximately 288 in the PAL system and approximately 240 in the NTSC system, so the sub-screen is reduced (or expanded) vertically and flattened horizontally (or 1). This is because it will be displayed as a video.

An object of the present invention is to provide an image processing device that can easily correct the vertical expansion/contraction distortion in a sub-screen video as described above even in parent-child display between composite video signals of different television systems. It is in.

[Measures Pi for solving the problem] Therefore, in the image processing device according to the present invention, in an image processing device that performs picture-in-picture processing in which a child screen is inserted into a part of a parent screen, It has means for detecting the number of scanning lines per field of the composite video signal for the screen and for the sub-screen, and for generating a readout clock signal with a period proportional to the ratio of the number of scanning lines of the two. The present invention is characterized in that the vertical expansion/contraction distortion caused in the sub-screen image due to the difference in the number of scanning lines is corrected by controlling the horizontal reading cycle of the sub-screen image data using the readout clock signal. .

[Function] According to the configuration of the image processing device according to the present invention, the parent-child field discrimination step shown in FIG. 1 calculates the number of scanning lines per field based on the composite video signal S1 for the parent screen. This is detected and set as the first number of scanning lines. Furthermore, the number of scanning lines per field is detected based on the composite video signal S2 for the child screen, and this is set as the second number of scanning lines. Distinguish between differences.

The read clock control circuit 21 is configured to control the first and second clocks.
Based on the number of scanning lines, a readout clock CR having a frequency proportional to the ratio of the number of first scanning lines to the number of second scanning lines is generated, and the readout time axis from the image memory 8 by the readout control circuit 114 is adjusted to The horizontal scanning direction is corrected only during the fitting period.

[Example] Next, an example of the image processing device P according to the present invention will be described in detail with reference to the drawings.

Note that, for convenience of explanation, the following conditions are assumed.

(b) Input composite video signal S1. S2 uses two systems: PAL and NTSC. Therefore, among the four combinations of parent screen vs. child screen, PAL vs. NTSC and NT
In the case of SC versus PAL, vertical expansion/contraction distortion of the sub-screen image occurs due to the difference in the number of scanning lines of the effective screen per field. Since the present invention is not dependent on these combinations, only PAL vs. NTSC will be discussed below.

(b) The number of horizontal scanning lines on the effective screen per field (1v) shall be 240 (NTSC) and 288 (PAL).

(c) The insertion position and size of the NTSC composite video input signal S2 for the child screen arbitrarily set by the parent and child display control circuit 15 are set to the lower right corner position and 1/4 size of the parent screen.

FIG. 1 is a block diagram showing an example of an image processing apparatus according to the present invention.

In the figure, the structure is the same as the conventional example shown in FIG. 4 except that a read clock control circuit 21 and a parent-child field discrimination circuit 22 are newly provided, so the same components as the conventional example are the same. The explanation will be omitted, and the explanation will focus on the newly added circuits 21 and 22.

In the figure, the parent-child field discrimination circuit 22 receives the composite video signal S1. The readout clock control circuit 21, which determines the television system in S2, uses the 20
The clock number/horizontal scanning period of No. 7913 CW (shown in FIG. 2) is corrected and outputted to each read control circuit 1 14 as a black/reverse signal CR.

Figure 2 shows the A/D for the NTSC composite video signal S2 for the sub screen during one horizontal scanning period (hereinafter referred to as IH).
This is an example of a timing chart showing sampling and writing processing to the image memory 8 by the conversion circuit 111i7.

FIG. 5A shows an NTSC composite video signal S2 for an IH small screen. The clock signal CW shown in (l) is a clock pulse generated by, for example, a phase-locked loop (PL, L) of the write control circuit 13 based on the horizontal synchronization signal, and in this example, the clock signal CW is 480 clocks/11 (480 clocks/11). .

The clock signal CD shown in (C) is the parent-child display control circuit 1.
The size information of the child screen output from 5 (in the example, 1/
4), the frequency of the clock signal CW is divided by four. In addition, (not shown in (1), the logical product of the enable signal EV and the clock signal CW is supplied from the write control circuit 13 as a sampling control pulse to the A/D conversion signal 7, and as a write control pulse (supplied to the image memory 8 as a wholesale pulse). be done.

In this way, digital image data of 100 sample points is stored in the image memory 8 for every four drawings per IH.

Also, since the sub-screen size is 1/4, in this example, out of the 240 effective scanning lines excluding the vertical blanking period (22,5l-()), every 4th line corresponds to 60 scanning lines. By performing sampling as described above in step 1', the sampling of the video signal of one field (IV=262.58) and the writing of the image data obtained thereby into the image memory 8 are completed. That is, 1 /4 size small screen data is 100 sample points x 60 scanning lines ii (#
It is written into the image memory 8 as data.

The timing chart shown in FIG.
This shows the process of inserting the sub-screen video signal S3 obtained by Y/C synthesis into a predetermined position of the main screen composite video signal Sl after /A conversion and chroma modulation.

Figure (a) shows the PAL composite video signal Sl for the IH main screen.
It is. IA(b) is a clock signal CR for correcting expansion/contraction distortion in the vertical direction of the sub screen according to the present invention.
It is.

Conventional wave! In , 480 clocks/LH was used as the corresponding clock signal, so although the horizontal size of the child screen embedded in the main screen can be reproduced normally, the vertical size is limited by the number of scanning lines on the effective screen of the PAL system. 2
The number of effective scanning lines in the NTSC system is reduced in proportion to 1/12, which is the ratio of 240 lines/field to 88 lines/field.

Therefore, in this example, the image that should be a perfect circle on the child screen is reduced in the vertical direction and displayed as a horizontally flattened ellipse.

In order to correct this problem, methods such as scanning line number conversion (interpolation or thinning) can be considered, but in addition to increasing the scale of the equipment, this method is not always satisfactory for moving images such as TV images. It is hard to say that it is a good measure as it does not give the desired results.

On the other hand, in the present invention, when reading the image data of the child screen to be inserted into the main screen from the image memory 8,
By changing the period of the read clock signal in the scanning line direction to a value proportional to the ratio of the number of scanning lines of the effective screen to 1/1.2, the horizontal direction of the sub-screen image is reduced, and the distortion caused by the vertical reduction is This is to correct.

For such correction in the horizontal direction, the above-mentioned clock signal C1? is generated. Specifically, the composite video input signal S1. Based on S2, the parent-child field discrimination circuit 22 determines the number of scanning lines/field (3
12.5 lines, 262.5 lines), and based on the number of effective screen scanning lines obtained from these numbers of scanning lines, the clock signal CR is output by, for example, a PLL provided in the readout clock control port n21. =576 (=480X28
8/240. ) Generates clock /IH (PAL).

13(c) is an enable signal ERR in the horizontal (scanning line) direction, and its width WH changes according to the position and size of the sub-screen. ! are the 410th clock and the 510th clock. The enable signal ERH generated by the parent-child display control circuit 15 is supplied to the read control circuit 14.

FIG. 5E shows a vertical enable signal ERV, the width Wv of which is changed depending on the position and size of the child screen. In the case of 121, the on which regulates the width W■
Off position 1 is 220H and 2808th. This enable signal ERV is generated by the parent-child display control circuit 15,
The signal is supplied to the read control circuit 14.

The readout control port V@14 outputs the AND of the clock signal CR, the horizontal enable signal ERI (and the vertical enable signal ERV) as a readout clock signal, and controls the readout of image data from the image memory 8. The resulting image data undergoes D/A conversion, chroma modulation, Y/C
After each synthesis process, the child screen is fitted into a predetermined position of the main screen by the switch 3, and a composite video signal S4 shown in FIG. 3(d) is obtained. These processes are similar to the conventional example.

Switch 3 is for fitting the child screen into the main screen.

It is controlled by the AND of the horizontal and vertical enable signals E R11 and E RV output from the parent-child display control circuit 15. The size of the sub-screen in the PAL composite video signal S4 obtained in this way is 61/1 in the horizontal direction in addition to the vertical direction in the conventional example.
．． Since the sphere is reduced by a factor of two, the sphere is displayed as a circle, as shown in FIG. 5, for example.

[Effects of the Invention] As described above, according to the configuration of the present invention, the vertical expansion/contraction distortion of the sub-screen video that occurs during picture-in-picture processing of a different format video signal is reduced because the image data is read out in the horizontal direction. This is corrected by expanding or contracting the period of the clock signal.

Therefore, since the embedded screen (child screen) can be corrected without requiring a large-scale circuit configuration such as scanning line interpolation or thinning as in the past, a suitable child screen image can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an image processing device according to the present invention, FIG. 2 is a timing diagram showing image data writing processing in the same device, and FIG. 3 is a timing chart showing image data reading processing in the same device. 4 are block diagrams showing an example of a conventional image processing device, and FIGS. 5 and 6 are diagrams showing examples of displaying a sub-screen by the conventional device. 7... A/D conversion circuit 8 - Wji image memory 9... D/A conversion circuit 13 - Write control circuit 14 - Read control circuit 15 - Parent-child display control circuit 21 - Read clock control circuit 22 - Parent-child Field discrimination circuit S1 - Composite video signal for main screen 82 Composite video signal for sub-screen S3 - Sub-screen video signal S4 Composite video signal

Claims (1)

[Claims] (1) In an image processing device that performs picture-in-picture processing in which a child screen is inserted into a part of the main screen, the number of scanning lines per field of the input composite video signal for the main screen and the child screen is detected. It also has means for generating a readout clock signal with a period proportional to the ratio of the number of scanning lines between the two, and the vertical expansion/contraction distortion caused in the sub-screen image due to the difference in the number of scanning lines between the two is corrected by the readout clock signal. What is claimed is: 1. An image processing device that performs correction by controlling a horizontal reading period of image data for a small screen.