JPH04164306A - Terminal electrode formation method of electronic part - Google Patents
Terminal electrode formation method of electronic partInfo
- Publication number
- JPH04164306A JPH04164306A JP27017888A JP27017888A JPH04164306A JP H04164306 A JPH04164306 A JP H04164306A JP 27017888 A JP27017888 A JP 27017888A JP 27017888 A JP27017888 A JP 27017888A JP H04164306 A JPH04164306 A JP H04164306A
- Authority
- JP
- Japan
- Prior art keywords
- jig
- terminal electrodes
- baking
- ceramic powder
- conductive paint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000000843 powder Substances 0.000 claims abstract description 22
- 239000000919 ceramic Substances 0.000 claims abstract description 21
- 239000003973 paint Substances 0.000 claims abstract description 13
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052582 BN Inorganic materials 0.000 claims description 2
- 239000003985 ceramic capacitor Substances 0.000 abstract description 22
- 229910052878 cordierite Inorganic materials 0.000 abstract description 3
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 abstract description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000006060 molten glass Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
Abstract
Description
【発明の詳細な説明】
産1」Jlt肚分1−
本発明は、電子部品の端子電極形成方法に関し、特に積
層セラミックコンデンサ等における導電塗料の焼成によ
る端子電極の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming terminal electrodes for electronic components, and more particularly to a method for forming terminal electrodes in multilayer ceramic capacitors and the like by firing conductive paint.
従】長口支術−
第2図に示すような一般的な構造をした積層セラミック
コンデンサは、次のようにして製作される。[Second] Long mouth technique - A multilayer ceramic capacitor having a general structure as shown in FIG. 2 is manufactured as follows.
ます、微細化したセラミック粉末と有機バインダを混練
した後、ドクターブレード法によって生ソートを作製す
る。次にこの生シートを所望の面積に切断し、その表面
の片面にスクリーン印刷により内部電極を被着・乾燥し
た生ソートを用意する。次に内部電極を印刷した生シー
トを電極を印刷しない生シートからなる保護層で、上下
からはさむようにして所望の枚数を積み重ね、積層体を
形成し、熱圧着した後、個片状態に切断して生チツプ個
片を形成する。この生チツプ個片を焼成して、第2図(
a)に示す焼成チップ1を作製する。First, after kneading the finely divided ceramic powder and an organic binder, a green sort is produced by the doctor blade method. Next, this raw sheet is cut into a desired area, and internal electrodes are applied to one side of the sheet by screen printing and dried to prepare a raw sort. Next, the desired number of raw sheets with internal electrodes printed on them are stacked by sandwiching them from above and below with a protective layer made of raw sheets without electrodes printed on them to form a laminate, which is heat-pressed and then cut into individual pieces. to form individual raw chips. These individual pieces of raw chips are fired and are shown in Figure 2 (
A baked chip 1 shown in a) is produced.
そして、その両端に銀を主成分として少量のガラスフリ
ントを含む導電塗料を塗布して、端子電極2,2を形成
する。最後にそれを焼き付けてチップ型積層セラミック
コンデンサ3を作成する。Then, a conductive paint containing silver as a main component and a small amount of glass flint is applied to both ends to form terminal electrodes 2, 2. Finally, it is baked to produce a chip type multilayer ceramic capacitor 3.
さらに、所望により、上記チップ型積層セラミックコン
デンサ3に、第2図(b)に示すようにす−ド線4,4
をハンダ付けし、最後に樹脂5にてモールドを施して、
リード付積層セラミックコンデンサ6が作成される。Furthermore, if desired, the chip type multilayer ceramic capacitor 3 may be provided with lead wires 4, 4 as shown in FIG. 2(b).
Solder and finally mold with resin 5,
A multilayer ceramic capacitor 6 with leads is produced.
8 f ′ −
ところで、上記従来の端子電極2,2の焼付けにおいて
、両端に導電塗料か塗布された多数の焼成チップ1,1
・・・・・・が、治具等に載置されて一括して焼成され
ているが、焼き付けをされる導電塗料には少量のガラス
フリットが入っているため、焼き付は時(400℃以上
)にガラスフリy)は溶融し、溶融したガラスフリット
は端子電極2,2の表面に出てくるため、端子電極2,
2同士が接触した状態で焼き付けすると、表面に出たガ
ラスフリットによりチップ同士が端子電極2.2にてく
っついてしまうという欠点があった。従って、この場合
、焼付けする時のチップはまばらな状態にしなくてはな
らす生産性が悪い。8f' - By the way, in the above conventional baking of the terminal electrodes 2, 2, a large number of baked chips 1, 1 with conductive paint applied to both ends
... are placed on a jig or the like and fired all at once, but since the conductive paint to be baked contains a small amount of glass frit, the baking takes place at a temperature of 400°C. The glass frit y) melts in the above), and the molten glass frit comes out on the surface of the terminal electrodes 2, 2.
If the chips are baked in a state where they are in contact with each other, the glass frit exposed on the surface causes the chips to stick to each other at the terminal electrodes 2.2. Therefore, in this case, the chips must be scattered in a sparse state during baking, resulting in poor productivity.
また、焼付は後の端子電極2,2のくっつきをり粉末を
散布し、端子電極2,2←中→が接触している部分にア
ルミナ、ジルコニア等のセラミ。In addition, after baking, sprinkle powder to prevent the terminal electrodes 2, 2 from sticking together, and apply ceramic such as alumina or zirconia to the part where the terminal electrodes 2, 2←center→are in contact.
る。しかし端子電極2,2表面のガラスフリットと、ア
ルミナ、ジルコニア等のセラミック粉末が、反応し、端
子電極2,2表面にアルミナ、ジルコニア粉末が付着し
てしまい、端子電極2,2のハンダ付性、外観に悪影響
を与え、また、端子電極2,2の表面にメツキを施した
場合においても、アルミナ、ジルコニア粉末の付着して
いる部分には、メツキが付かないという欠点があった。Ru. However, the glass frit on the surface of the terminal electrodes 2, 2 reacts with the ceramic powder such as alumina, zirconia, etc., and the alumina and zirconia powder adheres to the surface of the terminal electrodes 2, 2, resulting in poor solderability of the terminal electrodes 2, 2. This has a negative effect on the appearance, and even when the surfaces of the terminal electrodes 2, 2 are plated, the parts to which the alumina and zirconia powders are attached are not plated.
−−の
この発明は、導電塗料の焼き付は時において、導電塗料
が被着された多数の電子部品を窒化硼素(以下BNと称
する)系のゼラミノク粉末を介在して密に配列して焼き
付けることを特徴とする。--This invention discloses that when baking a conductive paint, a large number of electronic components coated with a conductive paint are sometimes baked in a dense array with a boron nitride (hereinafter referred to as BN) based gelaminok powder interposed therebetween. It is characterized by
1肛
上記のBN系セラミック粉末は、端子電極焼き付は時に
端子電極同士の接触を妨げ、焼き付は後の端子電極同士
のくっつきが防げる。またBN系セラミック粉末は、導
電塗料を構成する金属やガラスフリットに対して反応し
ないため、端子電極焼き付は後、端子電極へのBN系セ
ラミック粉末の付着はない。The BN-based ceramic powder described above sometimes prevents the terminal electrodes from contacting each other when the terminal electrodes are baked, and the baking can prevent the terminal electrodes from sticking together afterward. Further, since the BN ceramic powder does not react with the metal or glass frit that constitutes the conductive paint, the BN ceramic powder does not adhere to the terminal electrode after the terminal electrode is baked.
災胤肚
以下、この発明の一実施例について図面を参照して説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第1図は焼き付けに用いる治具7(セッター;コージラ
イト、アルミナ製)と、その上に密に配列された端子電
極用導電塗料が塗布された積層セラミックコンデンサ8
の平面図であり、円内は、その部分的拡大図である。Figure 1 shows a jig 7 (setter; made of cordierite, alumina) used for baking, and a laminated ceramic capacitor 8 coated with conductive paint for terminal electrodes arranged densely thereon.
FIG. 1 is a plan view of FIG.
この発明による積層セラミックコンデンサの端子電極焼
き付は方法は、次のようなものである。The method for burning the terminal electrodes of a multilayer ceramic capacitor according to the present invention is as follows.
まず、焼き付けに用いる治具として、コージライトある
いはアルミナの治具7を用意し、この治具7の上面に端
子電極用導電塗料の塗布された積層セラミックコンデン
サ8を互いに重ならない様に、密に並べる。次に、BN
系セラミック粉末(例えばデンカボロンナイトライドH
TD電気化学工業株)を治具7上に並へられた積層セラ
ミ、クコンデンサ8の上から散布する。上記BN系セラ
ミック粉末は、粒径lOθμ−〜300μ■程度である
ため、散布する時、周囲に散乱することなく治具7上に
均一に散布することが可能となる。First, a jig 7 made of cordierite or alumina is prepared as a jig used for baking, and the multilayer ceramic capacitors 8 coated with conductive paint for terminal electrodes are placed on the top surface of this jig 7 tightly so as not to overlap each other. Arrange. Next, B.N.
ceramic powder (e.g. DENKABORON NITRIDE H)
TD Denki Kagaku Kogyo Co., Ltd.) is sprayed onto the laminated ceramic capacitor 8 arranged on the jig 7. Since the above-mentioned BN ceramic powder has a particle size of about 1Oθμ− to 300μ■, when it is sprinkled, it can be uniformly sprinkled on the jig 7 without being scattered around.
次にBN系セラミックの散布された治具7を、コンベア
ベルト焼成炉に投入し、550℃〜650℃の温度で約
1時間焼き付ける。焼き付けが終わった治具7は、メツ
シュを用いて、BN系セラミック粉末と積層セラミック
コンデンサ8に分離する。この分離の際、端子電極同士
のくっつきによりメツシュ上に残る積層セラミックコン
デンサ8は認められなかった。分離された積層セラミッ
クコンデンサ8の表面には、若干BN系セラミック粉末
が付着しているため、これらを除去するために、超音波
洗浄を実施する。Next, the jig 7 on which the BN ceramic is sprinkled is placed in a conveyor belt firing furnace and fired at a temperature of 550°C to 650°C for about 1 hour. After baking, the jig 7 is separated into a BN ceramic powder and a multilayer ceramic capacitor 8 using a mesh. During this separation, the multilayer ceramic capacitor 8 remaining on the mesh was not observed due to the terminal electrodes sticking together. Since some BN-based ceramic powder adheres to the surface of the separated multilayer ceramic capacitor 8, ultrasonic cleaning is performed to remove this.
この超音波洗浄の結果、端子電極にBN系セラミック粉
末の残存は認められず、端子電極にメツキを施して−4
、BN系セラミック粉末の付着に起因するメツキ付着は
認められなかった。As a result of this ultrasonic cleaning, no residual BN ceramic powder was found on the terminal electrode, and the terminal electrode was plated and
, No plating adhesion due to adhesion of BN-based ceramic powder was observed.
なお、上記実施例は積層セラミックコンデンサの端子電
極形成について説明したが、他のコンデ/す、抵抗、半
導体素子等任意の電子部品の端子電極形成に適用できる
ものである。Although the above embodiments have been described with respect to the formation of terminal electrodes of a multilayer ceramic capacitor, the present invention can be applied to the formation of terminal electrodes of any other electronic component such as a capacitor, a resistor, a semiconductor element, or the like.
光肚Δ旦策
以上説明したように、この発明は、積層セラミ、クコン
デンサの端子電極焼き付は時にBN系セラミック粉末を
使用することにより、焼き付は治具上に密に並べられ、
生産性が約2倍に向上する。また、焼き付は後、端子電
極とBN系セラミ、り粉末の付着かないため、品質の面
でも悪影響を及ぼさない。As explained above, in this invention, the terminal electrodes of laminated ceramics and capacitors are sometimes baked by using BN ceramic powder, and the baking is arranged closely on the jig.
Productivity will be approximately doubled. In addition, since the BN-based ceramic powder does not adhere to the terminal electrode after baking, there is no adverse effect on quality.
第1図は、本発明の一実施例に係る積層セラミックコン
デンサの端子電極の焼き付は方法について説明する治具
上に密に並べられたチップ型積層セラミックコンデンサ
の平面図を示し、円内はその部分拡大平面図である。
第2図は、積層セラミ、クフンデンサの概要を示す図で
あり、第2図(a)は、チンプ型積層セラミ、クコンデ
ンサの断面図を示し、第2図(b)はリード付き積層セ
ラミックコンデンサの正面図を示す。
第1図
1112図
(b)FIG. 1 is a plan view of chip-type multilayer ceramic capacitors arranged closely on a jig to explain a method for baking terminal electrodes of a multilayer ceramic capacitor according to an embodiment of the present invention. It is a partially enlarged plan view. Fig. 2 is a diagram showing an outline of a multilayer ceramic capacitor, Fig. 2(a) is a cross-sectional view of a chimp type multilayer ceramic capacitor, and Fig. 2(b) is a multilayer ceramic capacitor with leads. shows a front view. Figure 1112(b)
Claims (1)
形成する際に、 導電塗料が被着された多数の電子部品を窒化硼素系のセ
ラミック粉末を介在して密に配列して焼き付けることを
特徴とする電子部品の端子電極形成方法。[Claims] When terminal electrodes are formed by baking conductive paint on the electronic component body, a large number of electronic components coated with conductive paint are densely arranged with boron nitride ceramic powder interposed therebetween. A method for forming terminal electrodes of electronic components, characterized by baking.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27017888A JPH04164306A (en) | 1988-10-26 | 1988-10-26 | Terminal electrode formation method of electronic part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27017888A JPH04164306A (en) | 1988-10-26 | 1988-10-26 | Terminal electrode formation method of electronic part |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04164306A true JPH04164306A (en) | 1992-06-10 |
Family
ID=17482612
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27017888A Pending JPH04164306A (en) | 1988-10-26 | 1988-10-26 | Terminal electrode formation method of electronic part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04164306A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19523798A1 (en) * | 1994-07-05 | 1996-01-11 | Murata Manufacturing Co | Manufacturing ceramic electronic components, e.g. monolithic capacitors |
WO2012132661A1 (en) * | 2011-03-28 | 2012-10-04 | 日本碍子株式会社 | Ceramic device and piezoelectric device |
-
1988
- 1988-10-26 JP JP27017888A patent/JPH04164306A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19523798A1 (en) * | 1994-07-05 | 1996-01-11 | Murata Manufacturing Co | Manufacturing ceramic electronic components, e.g. monolithic capacitors |
DE19523798C2 (en) * | 1994-07-05 | 1998-12-24 | Murata Manufacturing Co | Process for the production of ceramic electronic parts |
WO2012132661A1 (en) * | 2011-03-28 | 2012-10-04 | 日本碍子株式会社 | Ceramic device and piezoelectric device |
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