JPH04163797A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable read at high speed by setting the potential of one bit in a bit line pair including bit lines, to which memory transistors selected on the basis of ON-OFF of the memory transistor selected are connected, at levels higher or lower than that of the other bit line. CONSTITUTION:A bit-line connecting signal BLT, a load signal LTR, a word line WL1 and a dummy word signal DWLL are made to fall to L while a sense signal SO (-SO) is made to rise from (fall) to H(L). Consequently, a sense amplifier 21 is brought to an active state, and the potential difference between sense lines L1, L2 is detected, and amplified at H and L levels. The H and L levels of the sense lines L1, L2 amplified by the sense amplifier 21 are given to I/O line to I/O and -I/O through transistors Q1, Q2 finally, thus reading the stored content of a memory transistor MQ1. Accordingly, read at high speed as the page mode read of a DRAM is enabled.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

The present invention relates to a nonvolatile semiconductor memory device including a plurality of electrically writable and erasable memory transistors having floating gates. [0002]

[Conventional technology]

FIG. 7 is a cross-sectional view showing a memory transistor of a conventional flash (-batch erase type) EEPROM. In the figure, 11 is a P-type semiconductor substrate, 12 is an N-type drain diffusion region, and 13 is an N-type source diffusion region. These drain diffusion regions 12. A surface portion of the P-type semiconductor substrate 11 between the source diffusion regions 13 is defined as a channel region 18 . Also, 14 is a floating gate,
Source diffusion region 13 from above a part of drain diffusion region 12
A gate oxide film 15 is formed over a portion of the gate oxide film 15 with a thickness that allows tunneling. Further, a control gate 16 is formed on the floating gate 14 with a gate oxide film 17 interposed therebetween. Although not shown in FIG. 7, the bit line is electrically connected to the drain diffusion region 12, and the word line is electrically connected to the control gate 16. [0003] FIG. 8 is a block diagram showing a flash EEPROM using the memory transistor shown in FIG. 7. As shown in the figure, the drains 12 (see FIG. 7) of the memory transistors 1 (only one is shown in the figure) arranged in a matrix in the memory array 10 are connected to the bit lines 2, and the control gates 16 (see FIG. 7) are connected to the bit lines 2. ) to word line 3 and source 1
3 (see FIG. 7) is connected to a source line (not shown). One end of the bit line 2 is connected to the Y gate 4, one end of the word line 3 is connected to the X decoder 5, and the source line is connected to a source line switch 19. Also, Y gate 4 is
On/off is controlled by a decoder 6, and activation/inactivation of the word line 3 is controlled by an X decoder 5 during writing and reading. The control by the X decoder 5 and the X decoder 6 described above is performed based on the address output of the address buffer 7. On the other hand, the Y gate 4 is connected to the sense amplifier 8a and the write circuit 8.
b is also connected to the sense amplifier 8a and the write circuit 8.
b are both connected to the human output buffer 9. Note that the operation timing of each of the above-described components 5, 6, 7.8a, 8b, 9, and 19 is controlled by a control circuit 20. [0004] In such a configuration, erasing of the memory transistor 1 is performed as follows. Erase memory array 10
This is done for all memory transistors 1 in the memory transistor 1 by applying a high voltage from the source line switch 19 to the source diffusion region 13 of the memory transistor 1 and setting the control gate 16 to the ground level (the drain region 12 Floating is fine). [0005] With this setting, a high electric field is applied to the gate oxide film 15 and the electrons accumulated in the floating gate 14 are extracted to the source diffusion region 13 due to a tunneling phenomenon, thereby lowering the threshold value of the memory transistor (IV
degree). That is, the state is the same as that of the EP ROM after being erased by ultraviolet rays. [0006] On the other hand, nonvolatile writing is performed as follows. First, a high voltage is applied by a high voltage generating means (not shown) to the control gate 16 and drain diffusion region 12 of the memory transistor 1 connected to the word line 3 and bit line 2 selected by the X decoder 5 and the X decoder 6, Source line switch 19 sets source diffusion region 13 to ground level. [0007] With this setting, electrons flowing through the channel region 18 of the memory transistor are accelerated by the drain-source voltage in the pinch-off region near the drain diffusion region 12, and become hot electrons due to avalanche collapse due to the electric field generated by the control gate 16. By being injected into the floating gate 14 across the energy gap of the gate oxide film 15, the threshold voltage of the memory transistor becomes high (7V or more). Note that the high voltage source generated by the high voltage generating means and the source line switch 19 is supplied from the outside. This is because the current flowing through the bit line during writing is 1 mA to 5 mA, so a high voltage source such as a charge pump has insufficient current supply ability. [0008] As described above, when a write operation is performed, the threshold of the memory transistor 1 becomes 7V or more, and when an erase operation is performed, the threshold of the memory transistor 1 becomes about 1. On the other hand, for reading, the activated word line 3 is used to control the control gate 1.
When a voltage of about the power supply voltage Vcc (5V) is applied to the bit line 6, the memory transistor 1 turns on and the source diffusion region 13 is turned on from the bit line 2 (ie, the drain diffusion region 12).
This is done by using a current sensing type sense amplifier 8a to detect whether a current flows across the memory transistor 1 or whether no current flows with the memory transistor 1 remaining in an off state. At this time, when a high potential is applied to the bit line, a high electric field is applied to the gate oxide film 15 between the floating gate 14 and the drain diffusion region 12, and as in the erase operation, the electrons accumulated in the floating gate 14 are transferred to the source due to the tunnel phenomenon. There is a risk that it will be pulled out into the diffusion region 13,
The potential of the drain 12 must be suppressed to 1-2V. Therefore, in order to sense the current flowing through the memory cell while suppressing the drain potential, it is necessary to use a current sense type sense amplifier. In addition, the above writing. Erasing and reading are performed under the control of the control circuit 20. [0009]

[Problem to be solved by the invention]

Conventional flash EEPROMs are configured as described above, and have a large layout area for reading, and cannot be laid out at the bit line pitch and can only be provided at one ratio for a large number of bit lines.
There was a problem in that high-speed reading such as page mode reading of RAM was not possible. [00103] The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a nonvolatile semiconductor memory device that can perform high-speed reading and that can be electrically written and erased. [0011]

[Means to solve the problem]

A nonvolatile semiconductor memory device according to claim 1 of the present invention includes a plurality of memory transistors having floating gates and being electrically programmable and erasable, wherein the memory transistor is connected to at least one bit line constituting a bit line pair. A differential amplification type sense amplifier is connected between the pair of bit lines and detects and amplifies the potential difference between the pair of bit lines; The memory transistor is turned on/off in accordance with 110 of the memory content of the memory transistor.
a read voltage applying means for applying a read voltage at a level that turns off; and a read voltage applying means for applying a read voltage at a level that turns off the bit line pair including the bit line to which the selected memory transistor is connected based on whether the selected memory transistor is turned on or off during reading Of these, the bit line pair potential setting means is provided for setting the potential of one bit line to a higher/lower level than the potential of the other bit line. [0012] Furthermore, the nonvolatile semiconductor memory device according to claim 2 includes a plurality of memory transistors each having a floating gate and which can be electrically written and erased, and the memory transistor is connected to at least one bit line constituting a bit line pair. are connected to each other, a plurality of latches are provided for each bit line pair, and a read operation is performed by generating a potential difference in the bit line pair based on on/off of the selected memory transistor, and controlling the potential difference. a first read operation for selectively storing internal read data obtained by amplifying the internal read data in one of the corresponding plurality of latches; and selectively externally storing the internal read data stored in the plurality of latches. This is performed by a second read operation that is output as read data. [0013] On the other hand, the nonvolatile semiconductor memory device according to claim 3 includes a plurality of memory transistors each having a floating gate and which can be electrically written and erased, and the memory transistor is connected to at least one bit line constituting a bit line pair. are connected to each other, and are provided in units of a plurality of bit line pairs,
A differential amplification type sense amplifier having one terminal and the other terminal detects and amplifies the potential difference between the one terminal and the other terminal, and performs a read operation based on ON/OFF of the selected memory transistor. After creating a potential difference in the bit line pair connected to the memory transistor, each bit line of the bit line pair is selectively connected to one terminal and the other terminal of the sense amplifier, and the sense amplifier This is done by detecting and amplifying the potential difference between one terminal and the other terminal. [0014]

[Effect]

In the non-volatile semiconductor memory device according to claim 1 of the present invention, the bit line pair potential setting means determines whether the selected memory transistor is connected to a bit based on whether the selected memory transistor is turned on or off during reading. Since the potential of one bit line of a bit line pair including a line is set to a higher/lower level than the potential of the other bit line, on/off of the memory transistor is reflected as a potential difference between the bit line pair. [0015] Furthermore, in the non-volatile semiconductor memory device according to the second aspect, since the internal read data stored in the latches provided in plural bit line units can be selectively outputted as external read data, When internal read data is stored in all multiple latches by the first read operation, the number of data bits that can be read out externally is (number of bit line pairs) x (number of latches provided for each bit line pair). Become. 15 KOKAI Publication No. 4 (63797(9)) [0016] On the other hand, in the nonvolatile semiconductor memory device according to claim 3, the read operation is performed based on the on/off of the selected memory transistor, and the bit connected to the selected memory transistor. After generating a potential difference in the line pair, selectively connecting each bit line of the bit line pair to one terminal and the other terminal of a differential amplification type sense amplifier provided for each of the plurality of bit line pairs, Since this is performed by detecting and amplifying the potential difference between one terminal and the other terminal using the sense amplifier, one differential amplification type sense amplifier can be shared by a plurality of bit line pairs. [0017]

【Example】

FIG. 1 shows a flash E E which is a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing the periphery of a memory transistor of a PROM. As shown in the figure, the memory transistor MQIM
The control gates of Q2 are both connected to word line WLI, and the control gates of memory transistors MQ3 and MQ4 are both connected to word line WL2. On the other hand, the drains of memory transistors MQI and MOS are both connected to bit line BL1, and memory transistor MQ2
, MQ4 are both connected to the bit line BL2. These bit lines BLI and BL2 constitute one bit line pair. Further, the sources of all memory transistors MQI to MQ4 are connected to source line SL. [0018] Word lines WLI and WL2 are both connected to the row decoder 22, and bit line BLI is connected to NMOS transistor Q9, sense line L1 and NMO3) transistor Ql (Y gate).
bit line BL2 is connected to NMO5) transistor QIO, sense line L2 and NMO
3) Connected to the inverted I10 line bar I10 via transistor Q2 (Y gate). The source line SL is connected to a source line switch 23. In addition, the drains of dummy transistors DQI and DQ3 in the write state (“1” memory, threshold 2V) are connected to the bit line BLI, respectively, and the drains of dummy transistors DQI and DQ3 in the write state (“1” memory, threshold 7V or more) and the erase state (“1” memory, threshold 2V) are connected to the bit line BL2. The drains of dummy transistors DQ2 and DQ4 in the state and write state are connected, respectively. And dummy transistor DQ1
A dummy word signal DWLL is applied to the control gates of dummy transistors DQ3 and DQ2.
The control gate of Q4 has a dummy word signal DWL.
R is applied. Note that memory transistors MQI to M
The on-resistances of Q4 and the dummy transistors DQ1 to DQ4 are all the same R3. [0019] A flip-flop type sense amplifier 21 consisting of two CMOS inverters 1 and 2 cross-connected is inserted between the sense lines L1 and L2, and when in an active state, the node N1 on the sense line L1 and The potential difference between the sense line L2 and the node N2 is detected and amplified to H and L levels, respectively. The activation/inactivation of this sense amplifier 21 is determined by the sense signal SO.
Based on H/L (L/H) of (bar SO) <PMO3)
transistor Q3 and NMO5) transistor Q4 on/off
Controlled by OFF. [00201 In addition, an NMO3 load transistor Q5 is connected to the sense line L1.
．． The source of Q6 is connected, and the sense line L2 is connected to NMO5.
Load transistor Q7. The source of Q8 is connected. A load signal LTO is applied to the gates of load transistors Q5 and Q7, and a reset signal R5 is applied to their drains.
The output of CMOS inverter 3 which inputs T is applied. Further, load signals LTL and LTR are applied to the gates of the load transistors Q6 and Q8, respectively, and the drains are connected to the power supply. Note that by setting the transistor sizes of load transistors Q6 and Q8 to be larger than that of load transistors Q5 and Q7, on-resistance R1 of load transistors Q6 and Q8 is made smaller than on-resistance R2 of load transistors Q5 and Q7. . Further, the output CD◯ of the column decoder is applied to the gates of transistors Q1 and Q2, and the bit line connection signal BLT is applied to the gates of transistors Q9 and QIO. [0021] In the flash EEPROM having such a configuration, erasing and writing to the memory transistors are performed in the same manner as in the past. On the other hand, reading is performed as follows. [0022] FIG. 2 is a timing diagram showing a read operation for the memory transistor MQI (encircled in FIG. 1). The read operation will be explained below with reference to the same figure. [0023] First, the bit line connection signal BLT, reset signal R3T, and load signal LTO are set to H state (5v). Then, the output of inverter 3 becomes L (OV) and load transistor Q5 (ON resistance R2) Q7 (ON resistance R2)
By turning on transistors Q9 and Q10, bit line pairs BLI and BL2 and sense line pairs 1 and L
2 is initialized to L level. [0024] Then, after lowering the reset signal R3T to L and setting the output of the inverter 3 to H, the load signal LTR and the word line W
LI and dummy word signal DWLL are raised to H. Then, the load transistor Q8 (ON resistance R1
) and the dummy transistor DQ2 in the "1" storage state.
(ON resistance R3) is turned on. [0025] Memory transistor MQI is in write state (BL in FIG.
Since the memory transistor MQI is in the OFF state when I ``O''), the H level of the output of the inverter 3 is applied via the load transistor Q5.
Bit line BLI is charged towards 5v. [0026] Furthermore, the memory transistor MQI is in the erased state (B in FIG.
When LI is “1”), memory transistor MQI (
Since the on-resistance R3) is in the on state, the bit line BL1
The potential of V1 moves toward the potential V1 shown by the following equation (I). [0027] ■1=5・R3/ (R2+R3)...(I) On the other hand,
Memory transistor MQ2 is in write state (BL in FIG.
Since the memory transistor MQ2 is in the off state when the bit line BL2 is "0"), the bit line BL2 goes to the potential ■2 shown by the following equation (II). [0028] V2=5-R3/ (R12+R3)-( II) However, R12 is a parallel composite resistance of the on-resistance R1 of the load transistor Q8 and the on-resistance R2 of the load transistor Q7, and since R1<R2, R12<(R2/2). [0029] Furthermore, the memory transistor MQ2 is in the erased state (B in FIG. 2).
When L2 is "1''), the memory transistor MQ2 is in the on state, so the bit line BL2 is in the next (III) state.
It moves toward the potential ■3 shown by the formula. [0030] V3=5-R3'/(R12+R3') ・(
III) However, the resistor R3' is a dummy transistor D
It is a parallel combined resistance of on-resistance R3 of Q2 and on-resistance R3 of memory transistor MQ2, and R3' = R3/2
become. Therefore, formula (III) can be transformed into formula (IV). [0031] V3=5-R3/ (2-R12+R3) ・(IV
) (II) and (IV), it is clear that V2>V3. Also, when comparing formula (I) and formula (■v), it is R12 (R2/2), so v3>
[0032] In other words, the potentials of the bit lines BL1 and BL2 based on the memory contents of the memory transistors MQI and MQ2 are as shown in FIG.
A difference occurs as shown in FIG.
bit line BLI if it is in the erased state.
becomes lower than the potential of bit line BL2. At this time,
Since the bit line connection signal BLT is at H level, the transistor Q9. The potentials of the bit lines BL1 and BL2 are transmitted to the sense lines L1 and L2 via Q10. [0033] Then, the bit line connection signal BLT, the load signal LTR, the word line WL1 and the dummy intercostal space +4-163797 (12
) - Raise (lower) the sense signal SO (bar SO) to H (L) at the same time as the word signal DWLL falls to L. Then, the sense amplifier 21 becomes active, detects the potential difference between the sense lines L1 and L2, and amplifies it to H and L levels. That is, if the memory transistor MQI is in the write state, the sense line Ll/L2 is amplified to the H/L level, and if the memory transistor MQI is in the erase state, the sense line Ll/L2 is amplified to the L/H level. At this time, the bit line connection signal BLT is L, and the transistor Q9. Since QIO is off, the potentials of the sense lines L1 and L2 are not transmitted to the bit lines BLI and BL2, and the potentials of the bit lines BLI and BL2 do not rise. [0034] Then, the sense line L amplified by the sense amplifier 21
The H and L levels of L and L2 are finally connected to the transistor Ql.
, via Q2/○ line pair ■10. By giving a dimension to the bar ■/○, the memory transistor MQ1's memory transistor MQ1 is
It is possible to read out the contents. [0035] In this way, by creating a configuration that allows the use of the flip-flop type sense amplifier 21, which is easy to integrate into the sense amplifier for reading flash EEPROM, it is possible to ) Since a sense amplifier can be provided, high-speed reading can be performed like page mode reading of DRAM. [0036] In the first embodiment, the load transistors Q5. Although this is done via Q7, it is also possible to provide a separate transistor exclusively for reset. Further, although a flip-flop type sense amplifier is shown as a read sense amplifier, any differential amplification type sense amplifier such as a current mirror sense amplifier can be used instead. In addition, the drain voltage and gate voltage of load transistors 05 to Q8 are not necessarily set to the power supply voltage (H level).
There's no need to do it. In addition, the conductivity type of these load transistors 05 to Q8 may be P type. [0037] FIG. 3 shows a flash EEP, which is a second embodiment of the present invention.
FIG. 2 is a circuit diagram showing the periphery of a memory transistor of a ROM. As shown in the figure, bit line BLI is connected to NMOS transistor Q9, sense line L1 and NMO3) transistor Ql.
(Y gate) connected to ■/○ line ■/○, bit line BL2 is NMO3) transistor Q10, sense line L
2 and NMO3) is connected to the inverted I10 line I10 via the transistor Q2 (Y gate). [0038] A sense amplifier 21A having the same configuration as the sense amplifier 21 shown in the first embodiment (see FIG. 1) connects the sense line L1 via the transfer gate 31A and the sense line L2 via the transfer gate 31B. A sense amplifier 21B having the same configuration as the sense amplifier 21A is connected to the sense line L1 via the transfer gate 32A.
It is connected to sense line L2 via transfer gate 32B. [0039] The activation/inactivation of the sense amplifier 21A is determined by the sense signal S1.
It is controlled by the on/off of PMOS transistor Q3A and NMO3) transistor Q4A based on H/L (L/H) of (bar 81), and the activation/off of sense amplifier 21B.
Inactivation is H/L (L/L) of sense signal S2 (bar S2).
PMOS transistor 03B and NMO3 based on H)
) Controlled by turning on/off transistor Q4B. Further, a selection signal SEI is applied to each of the transfer gates 31A and 31B, and a selection signal SEI is applied to each of the transfer gates 31A and 31B.
A selection signal SE2 is applied to each gate. [0040] In addition, 24 is a column decoder, 25 is an I10 line pair/○
This is the main amplifier that increases the potential difference between , BAAE and ○. [0041]Although not shown, the internal configuration of the memory array 40 (including load transistors, dummy transistors, etc.) is exactly the same as that of the first embodiment. Flash EE in the second embodiment of such a configuration
In PROM, erasing and writing to memory transistors are performed in the same manner as in the past. On the other hand, reading is performed almost in the same manner as in the first embodiment. [0042] Only points different from the first embodiment will be described below. Bit line B
A memory transistor connected to LI (M in Figure 1)
Ql, MQ3, etc.), the first
A potential difference is generated between the bit line pair BLI and BL2 according to the memory contents of the memory transistors in the same manner as in the embodiment, and the potential difference is transferred to the sense lines 1 and L2, and then the bit line connection signal BLT and the load signal are generated. LTR, word line WL
At the same time as I and the dummy word signal DWLL fall to L, the sense signal SL (bar 81) rises (lowers) to H (L), and the selection signal SEL rises to H. Then, the sense amplifier 21A becomes active, and the sense line L
1. Detects the potential difference between L2 and amplifies it to HL level. At this time, the selection signal SE2 is set to L. As a result, the activated sense amplifier 21A is electrically connected between the sense lines LL and L2, and the inactive sense amplifier 21B is electrically disconnected from the sense lines LL and L2, so that it is not connected to the bit line BLI. The stored contents of the memory transistor are latched only by the sense amplifier 21A as internal read data. [0043] On the other hand, when reading the memory contents of the memory transistors (MQ2, MQ4, etc. in FIG. 1) connected to the bit line BL2, bits are read out according to the memory contents of the memory transistor in the same manner as in the first embodiment. A potential difference is generated between the line pair BLI and BL2, and the potential difference is applied to the sense line pair, L2.
After transferring the bit line connection signal BLT and load signal LT to
R, word line WL1 and dummy word signal DWLL to L
At the same time, sense signal S2 (bar S2)
is raised (lowered) to H (L), and the selection signal SE2 is raised to H. Then, the sense amplifier 21A becomes active, detects the potential difference between the sense lines L1 and L2, and amplifies it to H and L levels. At this time, the selection signal SE1 is set to L. As a result, the active sense amplifier 21B connects the sense line 1. It is electrically connected between L2 and sense amplifier 2.
1A is the sense line LL. Since it is electrically cut off from L2, the storage contents of the memory transistor connected to bit line BL2 are latched only in sense amplifier 21B as internal read data. JP-A-4-+637S7 (16) [0044] In this way, the first read operation in which the contents of the memory transistors connected to the bit lines BLI and BL2 of the sense amplifiers 21A and 21B, respectively, are internally read and latched as data. will be held. [0045] After that, by turning on the transistors Ql and Q2 and sequentially setting the selection signals SEL and SF3 to H, the internal read data latched in the sense amplifiers 21A and 21B is sequentially transferred to the sense lines LL and L2 and the transistor Q.
l, I10 wire pair via Q2 10. A second read operation is performed by applying the external read data to bar I10. [0046] In this way, in the second embodiment, the read operation is performed using the two sense amplifiers 21A having the latch function, using the stored contents of the memory transistor as internal read data.
, 21B, and a second read operation that selectively outputs the internal read data latched by the sense amplifiers 21A and 21B as external read data. Since a sense amplifier with a latch function can be provided in each line (one per bit line), the number of readable bits in page mode read operation is twice that of the first embodiment. effective. [0047] Furthermore, by increasing the number of sense amplifiers with a latch function between the bit line pairs to three or more, the number of readable bits in page mode read operation can be further increased. [0048] FIG. 4 shows a flash EEP that is a third embodiment of the present invention.
FIG. 2 is a circuit diagram showing the periphery of a memory transistor of a ROM. As shown in the figure, the third embodiment has almost the same configuration as the second embodiment, except that the sense amplifiers 21A and 21B are always set to an active state, and the sense lines LL and L2 are connected to each other. The difference is that a sense amplifier 50 is further provided. [0049] The activation/inactivation of the sense amplifier 50 is determined by the sense signal SA (
Based on H/L (L/H) of bar SA) <, PMOS)
transistor 33 and NMO3) transistor 34 on/off
It is controlled by turning off, and when the transistor 33 is turned on, ■c
c/■1. The output of the switching circuit 26 (V or V
) is applied to the sense amplifier 50, and the cc of the transistor 34 is
pp When on, the ground level is applied to the sense amplifier 50. [0050] With this configuration, erasing and writing to the memory transistors are performed in the same manner as in the prior art. On the other hand, reading is performed almost in the same manner as in the first embodiment. [0051] Only points different from the first embodiment will be described below. Bit line B
A memory transistor connected to LI (M in Figure 1)
When reading large contents such as QI and MQ3, a potential difference is generated between the bit line pair BLI and BL2 according to the stored content of the memory transistor in the same manner as in the first embodiment, and the potential difference is After transferring the potential difference between the sense lines 1 and L2, the sense amplifier 50 amplifies the potential difference between the sense lines 1 and L2, and then the selection signal SE! and SF3
By setting them to H and L, the amplified potential difference between the sense lines LL and L2 is transferred as internal read data to the sense amplifier 21A and latched. [0052] On the other hand, when reading the memory contents of the memory transistors (MQ2, MQ4, etc. in FIG. 1) connected to the bit line BL2, bits are read according to the memory contents of the memory transistor in the same manner as in the first embodiment. A potential difference is generated between the line pair BLI and BL2, and the potential difference is applied to the sense line pair, L2.
After transferring the voltage to the sense line, the sense amplifier 50 amplifies the potential difference between the sense lines 1 and L2, and then the selection signal SE
By setting L and SF3 to L and H, the amplified potential difference between the sense lines Ll and L2 is transferred as internal read data to the sense amplifier 21B and latched. [0053] In this way, bit lines BLI and B1 open +4-1f; 3797 (1
7) A first read operation is performed to latch the storage contents of the memory transistor connected to L2 as internal read data. [0054] Thereafter, by turning on the transistors Ql and Q2 and sequentially setting the selection signals SEL and SF3 to H, the internal read data latched by the sense amplifiers 21A and 21B is sequentially transferred to the sense lines LL and L2 and the transistor Ql. , Q2 to the I10 line pair I10 as external read data, thereby performing a second read operation. [0055] As described above, in the third embodiment, similarly to the second embodiment, the read operation is performed by selecting the two sense amplifiers 21A and 21B having the latch function as an internal read operation of the stored contents of the memory transistor. The first internal transfer
By performing this read operation and the second read data that selectively outputs the internal read data latched by the sense amplifiers 21A and 21B as external read data, a sense amplifier having a latch function can be created for each bit line. Therefore, the number of readable bits in page mode read operation is 2 in the first embodiment.
It has a double effect. [0056] Furthermore, the sense amplifiers 21A and 21B only need to have a latch function, and there is no need to satisfy high-speed sensing capability for minute potential differences, so their circuit design (transistor size, etc.) is different from that of the second embodiment. sense amplifier 21A in
and 21B. [0057] Furthermore, by providing the Vcc/VPP switching circuit 26, the H level of the sense amplifier 50 can be selected from the power supply voltage V or the high voltage ■PP, so that the sense C amplifier 50 can be used as a column latch during writing. It can also be used instead. [0058] Furthermore, by increasing the number of latches between the bit line pairs to three or more, the number of bits that can be read in the page mode read operation can be further increased, as in the second embodiment. [0059] FIG. 5 shows a flash EEP according to a fourth embodiment of the present invention.
FIG. 2 is a circuit diagram showing the periphery of a memory transistor of a ROM. As shown in the figure, bit line BLI is connected to NMOS transistor Q11, sense line L1 and NMOS transistor Q
The bit line BL2 is connected to the I10 line I10 through the NMO5) transistor Q12, the sense line L2 and the NMO3) transistor Q2 (Y gate). Bit line BL3
is NMO3) transistor Q13, sense lines L1 and NM
O3) Through transistor Ql (Y gate) /○ line■
/○, bit line BL4 is connected to NMO3) transistor Q14, sense line L2 and NMO3) transistor Q2
(Y gate) is connected to the inverted I10 line bar ■/○. A selection signal SA2, which is an output signal of the selection circuit 27, is applied to the gates of the transistors Qll and Q12, and a selection signal SA2, which is an output signal of the selection circuit 27, is applied to the gates of the transistors Q13 and Q14. [0060] The selection circuit 27 decodes a part of the external address signal (not shown) and selectively outputs the selection signals SAI, SA2, SA2.
and set SB2 to H level. [0061] Furthermore, a sense amplifier 51 is provided between the sense lines LL and L2, and the activation/deactivation of the sense amplifier 51 is determined by the sense signal S.
2MO based on H/L (L/H) of A (bar SA)
3) Controlled by turning on/off transistor 33 and NMO3) transistor 34. [0062] A sense amplifier 21A having the same configuration as the sense amplifier 21 shown in the first embodiment (see FIG. 1) connects the sense line L1 via the transfer gate 31A and the sense line L2 via the transfer gate 31B. A sense amplifier 21B having the same configuration as the sense amplifier 21A is connected to the sense line L1 via the transfer gate 32A.
It is connected to sense line L2 via transfer gate 32B. [0063] The activation/inactivation of the sense amplifier 21A is determined by the sense signal S1 (
Based on the H/L (L/H) of bar 81), the activation/inactivation of sense amplifier 21B is controlled by the on/off of transistor Q3A (PMO3) and transistor Q4A (NMO3), and the activation/inactivation of sense amplifier 21B is controlled by the H/L (L/H) of H/L (L/H
) based on <PMO3) transistor Q3B and NMO5)
Controlled by turning on/off transistor Q4B. In addition, each gate of transfer game) 31A, 31B has
A selection signal SAI, which is an output signal of the selection circuit 27, is applied to each gate of the transfer gates 32A and 32B. [0064] Note that 24 is a column decoder, and 25 is a ■/○ line pair I10.
．． This is a main amplifier that amplifies the potential difference between bar I10. [0065]Although not shown, the internal configuration of the memory array 40 (including load transistors, dummy transistors, etc.) is exactly the same as that of the first embodiment. In this configuration, erasing and writing to the memory transistors are performed in the same manner as in the prior art. On the other hand, reading is performed almost in the same manner as in the first embodiment. [0066] Only points different from the first embodiment will be described below. Bit line B
When reading the memory contents of the memory transistor connected to LI or SB2, bit line pair BL is read out according to the memory contents of the memory transistor in the same manner as in the first embodiment.
After creating a potential difference between bit lines I and BL2, the selection signals SA2 and SB2 are set to H and L, respectively, thereby changing the potential difference between the bit line pair BLI and BLZ to the sense lines Ll and L.
2. Then, the sense amplifier 51 amplifies the potential difference between the sense lines LL and L2. Thereafter, by setting the selection signals SAI and SB1 to H and L, respectively, the sense line Ll amplified by the sense amplifier 51
, L2 is transferred to the sense amplifier 21A as internal read data and latched. [0067] On the other hand, when reading the storage contents of the memory transistor connected to bit line BL3 or BL4, bit line pair BL3. After creating a minute potential difference between the bit line pairs BL3.BL4, the selection signals SA2 and SB2 are set to L and H, respectively. The potential difference between BL4 is transmitted to sense lines LL and L2. And sense lines Ll, L2
The sense amplifier 51 amplifies the potential difference between the two. Thereafter, by setting the selection signals SAI and SBI to L and H, respectively, the amplified potential difference between the sense lines LL and L2 is transferred as internal read data to the sense amplifier 21B and latched. [0068] In this way, bit line pairs BLI, BL2 and bit line pairs BL3 . BL
A first read operation is performed in which the stored contents of the memory transistor connected to the memory transistor 4 are latched as internal read data. [0069] Thereafter, by turning on the transistors Ql and Q2 and sequentially setting the selection signals SEL and SB2 to H, the internal read data latched by the sense amplifiers 21A and 21B is sequentially transferred to the sense lines Ll and L2 and the transistor Q1. ．． Work via Q2/○ line pair work 10. By being given to bar I10 as external read data, the second
A read operation is performed. [00703 As described above, in the fourth embodiment, one sense amplifier (sense amplifier 51) and two latches (sense amplifiers 21A and 21B) are provided for every two bit line pairs.
), the sense amplifiers 51.21A and 21B can be provided relatively easily even by miniaturizing the pitch of the bit lines. Therefore, it is effective in cases where it is difficult to form even a differential sense amplifier at the bit line pitch due to the ultra-miniaturization of the bit line pitch as memory capacity increases. [0071] Since there is no need to satisfy high-speed sensing capability for minute potential differences, the circuit design (transistor size, etc.) is easier than that of the sense amplifiers 21A and 21B in the second embodiment. [0072] In addition, in the fourth embodiment, similarly to the second and third embodiments, the read operation is performed using two sense amplifiers 21A and 21B having a latch function, using the contents stored in the memory transistor as internal read data. Selective internal transfer first
By performing this read operation and a second read operation that selectively outputs the internal read data latched by the sense amplifiers 21A and 21B as external read data, it is possible to have a latch function for each bit line pair. Since a sense amplifier is provided, the number of readable bits in the page mode read operation can be maintained at the level of the first embodiment. [0073] FIG. 6 shows a flash EEP which is a fifth embodiment of the present invention.
FIG. 2 is a circuit diagram showing the periphery of a memory transistor of a ROM. As shown in the figure, bit line BLI has NMOS transistor size, sense line L1 and NMO3) transistor Q
Bit line BL2 is connected to NMO3) transistor Q12, sense line L2 and NMO3) transistor Q2 (Y gate), and bit line BL2 is connected to NMO3) through resistor Q2 (Y gate). /○, bit line BL3
is NMO3) transistor Q13, sense lines L1 and NM
O3) Connected to I10 line /○ via transistor Ql (Y gate), bit line BL4 is connected to NMOS transistor Q14, sense line L2 and NMO3) transistor Q2
(Y gate) to the inverted I10 line bar I10. A selection signal SA, which is an output signal of the selection circuit 27, is applied to the gates of the transistors Qll and Q12.A selection signal SA, which is an output signal of the selection circuit 27, is applied to the gates of the transistors Qll and Q12.
A selection signal SB2 which is an output signal of is applied. [0074] The selection circuit 28 decodes a part of the external address signal (not shown) and generates selection signals SAI to SD1, SA2 and S.
B2 is selectively set to H level. [0075] Similarly to the fourth embodiment, the sense amplifier 21A is connected to the sense line L1 via the transfer gate 31A and to the sense line L2 via the transfer gate 31B, and has the same configuration as the sense amplifier 21A. Sense amplifier 21B is connected to sense line L1 via transfer gate 32A and to sense line L2 via transfer gate 32B, and sense amplifiers 21C and 21D having the same configuration are connected to transfer gate 33, respectively.
It is connected to the sense line L1 via A and 34A, and to the sense line L2 via transfer gates 33B and 34B, respectively. The activation/inactivation of the sense amplifiers 21A to 21D is based on the H/L (L/H) of the sense signals S1 to S4 (bar S1 to bar 34), respectively.
Controlled by turning on/off Q4D. In addition, a selection circuit 2 is provided at each gate of transfer games 31A and 31B.
The selection signal SAI which is the output signal of the transfer gate 32A and the selection signal SA2 is applied to each gate of the transfer gate 32A and 32B.
A selection signal SA3 is applied to each gate of transfer gates 33A and 33B, and a selection signal SA4 is applied to each gate of transfer gates 34A and 34B. [0076] In addition, 24 is a column decoder, 25 is a ■/○ line pair ■10
．． This is a main amplifier that amplifies the potential difference between bar I10. [0077]Although not shown, the internal configuration of the memory array 40 (including load transistors, dummy transistors, etc.) is exactly the same as that of the first embodiment. In this configuration, erasing and writing to the memory transistors are performed in the same manner as in the prior art. On the other hand, the read operation is performed almost in the same manner as in the first embodiment. [0078] Only points different from the first embodiment will be described below. Bit line B
When reading the memory contents of the memory transistor connected to LI, a potential difference is generated between the bit line pair BLI and BL2 according to the memory contents of the memory transistor in the same manner as in the first embodiment, and then the selection signals SA2 and By setting SB2 to H and L, respectively, bit line pair BLI
, BLZ is transmitted to sense lines LL and L2. [0079] Thereafter, by setting the selection signals SAI, SBI, SC1 and SDI to H, L, L and L, the sense amplifier 21A amplifies the potential difference between the sense lines LL and L2 and latches it as internal read data. [0080] On the other hand, when reading the memory contents of the memory transistor connected to the bit line BL2, bit line pair B
After creating a potential difference between LI and BL2, the selection signal SA2
By setting and SB2 to H and L, respectively,
The potential difference between the bit line pair BLI and BLZ is expressed as the sense line LL,
Transmit to L2. [0081] Thereafter, by setting the selection signals SAI, SBI, SC1 and SDl to LSH, L and L, the sense amplifier 21B amplifies the potential difference between the sense lines Ll and L2 and latches it as internal read data. [0082] Furthermore, when reading the memory contents of the memory transistor connected to the bit line BL3, the bit line pair B
L3. After creating a potential difference in BL4, the selection signal SA2
and SB2 are set to L and H, bit line pair BL3. The potential difference between BL4 is transmitted to sense lines LL and L2. [0083] Thereafter, by setting the selection signals SAI, SBI, SCI, and SDl to L, H, and L, the sense amplifier 21C amplifies the potential difference between the sense lines LL and L2 and latches it as internal read data. [0084] On the other hand, when reading the memory contents of the memory transistor connected to the bit line BL4, bit line pair B
L3. After creating a potential difference in BL4, the selection signal SA2
and SB2 are set to L and H, bit line pair BL3. The potential difference between BL4 is transmitted to sense lines LL and L2. [0085] Thereafter, by setting the selection signals SAI, SBI, SC1 and SDl to L, L and H, the sense amplifier 21D amplifies the potential difference between the sense lines Ll and L2 and latches it as internal read data. [0086] In this way, the first latches the memory contents of the memory transistors connected to the bit lines BLI to BL4, respectively, to the sense amplifiers 21A to 21D as internal read data.
A read operation is performed. [0087] Thereafter, by turning on the transistors Ql and Q2 and sequentially setting the selection signals SAI to SDI to H, the internal read data latched by the sense amplifiers 21A to 21D is sequentially transferred to the sense lines Ll and L2 and the transistor Q.
l, I10 line pair via Q2 ■10. By being assigned to the bar I10, it is sequentially read out as external read data. [0088] Thus, in the fifth embodiment, a sense amplifier group consisting of four differential amplification type sense amplifiers (sense amplifiers 21A to 21D) is provided, one set for every two bit line pairs. Therefore, the sense amplifiers 21A to 21D can be provided relatively easily by miniaturizing the bit line pitch. [0089] Further, in the fifth embodiment, the read operation is performed using four sense amplifiers 21A to 21 having a latch function, using the stored contents of the memory transistor as internal read data.
A first read operation in which the internal read data is selectively transferred to the sense amplifiers 21A to 21D, and a second read operation in which the internal read data latched in the sense amplifiers 21A to 21D are selectively output as external read data.
As a result, a sense amplifier with a latch function is provided for each bit line, so the number of bits that can be read in the page mode read operation is doubled as in the first embodiment. Note that the present invention is applicable not only to the flash EEPROMs shown in the first to fifth embodiments but also to other EEPROMs. [0091]

【Effect of the invention】

As described above, according to the nonvolatile semiconductor memory device according to the first aspect, when the read voltage applying means applies a read voltage to the control electrode during reading, the memory transistor is activated according to 1/0 of the stored content. Turn on/off. On the other hand, the bit line pair potential setting means sets the potential of one bit line of the bit line pair including the bit line to which the selected memory transistor is connected based on the on/off state of the selected memory transistor at the time of reading. Set it to a higher/lower level than the potential of the other bit line,
The on/off state of the memory transistor is reflected as a potential difference between a pair of bit lines. [0092] As a result, the read operation becomes possible by detecting and amplifying the potential difference between the bit line pairs that occurs during reading using a highly integrated differential amplification type sense amplifier. By providing two differential amplification type sense amplifiers, there is an effect that high-speed reading can be performed like page mode reading of DRAM. [0093] Further, according to the nonvolatile semiconductor memory device according to claim 2, when internal read data is stored in all of the plurality of latches by the first read operation, the internal read data is stored in a plurality of latches provided for each bit line. By selectively and sequentially outputting the read internal data as external read data, the number of data bits that can be read externally is (number of bit line pairs) x (number of latches provided for each bit line pair). Therefore, the number of bits that can be read out at once during high-speed reading can be increased, such as in page mode reading of DRAM. [0094] On the other hand, according to the nonvolatile semiconductor memory device according to claim 3, since a read operation can be performed while a plurality of bit line pairs share one differential amplification type sense amplifier, the pit line pitch is Even in the case of ultra-miniaturization, a differential amplification type sense amplifier can be provided relatively easily.

[Brief explanation of drawings]

[Fig. 1] Fig. 1 shows a flash EEP which is the first embodiment of this invention.
It is a circuit diagram showing a part of ROM.

[Figure 2] Figure 2 shows the timing diagram for the read operation. This is a diagram.

[Fig. 31] Fig. 3 shows a flash EEP which is a second embodiment of this invention.
It is a circuit diagram showing a part of ROM. [Fig. 4] Fig. 4 shows a flash EEP which is a third embodiment of this invention.
It is a circuit diagram showing a part of ROM.

[Fig. 5] Fig. 5 shows a flash EEP which is a fourth embodiment of the present invention.
It is a circuit diagram showing a part of ROM.

[Fig. 6] Fig. 6 shows a fifth embodiment of the present invention, a flash E.
FIG. 2 is a circuit diagram showing part of a PROM.

FIG. 7 is a cross-sectional view showing the structure of a memory transistor of a conventional flash EEPROM.

FIG. 8 is a block diagram showing the configuration of a conventional flash EEPROM.

[Explanation of symbols]

21 (21A-21D) 27.28 50.51 WLI, WL2 L BLI, BL2 Q1~QIO MQI~MQ4 DQ1~DQ4 Flip-flop type sense amplifier selection circuit Flip-flop type sense amplifier word line source line bit line MOS) transistor memory transistor dummy transistor

[Document core]

[Figure 1] drawing

[Figure 2] Japanese Patent Publication No. 4-1f; 3797 (29)

[Figure 3]

[Figure 4]

[Figure 6]

[Figure 7]

[Figure 8]

【Document name】 【Reference number】 【Filing date】 【address】 [Display of incident] 【application number】 [Name of the invention] [Person making the correction] [Relationship with the incident] 【Identification number】 【post code】 [Address or residence] [Name or title] [Representative] [Agent] 【Identification number】 【post code】 [Address or residence] 【patent attorney】 [Name or title]

【telephone number】

[Procedural amendment 1]

[Correction target item name] [Correction target item name] [Correction method] [Contents of correction]

Procedural amendment AP105004 July 18, 1991

Claims (3)

[Claims] 1. A nonvolatile semiconductor memory device comprising a plurality of electrically writable and erasable memory transistors each having a floating gate, the memory transistor being connected to at least one bit line constituting a bit line pair. a differential amplification type sense amplifier that is provided for each bit line pair and detects and amplifies a potential difference between the bit line pairs; read voltage applying means for applying a read voltage at a level that turns on/off the memory transistor according to 1/0 of the memory content; A non-volatile device comprising bit line pair potential setting means for setting the potential of one bit line to a higher/lower level than the potential of the other bit line of the bit line pair including the bit line to which a transistor is connected. Semiconductor storage device. 2. A nonvolatile semiconductor memory device comprising a plurality of electrically writable and erasable memory transistors each having a floating gate, the memory transistor being connected to at least one bit line constituting a bit line pair. , a plurality of latches are provided for each of the bit line pairs, and a read operation is performed by generating a potential difference between the bit line pairs based on on/off of the selected memory transistor and amplifying the potential difference. a first read operation of selectively storing the obtained internal read data in one of the corresponding plurality of latches; and selectively outputting the internal read data stored in the plurality of latches as external read data. A nonvolatile semiconductor memory device characterized in that a second read operation is performed. 3. A nonvolatile semiconductor memory device comprising a plurality of electrically writable and erasable memory transistors each having a floating gate, the memory transistor being connected to at least one bit line constituting a bit line pair. , a differential amplification type sense amplifier that is provided for each of the plurality of bit line pairs, has one terminal and the other terminal, and detects and amplifies the potential difference between the one terminal and the other terminal, and performs a read operation. , after generating a potential difference in the bit line pair connected to the memory transistor based on the on/off state of the selected memory transistor, the respective bit lines of the bit line pair and one terminal and the other of the sense amplifier are connected to each other. 1. A nonvolatile semiconductor memory device, characterized in that said terminals are selectively connected to each other, and said sense amplifier detects and amplifies a potential difference between said one terminal and said other terminal.