JPH04163672A - Logic simulating system - Google Patents

Abstract

PURPOSE:To reduce the number of times of the evaluation of an expression, and to speed up logic simulation by giving a function to keep the propagation of an event waiting. CONSTITUTION:A logic simulator 11 executes the logic simulation of an existing function level and an existing gate level. When the event is generated, an event counter 12 provided for every signal name increases a count value only when the event corresponds to its signal. When the value of the event counter 12 becomes over some definite value, an event propagation stop function module 13 stops the propagation until another event comes to an end, and it suppresses the generation to the event more than necessitated in this way. Thus, the logic simulation can be speeded up.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention is a logic simulation method (conventional technology ) Simulation is a common method for verifying descriptions at the behavioral or structural level. Although some research has been conducted to confirm the validity of descriptions without using simulations, there is nothing practical. There are two types of simulation methods: a compilation method and an event-driven method. The compilation method is a method of converting a circuit into instruction code for a certain machine and directly executing it. Although it has the advantage of fast execution speed, it is difficult to perform simulations that take delay into account, and there are limits to the range that can be handled. On the other hand, the event-driven method represents a circuit in a table format and simulates it while following it.

In conventional event-driven logic simulators, all events that occur at the same simulation time are propagated to logic formulas and netlists that serve as inputs. Figure 3 shows an example of hardware description. In the figure, the values of each signal are A-0, B-1, C-0, D-, respectively.
0,S-0゜T-1,U-0,X-0,Y-1,Z-1
Suppose it was. At this time, an event occurs in C, and C-
When it becomes 1, equation 31 in FIG. 3 is evaluated and becomes A-1.

Then, 232 in Figure 3, which inputs A, is evaluated and S-1
becomes. Then, equation 33 in FIG. 3 is evaluated and becomes X-1. Next, if an event occurs at B at the same simulation time and it becomes B-0, then Equation 31 is evaluated again and it becomes A-0, then Equation 32 is evaluated and it becomes S-O, and then 23
Evaluate 3 and get X-O. In this way, the expression is evaluated every time an event occurs.

(Problem to be Solved by the Invention) According to the conventional example described above, if one formula has many input signals or there is a feedback loop, the same formula will be evaluated over and over again, resulting in logic There was a drawback that the simulation time became long.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic simulation method that can speed up logic simulation.

[Structure of the Invention] (Means for Solving the Problems) The present invention counts the number of events occurring for each signal name at the same simulation time in a logic simulator that verifies descriptions at the behavioral level or structural level through simulation. It is equipped with a counter, and a function module that detects that the counter reaches a predetermined value, suspends event propagation, and allows event propagation when there are no other events. It is characterized by suppressing the occurrence of more events than necessary by executing reading.

(Function) With the configuration described above, when the counter that counts the number of events that occur for each signal name at the same simulation time reaches a certain value or more, the event is stopped from being propagated first. This suppresses the occurrence of unnecessary events and speeds up logic simulation.

As a result, the speed of logic simulation can be increased, and effects such as reduction in computer usage time and reduction in logic simulation cost can be obtained.

(Example) Embodiments of the present invention will be described below using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 11 is a logic simulator, which performs logic simulation at an existing functional level or gate level. Reference numeral 12 is an event counter provided for each signal name, and when an event occurs, the count value is incremented only if it corresponds to that signal. Reference numeral 13 denotes an event propagation stop function module, which stops propagation when the value of the event counter 12 reaches a certain level or more until other events converge.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention. In the figure, reference numeral 21 is a step for clearing the event counters 12, and the values of all event counters 12 are set to 0 before starting the process at simulation time t. Reference numeral 22 is a step for incrementing the event counter 12, and the value of the event counter 12 corresponding to the signal (name) in which an event has occurred is incremented. Reference numeral 23 is a step for determining whether or not to propagate an event, in which it is checked whether the number of events occurring for the same signal (name) exceeds a certain value. Reference numeral 24 is a step to temporarily stop the propagation of the event, and when the number of events that occur exceeds a certain value, the propagation of the event is temporarily stopped, and the event is propagated when there are no other events. do.

The operation of the embodiment of the present invention will be explained below.

The present invention is a functional-level or gate-level logic simulator that follows an event-driven method, and has an event counter 12 for each signal name, as shown in FIG. For example, when simulating three logical expressions as shown in Figure 3, there are 10 signal names, so the event counter 12
Prepare 10 pieces. When the simulation starts, all event counters 12 are set as shown in step 21 of FIG. 2 before starting the processing of each simulation time.
Set the value to O. Next, while simulating the signal A
When an event occurs, event counter 1 for signal A
2 is incremented, and when an event occurs on the signal S, the event counter 12 for the signal S is incremented (step 22).

The same applies when an event occurs on another signal.

If the value of the corresponding event counter 12 exceeds a certain value (for example, 10) due to the increment operation in step 22 (step 23), that event is not propagated and is made to wait until there are no other events (step 23). 24). Specifically, for example, if the number of events that occur for the signal S exceeds 10, stop propagating the event to Equation 33 shown in Figure 3, process other events, and when all events are completed, use this Propagate the event to 233 and evaluate it.

By providing the function of waiting for event propagation as described above, the number of expression evaluations can be reduced.
Logic simulation speed can be increased.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(1) Logic simulation can be accelerated.

(2) Computer usage time can be reduced.

(3) Logic simulation costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention, FIG. 2 is a flowchart showing the operation of the embodiment of the invention, and FIG. 3 is a diagram showing an example of hardware description. 11...Logic simulator, 12...Event counter, 13...Event propagation stop function module. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 A = (B & C)! D -1---(31)S
=(T!U)aA −=−−(32)X, va
zas ------- (33) a' Logical product 1 ' Logical sum <>: Priority order of 2 arithmetic Figure 3

Claims (1)

[Claims] In a logic simulator that verifies behavioral level or structural level descriptions through simulation, there is a counter that counts the number of events that occur for each signal name at the same simulation time, and an event is detected when this counter reaches a predetermined value. It is characterized by having a function module that temporarily stops the propagation of the event and allows the propagation of the event when there are no other events, and by reading and executing this function module, it suppresses the occurrence of more events than necessary. A logical simulation method.