JPH041587U - - Google Patents

Info

Publication number
JPH041587U
JPH041587U JP4060390U JP4060390U JPH041587U JP H041587 U JPH041587 U JP H041587U JP 4060390 U JP4060390 U JP 4060390U JP 4060390 U JP4060390 U JP 4060390U JP H041587 U JPH041587 U JP H041587U
Authority
JP
Japan
Prior art keywords
circuit board
terminals
interconnector
display panel
spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4060390U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4060390U priority Critical patent/JPH041587U/ja
Publication of JPH041587U publication Critical patent/JPH041587U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
JP4060390U 1990-04-18 1990-04-18 Pending JPH041587U (US08063081-20111122-C00044.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4060390U JPH041587U (US08063081-20111122-C00044.png) 1990-04-18 1990-04-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4060390U JPH041587U (US08063081-20111122-C00044.png) 1990-04-18 1990-04-18

Publications (1)

Publication Number Publication Date
JPH041587U true JPH041587U (US08063081-20111122-C00044.png) 1992-01-08

Family

ID=31550531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4060390U Pending JPH041587U (US08063081-20111122-C00044.png) 1990-04-18 1990-04-18

Country Status (1)

Country Link
JP (1) JPH041587U (US08063081-20111122-C00044.png)

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