JPH0415728A - Floating point arithmetic unit - Google Patents

Abstract

PURPOSE:To increase the floating point arithmetic processing speed by calculating an exponent and a mantissa which are normalized based on the exponent selected by an exponent selector and the mantissa selected by a mantissa selector respectively. CONSTITUTION:When the difference is obtained between the exponents of an optional operand to be computed and an optional operand, a mantissa candidate computing element 13 prepares the mantissa adders/subtractors 13a in number corresponding to the difference between both exponents. Then each adder/subtractor 13a performs the mantissa addition/subtraction operations in all combinations possible for each difference between both optional exponents. The addition/subtraction operations are carried out to the mantissas Fa and Fb of a computed operand Fa2<ea> and an operand Fb2<eb> to be inputted in all possible combinations. A mantissa selector 14 inputs the computed value of each adder/subtractor 13a and selects the computed value of the adder/subtractor 13a corresponding to the exponent difference computed by a subtractor 11 out of the computed values of those addres/subtractors 13a as a mantissa fa. A floating point normalizing unit 15 inputs the an exponent ea selected by an exponent selector 12 and the mantissa fa selected by the selector 14 and then outputs a nromalized exponent er and a normalized mantissa Fr. Thus the arithmetic processing speed is increased.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an arithmetic unit, more specifically to a floating point arithmetic unit, to increase the arithmetic processing speed of a denormalized exponent and a denormalized mantissa before being input to a floating point normalizer. A floating point arithmetic unit that can speed up arithmetic processing as a whole device, and a floating point normal that can increase the speed of arithmetic processing for normalizing unnormalized exponents and mantissas and speed up arithmetic processing as a whole device. The purpose of the present invention is to provide a subtracter that calculates the exponent difference between the exponents of an operand and an operand, and an exponent selector that selects the larger exponent based on the exponent difference calculated by the subtracter. , when calculating a difference from both exponents of an arbitrary operand and an operand, a mantissa adder/subtractor is provided for each possible difference between the two exponents, and each adder/subtractor calculates the mantissas of all possible combinations for each difference. A mantissa candidate calculator that performs addition and subtraction on both the mantissas of the input operand and the operand, and a mantissa of the adder/subtractor that corresponds to the exponent difference calculated by the subtracter from within the adder/subtracter of the mantissa candidate calculator. Consisting of a mantissa selector that selects a mantissa obtained by addition and subtraction, and a floating-point normalizer that operates a normalized exponent and mantissa based on the exponent selected by the exponent selector and the mantissa selected by the mantissa selector, and A detection encoder detects the bit length or the value at a predetermined bit position until the non-normalized mantissa consisting of multiple bits reaches a value other than 0 counted from the most significant bit, and the detection result detected by the detection encoder is used as the shift amount. A shifter that shifts the unnormalized mantissa by digits to make it a normalized mantissa, and an exponent candidate operation that is composed of a large number of calculators to calculate all the exponents expected when the unnormalized exponent is normalized. and an exponent selector that selects, as a normalized exponent, an exponent corresponding to the number of bits detected by the detection encoder from among the exponents determined by the exponent candidate calculator.

[Industrial Field of Application] The present invention relates to an arithmetic device, and more particularly to a floating point arithmetic device.

In recent years, there has been a demand for faster floating point arithmetic processing speeds in computer systems.

Therefore, it is important to increase the speed of processing in each calculation unit in the floating-point calculation device.

[Prior Art] Conventionally, in a floating point arithmetic device, for example, the operand Fa
When adding or subtracting 2°" and the operational number Fb 2°5, the exponent ea and the exponent eb are subtracted by the exponent subtractor I as shown in FIG. The exponent selector 2 inputs the exponent ea and the exponent eb, and selects the larger exponent (ea >
eb). On the other hand, the mantissa selector 3 transfers the mantissa with a small exponent (Fb in this case) to the barrel shifter 4.
Then, a mantissa having a large exponent (Fa in this case) is output to the mantissa adder/subtractor 5. The barrel shifter 4 shifts the mantissa Fb by the exponent difference (=eb-ea), equalizes it, and outputs it to the mantissa adder/subtractor 5. The mantissa adder/subtractor 5 adds and subtracts the equalized mantissas Fa and Fb fa(=Fa+:Fb2 (
eb-sat =F, 2-ac). and,
The exponent ea selected by the exponent selector 2 and the mantissa adder/subtractor 5
The mantissa fa from is output to the floating point normalizer 6 and normalized.

As shown in FIG. 7, the floating point normalization device 6 is composed of an exponent subtracter 6a, a detection encoder 6b, and a barrel shifter 6C. (=Fr 2-”
), counting from the most significant bit, find the numerical value (digit) corresponding to the bit position where "l" is first detected, and calculate the value (
=-ec) is output to the exponent subtractor 6a and barrel shifter 6c.

The exponent subtracter 6a subtracts the non-normalized exponent ea from the exponent selector 2 by the value (=-ec) to obtain the normalized exponent e.
Find r (=ea + ec).

On the other hand, the barrel shifter 6c shifts the non-normalized mantissa fa (=Fr 2°e) calculated by the mantissa adder/subtractor 5 to the right by the numerical value (digit) ac calculated by the detection encoder 6b, and converts it into a normalized mantissa (=Fr ) are looking for.

Thus, Fa2”±F b 2 ”= F r 2
” floating point operations are being performed.

[Problem to be Solved by the Invention] However, as described above, in the floating point arithmetic unit, as a process to obtain the denormalized mantissa, first the exponent difference is obtained, and then the mantissa is selected and shifted according to the exponent difference. This method requires a large number of processing stages, which poses a problem in achieving high speed.

Moreover, in the floating point normalization device 6 in the floating point arithmetic unit, after the detection encoder 6b obtains the bit position, the exponent and mantissa are normalized based on the obtained value, so the number of processing stages is large. This was a problem when trying to speed up the process.

The first invention was made to solve the above problems, and its purpose is to increase the processing speed of unnormalized exponents and unnormalized mantissas before they are input to the floating-point normalizer. It is an object of the present invention to provide a floating point arithmetic device that can speed up the arithmetic processing of the device as a whole.

The second invention was also made to solve the above problem, and its purpose is to increase the processing speed of normalizing the non-normalized exponent and the mantissa, thereby increasing the processing speed of the entire device. The purpose of the present invention is to provide a floating point normalizer that can perform the following steps.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of a floating point arithmetic device according to the first invention, in which a subtracter 11 operates on both an operand Fa2'''1 and an operand Fb2@b. This is an arithmetic unit that calculates the exponent difference between exponents ea and eb, and the exponent difference is output to the exponent selector 12 and the mantissa selector 14.The exponent selector 12 selects the operand Fa.
2'' and the arithmetic number Fb2'' are input, and the larger exponent is selected based on the exponent difference.

When calculating a difference from both exponents of an arbitrary operand and an operand, the mantissa candidate arithmetic unit 13 is provided with only mantissa adders/subtractors 13a of numbers corresponding to the possible difference from both exponents, and each adder/subtractor 13a calculates an arbitrary value. Perform addition and subtraction of mantissas for all possible combinations of the difference color from both exponents. Then, the mantissa candidate arithmetic unit 13 inputs the input operand Fa2°'' and the operand Fb.
Addition and subtraction of all possible combinations are performed for both success and failure Fa and Fb of 2°5.

The mantissa selector 14 is connected to each adder/subtracter 1 of the mantissa candidate arithmetic unit 13.
Input the calculated value of 3a and subtracter 11 from each calculated value.
The calculated value of the adder/subtractor 13a corresponding to the exponent difference calculated by is selected as the mantissa fa.

The floating point normalizer 15 then uses the exponent ea selected by the exponent selector 12 and the mantissa f selected by the mantissa selector 14.
Input a, convert it into a normalized exponent er and a mantissa F, and output it.

FIG. 2 is an explanatory diagram of the principle of the floating point normalization device of the second invention, in which the detection encoder 21 inputs a non-normalized mantissa fa that has not been normalized, and detects the most significant bit of the non-normalized mantissa fa. The bit length counting from 0 until a value other than 0 arrives or the value at a predetermined bit position is detected, and the detection result is output to the shifter 22 and the exponent selector 24. The shifter 22 uses the detection result detected by the detection encoder 21 as a shift amount to shift the non-normalized mantissa fa by digits to obtain a normalized mantissa Fr.

The exponent candidate calculator 23 includes a plurality of calculators 23a, and each of the calculators 23a calculates all the exponents expected when normalized. Then, the exponent candidate calculator 23 calculates all exponents expected when the input exponent ea is normalized.

The exponent selector 24 inputs the selected non-normalized exponent and each exponent obtained by the exponent candidate calculator 23, and selects the exponent corresponding to the detection result detected by the detection encoder 21 from among the exponents as the normalized exponent er. select.

[Operation] In the floating point arithmetic device of the first invention, the operand F input to each adder/subtractor 13a of the mantissa candidate arithmetic unit 13
Additions and subtractions of all possible combinations for both success and failure Fa and Fb of a 2"" and the operation number Fb 2°5 are obtained in advance at the same time, and the additions and subtractions of all possible combinations are calculated in advance using the mantissa selector 14 and the subtractor 11
Since the calculated value of the adder/subtractor 13a corresponding to the exponent difference calculated by is set as the mantissa fa, the unnormalized mantissa f in the floating point addition/subtraction before being input to the floating point normalizer 15
The number of arithmetic processing stages of a is reduced, and the mantissa arithmetic operation can be executed without waiting for the arithmetic result of the subtracter 11, and the arithmetic processing speed of the floating point arithmetic unit is correspondingly increased.

In the floating point normalization device of the second invention, all exponents expected when normalized to the exponent selected by each arithmetic unit 23a of the exponent candidate arithmetic unit 23 are calculated in advance, and each of the exponents is calculated in advance. Since the index corresponding to the detection result detected by the detection encoder 21 in the index selector 24 from among the index and the selected non-normalized index ea is set as the normalized index er,
Waiting for the detection result of the detection encoder 21, the normalization index er
This eliminates the need for calculations, and the calculation processing of the floating-point normalizer becomes faster.

[Embodiment] An embodiment in which the present invention is embodied in a computer equipped with a floating-point arithmetic unit will be described below with reference to the drawings.

In FIG. 3, n+1 registers rO-rn are registers in which numerical data is stored, and numerical data in floating point representation or fixed point representation for numerical calculations is stored through memory 31 or input/output interface 32. is input. The registers rO to rn are respectively connected to the data line Ll for the operand and the data line L2 for the operand, and can output the numerical data held therein as the operand or the operand.

The integer arithmetic unit 33 is connected to registers rO to rn via data lines Ll and L2, and calculates numerical data in fixed point representation of two registers selected from each register rO to rn as an operand and an operand. input. and,
The integer arithmetic device 33 executes an integer arithmetic operation based on the input operand and the arithmetic number, and stores the arithmetic result in the memory 3.
1 or the input/output interface 32.

Floating point adder/subtracter 34 is connected to data line Ll.

It is connected to registers rO to rn via L2, and inputs numerical data in floating point representation of two registers selected from each register rO to rn as operands and operands. The floating point addition/subtraction device 34 executes floating point operations (addition/subtraction) based on the input operands and operands, and outputs the operation results to the memory 31 or the register or input/output interface 32.

To explain the floating point adder/subtracter 34 in detail, the subtracter 11 and the exponent selector 12 are connected to the data line Ll.

It is connected to the registers rO to rn via L2, and is configured to input numerical data in floating point representation of the two selected registers, that is, the exponent of the operand and the operand. The subtracter 11 calculates the exponent difference between the exponents of the operand and the operand, and outputs the result to the exponent selector 12 and the mantissa selector 14. The exponent selector 12 selects the larger exponent based on this exponent difference, and the floating point normalizer 15 selects the larger exponent.
Output to.

The mantissa candidate arithmetic unit 13 is composed of a large number of mantissa adders/subtractors 13a, and each adder/subtractor 13a is connected to the data line L1. The selected 2
Numerical data in floating point representation in two registers, ie, the operand and the mantissa of the operand, are respectively input. The number of adders/subtractors 13a is provided in a number corresponding to the difference that can be considered from both exponents when calculating a difference from both exponents of an arbitrary operand and an operand. For example, when the exponent is composed of 7 bits, the mantissa candidate arithmetic unit 13 is composed of 15 adders/subtractors 13a. Then, the mantissa candidate calculator 13
Each adder/subtractor 13a performs mantissa addition/subtraction of all possible combinations of the difference color from arbitrary two exponents.

The mantissa selector 14 inputs the exponent difference calculated by the subtractor 11, selects the adder/subtractor 13a in the mantissa candidate calculator 13 that has performed the mantissa addition/subtraction corresponding to the exponent difference, and uses the calculated value as the mantissa to convert the floating point normal. output to converter 15.

The detection encoder 21 and barrel shifter 22 of the floating point normalizer 15 are connected to the unnormalized mantissa selector 1.
4. Input the selected mantissa (non-normalized mantissa). The detection encoder 21 detects which bit of the non-normalized mantissa has a value other than O, counting from the most significant bit, and outputs the detection result to the shifter 22 and the exponent selector 24. The shifter 22 uses the number of bits detected by the detection encoder 21 as a shift amount to shift the non-normalized mantissa and outputs it as a normalized mantissa.

The index candidate calculator 23 is a bow calculator 23 as a large number of calculators.
a, and the larger exponent (non-normalized exponent) selected by the exponent selector 12 based on the exponent difference is input as the operand.

The number of subtracters 23a is equal to the number of bit precisions of the mantissa. For example, when the mantissa is composed of 24 bits, the exponent candidate calculator 23 is composed of 24 subtracters 23a, and each subtracter 23a calculates the corresponding value from "1" to "24". Enter as a number.

Note that the exponent candidate arithmetic unit 23 of this embodiment outputs the unnormalized exponent as it is to the exponent selector 24 without using a subtracter in consideration of the case where the unnormalized exponent becomes the normalized exponent as it is.
You may also use a subtracter 23a that performs subtraction. and,
All the exponents expected when the exponents inputted by each subtractor 23a of the exponent candidate calculator 23 are normalized are determined.

The exponent selector 24 inputs the non-normalized exponent outputted from the exponent candidate calculator 23 and each exponent obtained by each subtractor 23a, and selects the number of bits detected by the detection encoder 21 from among the exponents. Select the index as the normalization index.

Then, the exponent selected by the exponent selector 24 and the mantissa selected by the mantissa selector 14 are output to the memory 31 or the input/output interface 32 as normalized exponents and mantissas.

Next, the floating point arithmetic unit 34 configured as described above
The effect of this will be explained.

Now, the numerical data F displayed as a floating point in register rO
a2@” as the operand and the floating-point displayed numerical data Fb2@b of the register r1 as the operand, and when the floating-point addition/subtraction unit 34 adds them, both exponents ea,
eb is output to the subtracter 11 and exponent selector 12.

The exponent difference ec (=ea −eb
), the exponent selector 12 selects the larger exponent and outputs it to each subtracter 23a of the exponent candidate calculator 23 and the exponent selector 24.

On the other hand, both mantissas Fa and Fb are input to each mantissa adder/subtractor 13a of the mantissa candidate calculator 13. Each adder/subtractor 13a has both mantissas Fa of the operand Fa 2°1 and the operand Fb 2°5,
Additions of all possible combinations to Fb are determined simultaneously. That is, a certain adder/subtractor 13a has an exponent difference ec of "
l'', a certain adder/subtractor 13a has an exponent difference ec of ``2''.
”, the possible index difference eS, i.e. =
n - n (n is an integer; if the exponent is made up of 7 bits, n = 7 and there are 15 possible exponent differences eC)
, the respective adders/subtractors 13a simultaneously execute the following corresponding mantissa operations.

Fb, Fa2 ”+Fb, -・・・・・・・・・-Fa
2'+Fb, Fa +Fb, Fa
+Fb 2...Fa 10Fb 2 F
The a mantissa selector 14 calculates the exponent difference ec calculated by the subtractor 11.
, and outputs the calculated value of the adder/subtractor 13a to the detection encoder 21 and barrel shifter 22 as a non-normalized mantissa fa.

The detection encoder 21 detects which bit of the non-normalized mantissa fa has a value other than 0, counting from the most significant bit, and outputs the detection result to the barrel shifter 22. The shifter 22 uses the number of bits detected by the detection decoder 21 as a shift amount to shift the non-normalized mantissa by digits to obtain a normalized mantissa Fr.

On the other hand, the exponent candidate calculation unit 23, which has input the non-normalized exponent ea selected by the exponent selector 12, uses each of its bow calculators 23a to calculate all the exponents expected when normalized as shown below. .

ea-1, ea-2, · Kushi... ea -nThe non-normalized exponent is expected to be the normalized exponent, that is, the exponent ea, which is output as is without being calculated by the subtractor. . Also, n is the number of bits of the mantissa.

The next-stage index selector 24 inputs the unnormalized index ea of the previous-stage index selector 12 and each index ea-1-ea-n obtained by the index candidate calculator 23, and inputs each index ea-ea
-n, the exponent corresponding to the number of bits detected by the detection encoder 21 is selected as the normalization exponent er.

In this way, in the floating point arithmetic device of this embodiment, both the mantissas Fa of the operand Fa2'' and the operand Fb2e1' are input to each adder/subtractor 13a.

Additions and subtractions of all possible combinations to Fb are obtained in advance at the same time, and the additions and subtractions are calculated by the mantissa selector 14 to the adder/subtractor 13a corresponding to the exponent difference eC calculated by the subtracter 11.
Since the calculated value of is set as the mantissa fa, the subtracter 1 is used as in the conventional method.
Numerical operations can be performed without waiting for the operation result of 1, and the processing speed of the floating-point arithmetic unit increases accordingly.

Moreover, in the normalization device 15, all the exponents expected when the exponent selected by the exponent candidate calculator 23 is normalized are obtained in advance, and each of the exponents and the selected unnormalized exponent eaO are calculated in advance. Since the exponent selector 24 uses the exponent corresponding to the number of bits detected by the detection encoder 21 as the normalization exponent er, there is no need to wait for the detection result of the detection encoder 2I to calculate the normalization exponent er.
The arithmetic processing of the floating point normalizer becomes faster by that much. As a result, the processing speed of the floating-point arithmetic device as a whole becomes even faster.

It should be noted that the present invention is not limited to the embodiment described above, and as shown in FIG. The normalizer 15 sequentially converts each unnormalized exponent and unnormalized mantissa through 35b.
Alternatively, the processing speed may be increased when continuous floating point operations are performed. still,
The registers r ml and r m2 are designed to temporarily store the results of each consecutive operation.

Furthermore, although the floating point normalization device is embodied in an addition/subtraction device, it may also be embodied in a multiplication device.

Figure 5 shows a floating point multiplication device, with the operand Fa2''
A multiplier 41 that multiplies the mantissa Fa of , by the mantissa Fb of the operation number Fb2sb, and an exponent candidate calculator 42 consisting of adders 42a and 42b that input both exponents ea and eb and add them under certain conditions, respectively. It is composed of an index selector 24 and a barrel shifter 22. And multiplier 4
1 multiplies both mantissas Fa and Fb and outputs the result to the barrel shifter 22 as a non-normalized mantissa. Also, this multiplier 4
1 has a function equivalent to the detection encoder 21 of the above embodiment, and transfers the value of the most significant bit in the calculation result, that is, the value of "0" or "1" which is a shift value for normalization, to the shifter 22 and It is output to the index selector 24. and,
If the shifter 22 is "0", the mantissa Fa is directly used as the normalized mantissa.

Output the result of multiplying by Fb, and if it is "1", the mantissa Fa
, Fb, and the result is shifted by one bit toward the least significant bit, normalized, and output.

On the other hand, the adder 42a of the index candidate arithmetic unit 42
, eb, and the adder 42b adds both exponents ea, eb
and 1 is added. That is, here, two expected normalization exponents are obtained in advance based on the calculation results of the multiplier 41.

Then, the exponent selector 24 determines that the value of the multiplier 41 is r()
”, the value of the adder 42a is output as the normalized exponent, and if it is “1”, the value of the adder 42b is output as the normalized exponent.

Therefore, even in this case, the processing speed for normalization in the floating-point multiplication device that performs Fa 2''·Fb 2@b=Fr 2'' becomes faster.

[Effects of the Invention] As detailed above, according to the floating point arithmetic device of the present invention, the processing speed of the unnormalized exponent and the unnormalized mantissa before being input to the floating point normalizer can be increased. This has the effect of increasing the speed of arithmetic processing in the entire device.

Further, in the floating point normalization device of the present invention, the processing speed for normalizing the non-normalized exponent and the mantissa can be increased, and the floating point processing device as a whole has the effect of increasing the processing speed.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of a floating point arithmetic device of the present invention, Fig. 2 is an explanatory diagram of the principle of a floating point normalization device of the present invention, and Fig. 3 is a diagram illustrating the configuration of a floating point arithmetic device embodying the present invention. FIG. 4 is a block diagram showing a separate floating-point arithmetic unit embodying the present invention; FIG. 5 is a block diagram showing the configuration of a floating-point multiplication device; FIG. 6 is a conventional floating-point addition/subtraction device. FIG. 7 is an electrical block circuit diagram of a conventional floating point normalizer. In the figure, 11 is a subtracter, 12 is an exponent selector, 13 is a mantissa candidate arithmetic unit, 14 is a mantissa selector, 15 is a floating point normalizer, 21 is a detection encoder, 22 is a shifter, 23 is an exponent candidate arithmetic unit, 24 is an index selector. Fig. 1 Detailed explanatory diagram of the invention in Fig. 2 Fig. 2 An explanatory diagram of the principle of the invention in Fig. 2 r r r

Claims (1)

[Claims] 1. A subtractor (11) for calculating the exponent difference between the exponents of the operand and the operand, and selecting the larger exponent based on the exponent difference calculated by the subtractor (11). When calculating a difference from both exponents of an arbitrary operand and an operand, a mantissa adder/subtractor (13a) is provided for each possible difference between the two exponents, and each adder/subtractor (13a) a mantissa candidate arithmetic unit (13) that performs all possible combinations of mantissa addition and subtraction for each difference on both the input mantissas of the operand and the operand; The adder/subtracter (13a) corresponds to the exponent difference calculated by the subtracter (11)
The mantissa selector (14) selects the mantissa obtained by adding and subtracting the mantissas in 13a), and the exponent selected by the exponent selector (12) and the mantissa selector (
14) A floating point arithmetic unit comprising a floating point normalizer (15) which calculates a normalized exponent and a mantissa based on the mantissa selected by the operator. 2. A detection encoder (21) that detects the bit length of a non-normalized mantissa consisting of a plurality of bits until a value other than 0, counted from the most significant bit, or a value at a predetermined bit position; and the detection encoder (21) A shifter (22) that uses the detected detection result as a shift amount to shift the unnormalized mantissa by digits to make it a normalized mantissa; , an index candidate calculator (23) composed of a large number of calculators (23a), and an index corresponding to the detection result detected by the detection encoder (21) from among the indices obtained by the index candidate calculator (23). and an exponent selector (24) for selecting the normalization exponent.