JPH04152559A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04152559A
JPH04152559A JP27988390A JP27988390A JPH04152559A JP H04152559 A JPH04152559 A JP H04152559A JP 27988390 A JP27988390 A JP 27988390A JP 27988390 A JP27988390 A JP 27988390A JP H04152559 A JPH04152559 A JP H04152559A
Authority
JP
Japan
Prior art keywords
input
output
mos
semiconductor device
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27988390A
Other languages
Japanese (ja)
Inventor
Satoru Kishimoto
悟 岸本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27988390A priority Critical patent/JPH04152559A/en
Publication of JPH04152559A publication Critical patent/JPH04152559A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Abstract

PURPOSE:To obtain a semiconductor device which is stable at a high frequency, which is excellent in a breakdown-resistant value and whose reliability is high by a method wherein transistor chips and input/output wires are arranged so as to be symmetric with respect to the input/output center line. CONSTITUTION:At a semiconductor device, transistor chips 1 in the even number and a MOS-C chip 4 for internal matching use are incorporated in a transistor package. At the semiconductor device, the transistor chips 1 and input/output wires 7, 8 are arranged so as to be symmetric with respect to the input/output center line 9. For example, a MOS-C chip 4 for internal matching use is die- bonded onto the input/output center line 9. Then, two transistor chip 1 are die-bonded so as to be symmetric with respect to the input/output line 9. Then, first input/output wires 7 and second input/output wires 8 are formed, by a prescribed wire bonding operation, on first bonding pads 2, second bonding pads 3, a first MOS-C electrode 5 and a second MOS-C electrode 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関し、特に高周波特性の安定
化、信頼性の向１を図るようにした半導体装置に関する
ものでおる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device designed to stabilize high frequency characteristics and improve reliability.

〔従来の技術〕[Conventional technology]

第２図は、従来の半導体装置のトランジスタ構成図であ
る。図において、（１）はトランジスタチップ、（２）
は第１のポンディングパッド、（３）は第２のポンディ
ングパッド、（４）は内部整合用ＭＯＳ−０、（５）は
第１　ノＭＯＳ−０［、［、（６）ハ第２　ノＭｏ５−
ｃ　電極、（７）は第１の入出力ワイヤ、（８）は第２
の入出力ワイヤ、（９）は入出力センターラインである
。FIG. 2 is a diagram showing a transistor configuration of a conventional semiconductor device. In the figure, (1) is a transistor chip, (2)
is the first bonding pad, (3) is the second bonding pad, (4) is the internal matching MOS-0, (5) is the first MOS-0 [, [, (6) C is the second NoMo5-
c electrode, (7) is the first input/output wire, (8) is the second
(9) is the input/output center line.

次に動作について説明する。第２図の半導体装置は、内
部整合用ＭＯＳ−０（６）を入出力センターライン（９
）上にグイボンドし、次にトランジスタチップ（１）も
入出力センターライン（９）上にダイボンドする。次に
第１の入出力ワイヤ（７）、第２の入出力ワイヤ（８）
を第１のポンディングパッド（２）、第２のポンディン
グパッド（３）、第１のＭＯＳ−０電椿（５）、第２の
ＭＯＳ−０″［極（６）にワイヤボンドして形成される
０ 〔発明が解決しようとする［１９　） 従来の半導体装置は以上のように構成されているので、
入出力ワイヤおよびトランジスタチップが入出力センタ
ーラインに対して対称でないため、高周波的に不安定、
破壊耐量が小さく、信頼性低下等の問題点があった。Next, the operation will be explained. The semiconductor device in Figure 2 connects the internal matching MOS-0 (6) to the input/output center line (9).
), and then the transistor chip (1) is also die-bonded onto the input/output center line (9). Next, the first input/output wire (7), the second input/output wire (8)
wire bond to the first bonding pad (2), the second bonding pad (3), the first MOS-0 electric camellia (5), and the second MOS-0'' [pole (6). [To be solved by the invention [19] Since the conventional semiconductor device is configured as described above,
The input/output wires and transistor chips are not symmetrical with respect to the input/output center line, resulting in high frequency instability.
There were problems such as low fracture resistance and decreased reliability.

この発明は上記のような問題点を解消するためになされ
たものでトランジスタチップ、入出力ワイヤを入出力セ
ンターラインに対し対称にするととによシ、バランスの
とれた安定な半導体装置を得ることを目的とする。This invention was made to solve the above problems, and it is possible to obtain a balanced and stable semiconductor device by making the transistor chip and input/output wires symmetrical with respect to the input/output center line. With the goal.

〔原題を解決するための手段〕[Means to solve the original problem]

この発明に係る半導体装置は、２個のトランジスタチッ
プにおいてパッケージの入出力センターラインに対し左
右対称となるように配置し、入出力ワイヤも左右対称と
なるようにワイヤボンドしたものである。In the semiconductor device according to the present invention, two transistor chips are arranged symmetrically with respect to the input/output center line of the package, and the input/output wires are also wire-bonded so as to be symmetrical.

〔作用〕[Effect]

この発明における半導体装置は、トランジスタチップ入
出力ワイヤを、入出力センターラインに対し、左右対称
にしたので、高周波的に安定となり、破壊耐量が向上す
る。In the semiconductor device according to the present invention, the transistor chip input/output wires are made symmetrical with respect to the input/output center line, so that the semiconductor device is stable at high frequencies and has improved breakdown resistance.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図は本発明の一実施例による半導体装置を示す図であり
、図において、（１）はトランジスタチップ、（２）は
第１のポンプイングツ（ラド、（３）は第２のポンディ
ングパッド、（４）は内部整合用ＭＯＳ−０、（５）ハ
第１のＭＯＳ−ＣｗＬ極、（６）は第２のＭＯＳ−０を
極、（７）は第１の入出力ワイヤ、（８）は第２の入出
力ワイヤ、（９）は入出力センターツインである。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a semiconductor device according to an embodiment of the present invention. In the figure, (1) is a transistor chip, (2) is a first pumping pad (RAD), (3) is a second pumping pad, ( 4) is the internal matching MOS-0, (5) is the first MOS-CwL pole, (6) is the second MOS-0 as the pole, (7) is the first input/output wire, and (8) is the The second input/output wire, (9) is the input/output center twin.

次に動作について説明する。内部整合用ＭＯＳ−Ｃチッ
プ（４）を入出力センターライン（９）上にグイボンド
する。次に入出力センターツイン（９）に対し左右対称
に々るように２個のトランジスタチップ（１）をダイボ
ンドする０次に第１のポンディングパッド（２）と第２
のポンディングパッド（３）、第１のＭＯＳ−〇電極（
５）と第２のＭＯＳ−０［極（６）に、所定のワイヤボ
ンドによシ第１の入出力ワイヤ（７）、第２の入出力ワ
イヤ（８）を形成する。このような構成にした第１図の
ものは入出力センターラインに対し左右対称である。Next, the operation will be explained. An internal matching MOS-C chip (4) is bonded onto the input/output center line (9). Next, die bond two transistor chips (1) symmetrically to the input/output center twin (9).
bonding pad (3), first MOS-〇 electrode (
5) and the second MOS-0 [pole (6), a first input/output wire (7) and a second input/output wire (8) are formed by predetermined wire bonds. The configuration shown in FIG. 1 is symmetrical with respect to the input/output center line.

なお、上記実施例では、２個のトランジスタチップにつ
いて説明したが４個以五の偶数個のトランジスタチップ
であっても同様の効果を奏する。In the above embodiment, two transistor chips have been described, but the same effect can be obtained even if an even number of transistor chips of four or more are used.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、トランジスタチップ入
出力ワイヤを入出力センターラインに対し左右対称にし
たので、高周波的に安定し、破壊耐量のすぐれた、高倍
軸性のものが得られる効果がある。As described above, according to the present invention, since the transistor chip input/output wires are made symmetrical with respect to the input/output center line, it is possible to obtain a high-multiply axial property that is stable at high frequencies and has excellent breakdown resistance. be.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例による半導体装置の構成図
、第２図は従来の半導体装置の構成図である。 図において、（１）はトランジスタチップ、（２）は第
１のポンディングパッド、（３）は第２のポンディング
パッド、（４）は内部整合用ＭＯ３−０，（５）は第１
のＭＯＳ−０電極、（６ンは第２のＭＯＳ−Ｃ！電極、
（７）は第１の入出力ワイヤ５（８）ｔｉ第２の入出力
ワイヤ、（９）は入出力センターライン なお、図中、同一符号は同一　又は相当部分を示す。FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor device. In the figure, (1) is the transistor chip, (2) is the first bonding pad, (3) is the second bonding pad, (4) is MO3-0 for internal matching, and (5) is the first bonding pad.
MOS-0 electrode, (6 is the second MOS-C! electrode,
(7) is the first input/output wire 5 (8) ti second input/output wire, and (9) is the input/output center line. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　トランジスタパッケージに偶数個のトランジスタチッ
プおよび内部整合用ＭＯＳ−Ｃを組み込んだ半導体装置
において、トランジスタチップおよび入出力ワイヤを入
出力センターツインに対し左右対称に配置したことを特
徴とする半導体装置。1. A semiconductor device in which an even number of transistor chips and an internal matching MOS-C are incorporated in a transistor package, characterized in that the transistor chips and input/output wires are arranged symmetrically with respect to an input/output center twin.
JP27988390A 1990-10-16 1990-10-16 Semiconductor device Pending JPH04152559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27988390A JPH04152559A (en) 1990-10-16 1990-10-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27988390A JPH04152559A (en) 1990-10-16 1990-10-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04152559A true JPH04152559A (en) 1992-05-26

Family

ID=17617266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27988390A Pending JPH04152559A (en) 1990-10-16 1990-10-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04152559A (en)

Similar Documents

Publication Publication Date Title
JPH05275943A (en) Low inductance for plural parallel-connected devices for operating at high frequency
JPH04152559A (en) Semiconductor device
JPH05335474A (en) Resin sealed semiconductor device
JPS6028256A (en) Semiconductor device
JP2908350B2 (en) Semiconductor device
JPH07101698B2 (en) Method for manufacturing resin-sealed semiconductor device
JPS63202948A (en) Lead frame
JPH02105450A (en) Semiconductor device
JP2901572B2 (en) Semiconductor device wire bonding method
JPH0543478Y2 (en)
JP2692904B2 (en) Semiconductor device with built-in diode chip and manufacturing method thereof
JPH07335818A (en) Semiconductor device
JPH02185047A (en) Semiconductor device
JPH0621319A (en) Lead frame for semiconductor device
JPH02112242A (en) Semiconductor device
JPS59198744A (en) Resin sealed type semiconductor device
JPH0228958A (en) High-frequency high-output transistor
JPH0555452A (en) Semiconductor integrated circuit device
JPH04151842A (en) Semiconductor device
JPH0385737A (en) Semiconductor device
JPH09246463A (en) Semiconductor integrated circuit device
JPH06334100A (en) Semiconductor device and lead frame thereof
JPH11297925A (en) Ic chip laminated package
JPH04368140A (en) Semiconductor device
JPH0645503A (en) Lead frame for resin seal type semiconductor device