JPH041500B2 - - Google Patents

Info

Publication number
JPH041500B2
JPH041500B2 JP58141670A JP14167083A JPH041500B2 JP H041500 B2 JPH041500 B2 JP H041500B2 JP 58141670 A JP58141670 A JP 58141670A JP 14167083 A JP14167083 A JP 14167083A JP H041500 B2 JPH041500 B2 JP H041500B2
Authority
JP
Japan
Prior art keywords
sealing
cap
package
frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58141670A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6032341A (ja
Inventor
Manabu Bonshihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58141670A priority Critical patent/JPS6032341A/ja
Publication of JPS6032341A publication Critical patent/JPS6032341A/ja
Publication of JPH041500B2 publication Critical patent/JPH041500B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/163Connection portion, e.g. seal

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP58141670A 1983-08-02 1983-08-02 半導体装置 Granted JPS6032341A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58141670A JPS6032341A (ja) 1983-08-02 1983-08-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58141670A JPS6032341A (ja) 1983-08-02 1983-08-02 半導体装置

Publications (2)

Publication Number Publication Date
JPS6032341A JPS6032341A (ja) 1985-02-19
JPH041500B2 true JPH041500B2 (zh) 1992-01-13

Family

ID=15297456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58141670A Granted JPS6032341A (ja) 1983-08-02 1983-08-02 半導体装置

Country Status (1)

Country Link
JP (1) JPS6032341A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5206713B2 (ja) * 2010-03-09 2013-06-12 富士電機株式会社 半導体パッケージの組立方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240069A (en) * 1975-09-26 1977-03-28 Hitachi Ltd Insulator vessel sealed type semiconductor device and process for prod uction of same
JPS5547772B2 (zh) * 1976-03-02 1980-12-02

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5547772U (zh) * 1978-09-26 1980-03-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240069A (en) * 1975-09-26 1977-03-28 Hitachi Ltd Insulator vessel sealed type semiconductor device and process for prod uction of same
JPS5547772B2 (zh) * 1976-03-02 1980-12-02

Also Published As

Publication number Publication date
JPS6032341A (ja) 1985-02-19

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