JPH04145663A - Mos type solid state image sensor and driving method therefor - Google Patents

Abstract

PURPOSE:To obtain an excellent image in low illuminance and to prevent blooming by providing an insular P-type region on an N-type semiconductor substrate, an N<+> type region and a P<+> type region formed in the insular region, first-third switches, etc. CONSTITUTION:When a minus several volts (7 volts) is set to a P<+> type region 2 and the surface potential of an N<+> type region 4 under a horizontal electrode 7 of a first stage is set to a potential higher by 1 volt than that of the region 2, an insular P-type region 3 of an uppermost stage is all depleted or completely depleted. Then, when the surface potential under a pM0S transistor Tr 8 is set to about 0.5V, a Tr 8, nMOSTr9 are all turned OFF, and the region 2 is floated. The uppermost stage starts to stored signal holes, and when signal storage of second stage is finished, a signal is then read through first-third switches 15, 16, 17, a capacity 17, etc. Such an operation is repeated to continuously obtain a signal responsive to an incident light from an all screen with high sensitivity, and blooming can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS solid-state imaging device and a method for driving the same.

[Conventional technology]

Conventional solid-state imaging devices are broadly classified into MOS solid-state imaging devices and CCD-type solid-state imaging devices. FIG. 4 is a circuit diagram of a MOS type solid-state imaging device. This device consists of a vertical shift register 101, a horizontal shift register 102, a photodiode PD, and two M○S transistor switches Tv (vertical) and Tv provided for vertical and horizontal scanning of each photodiode.
H (horizontal), and each horizontal signal line 103 is connected to a video bias V immediately before reading each horizontal element.
Transistor TR and transistor Tλ reset to R
A reset signal line Rp for turning on and off the video amplifier 104, and a switch SV for controlling input and non-input of each horizontal video signal to the video amplifier 104.

Next, the operation of this solid-state imaging device will be described.

First, the vertical shift register 1 is placed on the top vertical scanning line 105.
A pulse voltage is applied from 01 to turn on all the transistors TV in the uppermost stage. Next, reset transistor TR
By turning on state by the reset signal Rp, the potential of the horizontal signal line is set to the video bias VR. Next, after turning off the transistor TR, the leftmost MOS transistor TH is activated by the output from the horizontal shift register 1.about.2 to read out the video signal. Here, the transistor Tλ is turned on and off again to set the potential of the horizontal signal line to the video bias h. Next, 2 from the left in the first row
The transistor TH of the pixel is activated to read out the video signal. This operation is carried out until the right end, and the -th stage video output is obtained from the video amplifier 104. Next, the output of the vertical shift register is transferred to the second stage, and the same operation as in the first stage is performed to obtain the output of the second stage. This operation is performed until the lowest stage, and after the vertical blanking period, the output signal is read out in exactly the same manner from the -th stage. Through the above operations, electrons generated by light incident on the photodiode PD are sent to the video amplifier 104 and become a video signal. However, the electrons generated by the light are sent from the photodiode to the video amplifier 104 without being amplified at all.

In a CCD type solid-state imaging device, the photoelectrically converted signal charge is sent to a vertical CCD register, transferred to a horizontal CCD register, and then sent to a video amplifier. It is similar to an imaging device.

[Problem to be solved by the invention]

As explained above, in conventional MOS solid-state imaging devices, the pixels themselves do not have an amplification function, so in low-light imaging where the amount of incident light is small, the image quality is affected by the noise generated from the readout circuit made of MOS transistors. It has the disadvantage of significant deterioration.

An object of the present invention is to provide a MOS solid-state imaging device that can obtain good images at low illuminance.

[Means to solve the problem]

The MOS type solid-state imaging device of the present invention includes an island-like P (or N) type region selectively formed on an N (or P) type semiconductor substrate, and an N'' formed in the island-like P (or N) type region. (or P+) region, a P” (or N”) region formed at a predetermined distance from the island-like P (or N) type region, and the P+
(or N'') region, the N'' (or P+) region, and the island-like P (or N) type region.
) A composite MOS transistor having an insulating film formed on the surface of a semiconductor substrate and a gate electrode provided on the insulating film is placed at the intersection of L horizontal electrodes and M vertical readout lines with the gate electrode is connected to the horizontal electrode and the N
” (or P”) region connected to the vertical readout line, and the sensor array arranged respectively, and M inserted between one end of each of the M vertical readout lines of the sensor array and the reference potential end. between M first switches, M second switches each having one end connected to the other end of each of the M vertical readout lines, and the other end of each of the second switches and the signal line. a third switch inserted in each, a charge storage means inserted between the other end of the second switch and a reference potential end, and a pulse that sequentially opens and closes the third switch; a horizontal shift register; a vertical register that sequentially applies predetermined pulses to the vertical readout line; a means for applying a predetermined positive (or negative) DC potential to the N (or P) type semiconductor substrate; The MOS transistor has means for applying a predetermined negative (or positive) DC potential to the P" (or N") region of the MOS transistor.

Further, the method for driving the MOS type solid-state imaging device of the present invention includes: an island-like P (or N) type region selectively formed on an N (or P) type semiconductor substrate; a formed N'' (or P+) region, a P+ (or N'') region formed at a predetermined distance from the island-like P (or N) type region, and the P'' (or N'') region and the N'' (or P'') region and the island-like P (or N) type region, an insulating film formed on the surface of the N (or P) type semiconductor substrate, and a gate electrode provided on the insulating film. A composite MOS transistor is placed at the intersection of L horizontal electrodes and M vertical readout lines, with the front and gate electrodes connected to the horizontal electrodes, and the N'' (or P'') region connected to the vertical readout lines. and a sensor array arranged respectively, M first switches inserted between one end of each of the M vertical readout lines of the sensor array and a reference potential end, and the M vertical readout lines. M second switches each having one end connected to the other end of each of the second switches; a third switch inserted between the other end of each of the second switches and the signal line; charge storage means each inserted between the other end of the switch and a reference potential end, a horizontal shift register that generates pulses to sequentially open and close the third switch, and a predetermined pulse that is sequentially applied to the vertical readout line. means for applying a predetermined positive (or negative) DC potential to the N (or P) type semiconductor substrate; (or a positive) DC potential of each composite MoS transistor through the i-th (1≦i≦L) horizontal electrode of the MOS solid-state image sensor having
(or n) The surface potential of the channel of the MOS transistor is set to be about 1 volt higher (or lower) than the potential of the P" (or N") region to deplete the island-like P (or N) type region. and setting the surface potential to a predetermined potential via the i-th horizontal electrode to
i
=1 to i=L, the M second switches are opened, the M first switches are closed, and the potentials of the M vertical readout lines are initialized. After opening M of the first switches and closing M of the second switches, a positive (or negative) voltage is applied to the i-th horizontal electrode.
n( of the composite MOS transistor) by applying a potential pulse
or p) conduct the MOS transistor to take out a signal current corresponding to the incident light to the vertical readout line and store it in the charge storage means, open the third switch, and sequentially use the pulse from the horizontal shift register. Pre-word self 2nd
The operation of closing the switch and taking out the charge in the charge storage means to the signal line is performed sequentially from i=1 to i=L to obtain one field of video information.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the MOS solid-state imaging device of the present invention (for convenience, a sensor array with 2 rows and 2 columns is shown), and FIG. 2(a) is a circuit diagram of a sensor array in the first embodiment. A plan view showing the structure, FIGS. 2(b) and 2(c) are a sectional view taken along the line AA and BB in FIG. 2(a), respectively.

First, the pixels of the sensor array will be explained.

A hexagonal island-shaped P-type region 3 is formed on the surface of the N-type semiconductor substrate 1.
is provided. A P1 region 2 surrounds the island-like P-type region 3 at a predetermined interval.

Furthermore, a shallow N+ region 4 is provided in the center of the island-like P-type region 3. On the surface of such an N-type semiconductor substrate 1, a 5i02 film (8°9) with a thickness of several tens of nanometers is provided over the entire surface, and a horizontal electrode 7 such as a polysilicon film (with a thickness of several hundred nanometers) is provided thereon. It is being S on the surface of the horizontal electrode
An i02 membrane 10 is provided. Further, a vertical readout line 5b is provided in contact with the N+ region 4 at a contact region 5a. In order to short-circuit the contact region 5a with the horizontal electrode, the side surface of the contact hole penetrating the horizontal electrode is covered with a silicon oxide film.

Pixels having such a structure are arranged in the horizontal direction and share the horizontal electrode 7. A plurality of such horizontal rows are arranged in parallel to form a sensor array with a hexagonal close-packed structure. The P+ area of each pixel is connected vertically and horizontally to form a net shape. Further, the vertical readout lines 5b of each pixel are connected in a zigzag manner in the vertical direction6. Each pixel is a PMOS transistor (hereinafter referred to as PMOS transistor) having the island-like P wall region 3 as the source, the P+ region 2 as the drain, and the SfOzM8 as the gate insulating film. The reference number is (8)), the N1 region is the source, the 5i02 film 9 on the island-like P-type region is the gate insulating film, and the N-type semiconductor substrate 1 is the train.
A transistor (hereinafter referred to as reference number (9)) is included. The horizontal electrode 7 is a pMoS transistor (8), an nMO
This is the gate electrode of the S transistor (9).

A first switch 15 is inserted between one end of each of the two vertical readout lines 5 of the sensor array described above and the ground potential terminal, and a second switch 15 is inserted between the other end of each of the two vertical readout lines 5.
One end of the switch 16 is connected, the other end of the second switch is connected to the capacitor 17 and one end of the third switch 18, and the other end of the third switch is connected to the signal line 20. The gate electrode of the MOS transistor, which is the third switch 18, is connected to each stage of the horizontal shift register 14. The vertical signal readout line 7 is provided with the following information by the vertical register 13.
Pulses are applied sequentially. Further, a power supply 11 is connected to the N-type semiconductor substrate 1, and a power supply 12 is connected to the P" region 2 of each pixel.
is connected.

Next, the operation of this pixel will be explained.

A substrate bias voltage of plus several volts is applied to the N-type semiconductor substrate 1 by the power supply 11, and a substrate bias voltage of several volts (7
At the same time, a voltage slightly higher than the voltage applied to the P+ region 2 is applied to the horizontal electrode 7, and the surface potential of the N-type semiconductor substrate 1 is changed to the P+ region 2.
The voltage is about IV higher than that of the voltage.

At this time, a pMOS transistor (8) exists between the P+ region 2 and the island-like P wall region 3. Therefore, the holes in the island-like P wall region 3 pass under the thin SiC2 under the horizontal electrode 7 and pass through the P+
It is drawn into region 2 and has a negative potential. Its size is equal to the surface potential of the pMOS transistor (8) and the channel region.

Furthermore, when the voltages of the P+ region 2 and the horizontal electrode 7 are both negative and large (the P+ region 2 is more negative), all the holes in the island-like P wall region 3 are drawn away to the P+ region 2, and the island-like P Wall region 3 is completely depleted. Next, the potential below 8 is 10, 5
Apply a voltage to the horizontal electrode 7 such that: (2). At this time, the island-like P wall region becomes a potential well. When light hits this cell, holes generated in the island-like P-wall region 3 and its surroundings flow into the island-like P-wall region and the floating capacitance connected to the island-like P-wall region, raising the potential thereof. Now, an nMOS) radiator (9) with the N+ region 4 as the source (usually 0 volts), the region of the island-like P wall region 3 with the gate insulating film 9 on its surface as the gate, and the N-type semiconductor substrate 1 as the drain.
think of.

At this time, the potential of the island-like P wall region approaches zero as the incident light increases, so the back gate voltage of the nMOS transistor (9) decreases, the threshold voltage also decreases, and the drain current increases2. Therefore, the amount of light incident on the pixel can be determined from the magnitude of the train current. This current appears on the vertical readout line 5.

Next, the driving method of this first embodiment (the first embodiment of the driving method of the MO8 type solid-state imaging device of the present invention) will be explained.

If P" region 2 is set to minus several volts (7 volts) and the surface potential of N region under the first stage horizontal electrode is set to a potential 1 volt higher than P+ region 2, the island-like P wall region of the topmost stage is all Depletion or complete depletion.Next, when the horizontal electrode 7 of the first stage is set so that the surface potential under the pMOSMOS transistor is about 0.5V, both the pMOS transistor (8) and the nMOS transistor (9) are turned off, and the island is depleted. The P-type region floats. In this state, the top stage starts accumulating signal holes. In this state, the same operation is performed on the second stage to start signal accumulation. Once the signal accumulation in the second stage is completed, the next Read out the signal.

In the signal accumulation state described above, the nMOS transistor of each pixel is off. In this state, the first switch 16 is first opened, and the second switch 15 is closed to set the potential of the vertical read line 5 to the ground potential and initialize the potential of the vertical read line. Next, open the first switch 15.

Next, turn off all the third switches and then turn on the second switch.

Next, the uppermost horizontal electrode 7 is moved by the vertical shift register 13.
Give a positive potential to.

The pMOS transistor (8) continues to turn off, and the nMOS
Transistor (9) turns on. Current flows from the N-type semiconductor substrate 1 to the capacitor 17 through the N+ region 4 and the vertical readout line 5. This current is related to the threshold voltage of these transistors; when no light hits them, the back gate bias of the island-shaped P-type region is at its maximum, so the threshold voltage becomes large and only a small current flows. However, as the amount of light that hits the device increases, the threshold voltage decreases and the amount of current that flows increases. Appropriate time for reading out such a video signal is about 1 μs. This is because when very strong light enters the island-like P-type region during readout, the PMOS transistor is turned off, so excess holes cannot escape to the P+ region, and the island-like P-type region 3 becomes positive with respect to its surroundings. be.

At this time, the holes are transferred from the island-like P-type region to the N-type semiconductor substrate 1.
As holes flow into the cells, holes diffuse into surrounding cells, resulting in blooming. Therefore, the readout time of the video signal must be as short as possible.

Next, after opening all the second switches 16, the third switch 1 is sequentially opened by the output from the horizontal shift register 14.
8 is turned on, and the signal charges accumulated in the capacitor 17 are sequentially output.

In this case, when the second switch 16 is turned off, the sensor array and the upper and lower peripheral circuits are electrically isolated. After turning off the second switch 16, the output of the first stage of the vertical shift register is applied to the first stage of the sensor array. In this case, the peak value of the pulse from the shift register starts at minus several volts and continues at -0.5 volts after several microseconds, for example, so that the island-shaped P-type region not only accumulates signal holes but also prevents blooming.

After reading the signal height of the first stage, set the surface potential of the first stage N-type semiconductor substrate to a voltage slightly higher than minus several volts (approximately 1 volt). The zero-order first stage horizontal electrode 7, which is completely depleted or completely depleted, is pM.

The surface potential of the N-type semiconductor substrate of the S transistor (8) is -
The voltage should be about 0.5 volts. At this time pMOS
Both the transistor (8) and the nMOS transistor (9) are turned off, and the island-shaped P-type region floats. In this state, the top stage starts accumulating signal holes. Signal reading from the second stage and subsequent stages and signal accumulation are performed as described above to form one field screen. By repeating such operations, signals corresponding to the incident light can be continuously read out from the entire screen.

Since the sensor array has a hexagonal close-packed arrangement, it is possible to achieve high pixel density and realize a high-resolution solid-state imaging device.

The potential of the island-like P-type region changes depending on the amount of light.

The amount of change in charge accumulated in the island-shaped P-type region during one field (or frame) period due to the amount of light is expressed as ΔQII1. nMO
If the amount of change in charge read out during 1 μs through the S transistor due to the amount of light is ΔQ out, then the charge gain is given by ΔQout/QIa. This charge gain is n
This is due to the back gate effect of the MO8 transistor, and according to the inventor's studies, it is possible to achieve a very large value of 103 to 105.

In addition, since there is a blooming prevention mechanism except during the signal continuous period, blooming is reduced.

FIG. 3 is a plan view of a sensor array showing a second embodiment.

This embodiment has a horizontal direction electric current 8i19 in addition to that of the first embodiment.
is added.

Horizontal electrode7. The vertical readout line 5b is covered with a polysilicon film or a horizontal electrode 19 of the A(film) via a SiO2 film, except for the upper part of the island-like P wall region 3 of each horizontal row. Either one of the direction electrodes 19 is provided on the surface of the N-type semiconductor substrate sandwiched between the island-like P wall region 3 and the P+ region 2 via a 5in2 film (same thickness as 8 and 9) in each pixel. This means that

By applying a voltage slightly higher than the voltage applied to the P+ region 2 to this horizontal electrode, the holes in the island-shaped P-type head region are
+ Absorb into area. In the first embodiment, this effect was achieved only by the horizontal electrode, but in the second embodiment, since the horizontal electrode is provided, holes can be quickly absorbed into the P1 region. For example, the same pulse may be applied to the horizontal electrode and the horizontal electrode.

In addition, in the signal accumulation mode, N around the island-like P-type region
Since the surface potential of the type semiconductor substrate is about -0.5 volts, the blooming suppressing effect is more reliable than in the first embodiment.

Also, during the signal readout period, if the surface potential of the N region under the horizontal electrode is set to -0.5 volts, excess holes accumulated in the island-like P wall region will pass through the surface of the N region mentioned above. P'' area. Therefore, even if the read period is lengthened, blooming can be prevented.

The other aspects are the same as the driving method of the first embodiment.

In the above embodiments, it is clear that the conductivity type and voltage polarity may be reversed without going into detailed explanation again.

〔Effect of the invention〕

As explained above, according to the present invention, p (or n) MO
N” (or P”) in one active region of the S transistor
This has the effect of realizing a MOS type solid-state imaging device with high sensitivity and a blooming prevention effect using a composite transistor provided in the ) region as a photoelectric conversion element.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the first embodiment of the MOS type solid-state imaging device of the present invention, FIG. 2 (a> is a plan view showing the structure of the sensor array in FIG. 1, FIG. ) are a sectional view taken along line AA and BB in FIG. , Figure 4 shows the conventional MO
FIG. 2 is a circuit diagram of an S-type solid-state imaging device. 1... N-type semiconductor substrate, 2... P+ region, 3...
Island-like P wall region, 4... N+ region 5a... contact region, 5b... vertical readout line, 7... horizontal electrode, 1
One...horizontal electrode.

Claims (1)

[Claims] 1. An island-like P (or N) type region selectively formed on an N (or P) type semiconductor substrate, an N^+ formed in the island-like P (or N) type region (or P^+) region, a P^+ (or N^+) region formed at a predetermined interval from the island-like P (or N) type region, and a region between the P^+ (or N^+) region and the N
an insulating film formed on the surface of the N (or P) type semiconductor substrate including a ^+ (or P^+) region and the island-like P (or N) type region, and a gate provided on the insulating film A composite MOS transistor having an electrode is connected to the intersection of L horizontal electrodes and M vertical readout lines, the gate electrode is connected to the horizontal electrode, and the N^+ (or P^+) region is connected to the vertical readout line. M first switches inserted between one end of each of the M vertical readout lines of the sensor array and a reference potential end; M second switches each having one end connected to the other end of each of the vertical readout lines; and a third switch inserted between the other end of each of the second switches and the signal line.
a switch, a charge storage means inserted between the other end of the second switch and the reference potential end, and a third switch.
a horizontal shift register that generates pulses to sequentially open and close the switches; a vertical register that sequentially applies predetermined pulses to the vertical readout line; and a predetermined positive (or negative) register to the N (or P) type semiconductor substrate. means for applying a direct current potential of;
A MOS type solid-state imaging device, comprising means for applying a predetermined negative (or positive) direct current potential to the P^+ (or N^+) region of the composite MOS transistor. 2. Island-like P (or N) type region selectively formed on the N (or P) type semiconductor substrate, N^+ (or P^+) formed in the island-like P (or N) type region a P^+ (or N^+) region formed at a predetermined distance from the island-like P (or N) type region, and a P^+ (or N^+) region and the N
an insulating film formed on the surface of the N (or P) type semiconductor substrate including a ^+ (or P^+) region and the island-like P (or N) type region, and a gate provided on the insulating film A composite MOS transistor having an electrode is connected to the intersection of L horizontal electrodes and M vertical readout lines, the gate electrode is connected to the horizontal electrode, and the N^+ (or P^+) region is connected to the vertical readout line. M first switches inserted between one end of each of the M vertical readout lines of the sensor array and a reference potential end; M second switches each having one end connected to the other end of each of the vertical readout lines; and a third switch inserted between the other end of each of the second switches and the signal line.
a switch, a charge storage means inserted between the other end of the second switch and the reference potential end, and a third switch.
a horizontal shift register that generates pulses to sequentially open and close the switches; a vertical register that sequentially applies predetermined pulses to the vertical readout line; and a predetermined positive (or negative) register to the N (or P) type semiconductor substrate. means for applying a direct current potential of;
and means for applying a predetermined negative (or positive) DC potential to the P^+ (or N^+) region of the composite MOS transistor. Through the horizontal electrode, the surface potential of the channel of the p (or n) MOS transistor of each of the composite MOS transistors is set to be about 1 volt higher (or lower) than the potential of the P^+ (or N^+) region. Set the island-like P (
Alternatively, the N) type region is depleted and the surface potential is changed to the i
The holes (or electrons) generated by the light incident on the island-like P (or N) type region and its surroundings are set at a predetermined potential through the second horizontal electrode. After performing the operation of accumulating the stray capacitance in the area and surrounding stray capacitance for a certain period of time sequentially from i=1 to i=L, the M second switches are opened and the M first switches are closed. After initializing the potential of the vertical reading line of the book, M
After opening M of the first switches and closing M of the second switches, a positive (or negative) potential pulse is applied to the i-th horizontal electrode to
(or p) conduct the MOS transistor, take out a signal current corresponding to the incident light to the vertical readout line and store it in the charge storage means, open the third switch, and then to the second
A MOS type solid-state imaging device characterized in that the operation of closing a switch and extracting the charge of the charge storage means to the signal line is performed sequentially from i=1 to i=L to obtain one field of video information. driving method. 3. A composite MOS transistor whose planar shape includes a hexagonal shape and a P^+ (or N^+) region surrounding an island-like P (or N) type region at a predetermined interval is arranged in a hexagonal dense manner. MOS type solid-state imaging device according to item 1. 4. An island-like P (or N) type region selectively formed on an N (or P) type semiconductor substrate so that the planar shape is hexagonal, an N region formed in the island-like P (or N) type region ^+ (or P
^+) region, a P^+ (or N^+) region formed by surrounding the periphery of the island-like P (or N) type region at a predetermined interval, and the P^+ (or N^+) region. Said N^+ (or P
A composite MOS having an insulating film formed on the surface of the N (or P) type semiconductor substrate including the ^+) region and the island-like P (or N) type region, and a gate electrode provided on the insulating film. Multiple transistors are arranged in a hexagonal close-packed structure,
L horizontal electrodes are connected to the gate electrodes of the composite MOS transistors for each horizontal column, and the P^ electrodes are connected to each other for each vertical column.
The N^+ (or P) region of the composite MSO transistor is arranged in a zigzag manner on the
M vertical readout lines connected to the ^+) region, and horizontal lines connected to each horizontal column provided through an insulating film except on the island-like P (or N) type region of the composite MOS transistor. a sensor array including an electrode; M first switches inserted between one end of each of the M vertical readout lines of the sensor array and a reference potential end; M second switches each having one end connected to the other end; a third switch inserted between the other end of each of the second switches and the signal line; charge storage means inserted between the end and the reference potential end, a horizontal shift register that generates pulses that sequentially open and close the third switch, and a predetermined pulse that sequentially applies predetermined pulses to the vertical readout line. a vertical resistor, means for applying a predetermined positive (or negative) DC potential to the N (or P) type semiconductor substrate, and means for applying a predetermined negative (or positive) DC potential to the P^+ (or N) region of the composite MOS transistor; ).
OS type solid-state imaging device. 5. An island-like P (or N) type region selectively formed on the N (or P) type semiconductor substrate so that the planar shape is hexagonal, an N formed in the island-like P (or N) type region ^+ (or P
^+) region, a P^+ (or N^+) region formed by surrounding the periphery of the island-like P (or N) type region at a predetermined interval, and the P^+ (or N^+) region. Said N^+ (or P
A composite MOS having an insulating film formed on the surface of the N (or P) type semiconductor substrate including the ^+) region and the island-like P (or N) type region, and a gate electrode provided on the insulating film. A plurality of transistors are arranged in a hexagonal close-packed structure, and each horizontal column has L horizontal electrodes connected to the gate electrodes of the composite MOS transistors, and each vertical column has the P^+
The N^+ (or P^+) region of the composite MSO transistor is arranged in a zigzag manner through an insulating film on the N^+ (or P^+) region.
M vertical readout lines connected to the +) region, and horizontal electrodes provided through an insulating film and connected for each horizontal column except on the island-like P (or N) type region of the composite MOS transistor. M first switches inserted between one end of each of the M vertical readout lines of the sensor array and a reference potential end, and each other of the M vertical readout lines of the sensor array. M second terminals connected one end to the other end
a third switch inserted between the other end of each second switch and the signal line, and a third switch inserted between the other end of each of the second switches and the signal line;
charge accumulating means inserted between the other end of the switch and the reference potential end, a horizontal shift register that generates pulses that sequentially open and close the third switch, and a vertical register that applies a pulse, and a predetermined positive (or negative) register to the N (or P) type semiconductor substrate.
means for applying a DC potential of , and a predetermined negative (or positive)
The surface potential of the i-th (1≦i≦L) horizontal electrode and the N (or P) type semiconductor substrate under the horizontal electrode of the MOS solid-state imaging device having means for applying a DC potential of The potential of the island-shaped P(
Alternatively, the N) type region is depleted and the surface potential is changed to the i
Holes (or electrons) generated by light incident on the island-like P (or N) type region and its surroundings are set at a predetermined potential through the second horizontal electrode and the horizontal electrode. Alternatively, after performing the operation of accumulating the stray capacitance in the N) type region and the surrounding stray capacitance for a certain period of time sequentially from i=1 to i=L, the M second switches are opened and the M first switches are opened. After closing the switches and initializing the potentials of the M vertical readout lines, the M first switches are opened to set the M vertical readout lines.
After closing the second switches, a positive (or negative) potential pulse is applied to the i-th horizontal electrode to
The n (or p) MOS transistor of the OS transistor is turned on, a signal current corresponding to the incident light is taken out to the vertical readout line and stored in the charge storage means, the second switch is opened, and a signal current corresponding to the incident light is transferred from the horizontal shift register. The operation of sequentially closing the third switch and taking out the charge of the charge storage means to the signal line by the pulse of i=1 to i
1. A method for driving a MOS solid-state imaging device, characterized in that the processing is sequentially performed up to =L to obtain video information for one field.