JPH0413852B2 - - Google Patents
Info
- Publication number
- JPH0413852B2 JPH0413852B2 JP21938685A JP21938685A JPH0413852B2 JP H0413852 B2 JPH0413852 B2 JP H0413852B2 JP 21938685 A JP21938685 A JP 21938685A JP 21938685 A JP21938685 A JP 21938685A JP H0413852 B2 JPH0413852 B2 JP H0413852B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- epitaxial growth
- semiconductor substrate
- growth layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000003082 abrasive agent Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に関し、特に
半導体基板表面上に選択的に形成されたエピタキ
シヤル成長層の表面を平坦化する方法に関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for planarizing the surface of an epitaxial growth layer selectively formed on the surface of a semiconductor substrate. be.
第２図ａ，ｂは、従来の半導体基板表面上に選
択的に形成されたエピタキシヤル成長層の表面を
平坦化する半導体装置の製造方法を説明するため
の工程図である。この方法について説明すると、
まず、周知の適当な方法により、半導体基板１表
面上に、この半導体基板の表面の一部分が露出す
るように、絶縁膜パターン２たとえば酸化膜のパ
ターンを選択的に形成する。この後、絶縁膜パタ
ーン２をマスクとして半導体基板１の露出した部
分上にこの半導体基板と同種の材料によつて選択
的にエピタキシヤル成長層３を形成する〔第２図
ａ〕。次に、エピタキシヤル成長層３の表面を研
磨材を用いて研磨して平坦化する。３０はその表
面が平坦化されたエピタキシヤル成長層である
〔第２図ｂ〕。
FIGS. 2a and 2b are process diagrams for explaining a conventional method for manufacturing a semiconductor device in which the surface of an epitaxial growth layer selectively formed on the surface of a semiconductor substrate is planarized. To explain this method,
First, an insulating film pattern 2, such as an oxide film pattern, is selectively formed on the surface of the semiconductor substrate 1 by a well-known appropriate method so that a portion of the surface of the semiconductor substrate is exposed. Thereafter, using the insulating film pattern 2 as a mask, an epitaxial growth layer 3 is selectively formed on the exposed portion of the semiconductor substrate 1 using the same type of material as the semiconductor substrate (FIG. 2a). Next, the surface of the epitaxial growth layer 3 is polished and planarized using an abrasive. 30 is an epitaxially grown layer whose surface is flattened [FIG. 2b].
ところで、第２図ｂに示すように、選択的に形
成されたエピタキシヤル成長層３の表面を研磨材
を用いて研磨して平坦化すると、エピタキシヤル
成長層３０の表面近傍に研磨によるダメージ層４
を発生させてしまうという問題点があつた。
By the way, as shown in FIG. 2b, when the surface of the selectively formed epitaxial growth layer 3 is polished and flattened using an abrasive, a damaged layer due to polishing is created near the surface of the epitaxial growth layer 30. 4
There was a problem in that it caused .
この発明は上記のような問題点を解消するため
になされたもので、選択エピタキシヤル成長層の
表面を研磨材を用いて研磨して平坦化する場合に
おいて、研磨によりエピタキシヤル成長層に生じ
るダメージ層を除去できる半導体装置の製造方法
を得ることを目的とする。 This invention was made to solve the above-mentioned problems, and when the surface of a selective epitaxial growth layer is polished and flattened using an abrasive material, damage caused to the epitaxial growth layer due to polishing may occur. An object of the present invention is to obtain a method for manufacturing a semiconductor device in which layers can be removed.
この発明に係る半導体装置の製造方法は、半導
体基板表面上に選択的に形成されたエピタキシヤ
ル成長層と絶縁膜との表面を研磨材を用いて研磨
して平坦化する半導体装置の製造方法において、
上記研磨によりエピタキシヤル成長層に生じるダ
メージ層を熱酸化して酸化膜を形成し、次に等方
性または異方性エツチングによりこの酸化膜と上
記絶縁膜の表面層とを除去する方法である。
A method for manufacturing a semiconductor device according to the present invention includes polishing and planarizing the surfaces of an epitaxial growth layer and an insulating film selectively formed on a surface of a semiconductor substrate using an abrasive. ,
In this method, the damaged layer generated in the epitaxial growth layer by the above polishing is thermally oxidized to form an oxide film, and then this oxide film and the surface layer of the above insulating film are removed by isotropic or anisotropic etching. .
この発明においては、上記研磨によりエピタキ
シヤル成長層に生じるダメージ層は、このダメー
ジ層を熱酸化して酸化膜を形成し、この酸化膜を
上記絶縁膜の表面層と一緒にエツチング除去する
ことによつて除去される。
In this invention, the damaged layer generated in the epitaxial growth layer by the polishing is removed by thermally oxidizing the damaged layer to form an oxide film, and removing this oxide film together with the surface layer of the insulating film. It is then removed.
以下、この発明の実施例を図について説明す
る。なお、この実施例の説明において、従来の技
術の説明と重複する部分については適宜その説明
を省略する。
Embodiments of the present invention will be described below with reference to the drawings. In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.
第１図ａ，ｂ，ｃ，ｄは、この発明の実施例で
ある、半導体基板表面上に選択的に形成されたエ
ピタキシヤル成長層の表面を平坦化する半導体装
置の製造方法を説明するための工程図である。こ
の方法について説明すると、第１図ａ，ｂの工程
〔第２図ａ，ｂの工程と同じ〕を経た後、研磨に
より生じたエピタキシヤル成長層３０のダメージ
層４を酸化性雰囲気で高温熱処理して熱酸化膜５
を形成する。３１はエピタキシヤル成長層３０の
うち熱酸化されなかつた部分である〔第１図ｃ〕。
次に、フツ化水素酸水溶液を用いるエツチングま
たは異方性エツチングなど適当なエツチング方法
により、熱酸化膜５とマスクである絶縁膜２の表
面層とを除去することによつて、ダメージがなく
かつその表面が平坦なエピタキシヤル成長層３２
と、その表面が平坦な絶縁膜２０とを形成するこ
とができる〔第１図ｄ〕。 Figures 1a, b, c, and d are for explaining a method of manufacturing a semiconductor device, which is an embodiment of the present invention, for planarizing the surface of an epitaxial growth layer selectively formed on the surface of a semiconductor substrate. This is a process diagram. To explain this method, after going through the steps shown in FIG. 1 a and b (same as the steps shown in FIG. 2 a and b), the damaged layer 4 of the epitaxial growth layer 30 caused by polishing is subjected to high-temperature heat treatment in an oxidizing atmosphere. thermal oxide film 5
form. 31 is a portion of the epitaxially grown layer 30 that has not been thermally oxidized [FIG. 1c].
Next, by removing the thermal oxide film 5 and the surface layer of the insulating film 2, which is a mask, by an appropriate etching method such as etching using a hydrofluoric acid aqueous solution or anisotropic etching, there is no damage. Epitaxial growth layer 32 whose surface is flat
and an insulating film 20 whose surface is flat [FIG. 1d].
なお、上記実施例では、エピタキシヤル成長層
の表面を研磨して平坦化し、そのとき生じるダメ
ージ層を除去する場合について述べたが、この発
明は適当な方法によつて形成された選択ポリシリ
コン層についても適用することができる。 In the above embodiment, the surface of the epitaxially grown layer is polished to make it flat and the damaged layer generated at that time is removed. It can also be applied to
以上のようにこの発明によれば、半導体基板表
面上に選択的に形成されたエピタキシヤル成長層
と絶縁膜との表面を研磨材を用いて研磨して平坦
化する半導体装置の製造方法において、上記研磨
によりエピタキシヤル成長層に生じるダメージ層
を熱酸化して酸化膜を形成し、次に等方性または
異方性エツチングによりこの酸化膜と上記絶縁膜
の表面層とを除去するようにしたので、半導体基
板上に、ダメージ層のない平坦化された選択エピ
タキシヤル成長層と、平坦化された絶縁膜とを得
ることができる。
As described above, according to the present invention, in the method of manufacturing a semiconductor device, the surfaces of the epitaxial growth layer and the insulating film selectively formed on the surface of the semiconductor substrate are polished and planarized using an abrasive material. The damaged layer generated in the epitaxial growth layer by the above polishing is thermally oxidized to form an oxide film, and then this oxide film and the surface layer of the above insulating film are removed by isotropic or anisotropic etching. Therefore, a planarized selective epitaxial growth layer without a damaged layer and a planarized insulating film can be obtained on the semiconductor substrate.
第１図ａ，ｂ，ｃ，ｄは、この発明の実施例で
ある、半導体基板表面上に選択的に形成されたエ
ピタキシヤル成長層の表面を平坦化する半導体装
置の製造方法を説明するための工程図である。第
２図ａ，ｂは、従来の半導体基板表面上に選択的
に形成されたエピタキシヤル成長層の表面を平坦
化する半導体装置の製造方法を説明するための工
程図である。
図において、１は半導体基板、２は絶縁膜パタ
ーン、３，３０，３１，３２はエピタキシヤル成
長層、４はダメージ層、５は熱酸化膜である。な
お、各図中同一符号は同一または相当部分を示
す。
Figures 1a, b, c, and d are for explaining a method of manufacturing a semiconductor device, which is an embodiment of the present invention, for planarizing the surface of an epitaxial growth layer selectively formed on the surface of a semiconductor substrate. This is a process diagram. FIGS. 2a and 2b are process diagrams for explaining a conventional method for manufacturing a semiconductor device in which the surface of an epitaxial growth layer selectively formed on the surface of a semiconductor substrate is planarized. In the figure, 1 is a semiconductor substrate, 2 is an insulating film pattern, 3, 30, 31, 32 are epitaxial growth layers, 4 is a damaged layer, and 5 is a thermal oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
分が露出するように絶縁膜を選択的に形成し、前
記半導体基板の前記露出部分上に該半導体基板と
同種の材料によつて選択的にエピタキシヤル成長
層を形成し、前記エピタキシヤル成長層と前記絶
縁膜との表面層を研磨材を用いて研磨して平坦化
する半導体装置の製造方法において、 前記研磨により前記エピタキシヤル成長層に生
じるダメージ層を熱酸化して酸化膜を形成し、次
に等方性または異方性エツチングにより前記酸化
膜と、前記絶縁膜の表面層とを除去することを特
徴とする半導体装置の製造方法。[Scope of Claims] 1. An insulating film is selectively formed on the surface of a semiconductor substrate so that a portion of the surface of the semiconductor substrate is exposed, and a material of the same type as the semiconductor substrate is formed on the exposed portion of the semiconductor substrate. and selectively forming an epitaxial growth layer, and polishing a surface layer of the epitaxial growth layer and the insulating film using an abrasive material to planarize the surface layer, the method comprising: A semiconductor device characterized in that an oxide film is formed by thermally oxidizing a damaged layer generated in a growth layer, and then the oxide film and the surface layer of the insulating film are removed by isotropic or anisotropic etching. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21938685A JPS6278829A (en) | 1985-09-30 | 1985-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21938685A JPS6278829A (en) | 1985-09-30 | 1985-09-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6278829A JPS6278829A (en) | 1987-04-11 |
| JPH0413852B2 true JPH0413852B2 (en) | 1992-03-11 |
Family
ID=16734603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21938685A Granted JPS6278829A (en) | 1985-09-30 | 1985-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6278829A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234924A (en) * | 1988-07-25 | 1990-02-05 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JP2726488B2 (en) * | 1989-04-10 | 1998-03-11 | 株式会社東芝 | Method for manufacturing semiconductor device |
| FR2797714B1 (en) | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | PROCESS FOR PROCESSING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS |
-
1985
- 1985-09-30 JP JP21938685A patent/JPS6278829A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6278829A (en) | 1987-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH10233351A (en) | Structure of semiconductor substrate and manufacture of the same | |
| CA2130149A1 (en) | Sub-micron bonded soi by trench planarization | |
| JPH0413852B2 (en) | ||
| JP2807717B2 (en) | Manufacturing method of semiconductor substrate | |
| JPH01305534A (en) | Manufacture of semiconductor substrate | |
| JP2584639B2 (en) | Semiconductor substrate manufacturing method | |
| JP2779659B2 (en) | Method for manufacturing semiconductor device | |
| JPH056883A (en) | Manufacture of semiconductor substrate | |
| JPH0158660B2 (en) | ||
| JPH1022374A (en) | Manufacture of semiconductor device | |
| JPH0987100A (en) | Method for flattening surface of crystal substrate | |
| JPH0661340A (en) | Manufacture of clad semiconductor substrate | |
| JPH0416019B2 (en) | ||
| JPH04144134A (en) | Manufacture of semiconductor device | |
| JPH03141660A (en) | Manufacture of semiconductor device | |
| JPS63275137A (en) | Manufacture of semiconductor device | |
| JPH02215129A (en) | Manufacture of semiconductor device | |
| JPS6165447A (en) | Manufacture of semiconductor device | |
| JPH06163530A (en) | Selective oxidation of silicon substrate | |
| JPH0416018B2 (en) | ||
| JPS6387750A (en) | Manufacture of semiconductor device | |
| JPS6367736A (en) | Manufacture of semiconductor substrate | |
| JPH01225331A (en) | Manufacture of semiconductor device | |
| JPH02164037A (en) | Selecting oxidative separation | |
| JPH04142035A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |