JPH04134868A - Insulated gate type effect transistor - Google Patents

Insulated gate type effect transistor

Info

Publication number
JPH04134868A
JPH04134868A JP25812090A JP25812090A JPH04134868A JP H04134868 A JPH04134868 A JP H04134868A JP 25812090 A JP25812090 A JP 25812090A JP 25812090 A JP25812090 A JP 25812090A JP H04134868 A JPH04134868 A JP H04134868A
Authority
JP
Japan
Prior art keywords
depth
film
recessed part
formed
required
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25812090A
Inventor
Masahiro Hasegawa
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP25812090A priority Critical patent/JPH04134868A/en
Publication of JPH04134868A publication Critical patent/JPH04134868A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To relax a strain due to a stress of a LOCOS film and to reduce energy level which produces a leak current by forming a recessed part of a specified depth provided to a semiconductor substrate.
CONSTITUTION: In the figure, 11 is an Si substrate, 12 is a LOCOS film, and 13 is a recessed part formed in the Si substrate. After formation of an insulating film (SiO2 film) 17, the recessed part 13 is formed using etching method of high selectivity ratio of an oxide film and silicon. A buried layer 18 is formed for the purpose of forming and flattening of an electrode. Although a position and a size of the recessed part can be set arbitrarily in a range to satisfy a device size, a depth thereof is required which is at least a depth from a substrate surface to a LOCOS film bottom. Although formation method of a diffusion layer which constitutes a source/drain region 14 is arbitrary, a depth is required to acquire an effective gate length whereby a junction depth in a transverse direction does not make a transistor operation impossible.
COPYRIGHT: (C)1992,JPO&Japio
JP25812090A 1990-09-26 1990-09-26 Insulated gate type effect transistor Pending JPH04134868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25812090A JPH04134868A (en) 1990-09-26 1990-09-26 Insulated gate type effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25812090A JPH04134868A (en) 1990-09-26 1990-09-26 Insulated gate type effect transistor

Publications (1)

Publication Number Publication Date
JPH04134868A true JPH04134868A (en) 1992-05-08

Family

ID=17315781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25812090A Pending JPH04134868A (en) 1990-09-26 1990-09-26 Insulated gate type effect transistor

Country Status (1)

Country Link
JP (1) JPH04134868A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator

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