JPH04134509A - Personal computer - Google Patents

Abstract

PURPOSE:To reduce energy consumption by writing stop information from a system to a control register and stopping oscillation by a gate circuit synchronously with a memory cycle. CONSTITUTION:When the stop information is written, a control circuit 13 generates a stop signal synchronously with the memory cycle so as to stop the oscillating operation through an AND gate 14 since a memory 3 is accessed asynchronously with the operation cycle of the system according to a clock generated by an oscillation circuit 2. In order to start the oscillation again, it is necessary to write start information from the system to a control register 12, and the stop signal is canceled by the control circuit 13, to which the start information is written, so as to start the oscillation again. Thus, since the oscillating operation of the oscillation again. Thus, since the oscillating operation of the oscillation circuit is selectively stopped under the control of the system, the energy consumption can be more reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a personal computer in which low power consumption control is an important design issue.

(Prior Art) In the field of personal computers, the laptop type, which is small, lightweight, and convenient to carry, has become popular in place of the conventional desktop type.

Due to their characteristics, many personal computers of this type are powered by batteries. Therefore, low power consumption control becomes an important design issue.

Conventionally, when a personal computer or the like is waiting for a key input, the system performs memory access, etc. (loops at a specific part of the keyboard control routine) even though the system is in an idle state. Therefore, even when the key is waiting for human power, the same amount of power is consumed as usual. In order to reduce power consumption in battery-powered personal computers, it is common to reduce the operating frequency or gate the output of the oscillation circuit to slow down the operation.

(Problem to be solved by the invention) The conventional method of lowering the operating frequency or gating the output of the oscillation circuit when in an idle state completely eliminates unnecessary power consumption because the oscillation circuit itself is operating. It doesn't matter.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a personal computer that does not waste power when in an idle state, such as for a key worker.

[Structure of the Invention] (Problems to be Solved by the Invention) A personal computer of the present invention includes an oscillation circuit, a control register in which operation information for starting and stopping the oscillation circuit can be written by the system, and a control register in which operation information for starting and stopping the oscillation circuit can be written. It consists of a gate circuit that allows or prohibits the supply of the clock signal generated by the oscillation circuit to the system according to the input information, and a memory access control circuit that controls memory access according to the clock supplied via this gate. Ru. Further, the control circuit starts the memory operation according to permission information written to the control register by the system after a predetermined time period immediately after the oscillation circuit starts oscillating.

(Function) In the above configuration, in order to stop the operation of the oscillation circuit, first, the system writes stop information to the control register. Then, the oscillation is stopped by the gate circuit in synchronization with the memory cycle. To start oscillation again, start information is written to the control register, and memory operation is started after a certain period of time for the clock to stabilize.

This has the advantage that it is possible to reduce the power consumption of the negative layer, and in particular, in the case of a CMOS circuit, almost no power is required to be consumed.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. In the figure, reference numeral 1 indicates a gate array, including a control register 12, a memory control circuit 13, and an AND gate 14.
, an inverter gate 15, etc. The control register 12 is a register in which information on starting/stopping the oscillation circuit 2 can be written by the system. The above-mentioned starting/stopping information for the oscillation circuit 2 is supplied from a CPU (not shown) via the system bus 4. Control circuit 1
Reference numeral 3 controls generation of memory control signals and starting/stopping of the oscillation circuit 2. The AND gate 14 receives the stop signal from the control circuit 13 described above as input information, and gates the clock generated by the oscillation circuit 2. 15 is an inverter gate. AND gate 14 included in gate array 1 and inverter gate 1
5 will be explained here as some elements constituting the oscillation circuit 2.

2 is an oscillation circuit for generating a clock.

This oscillation circuit 2 includes, in addition to the above-mentioned AND gate 14 and inverter gate 15, a resistor 26, an oscillator 27, capacitors 28 and 29, and the like. The oscillator 27 is the oscillation circuit 2
This is the source of the clock frequency generated by Reference numeral 3 denotes a memory, which operates under the control of the control circuit 13.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. In order to stop the operation of the oscillation circuit 2, it is first necessary to write stop information from the system to the control register 12.

When the stop information is written, the control circuit 13 accesses the memory 3 asynchronously with the system operation cycle using the clock generated by the oscillation circuit 2, so it generates a stop signal in synchronization with the memory cycle and executes the AND gate. The oscillation operation is stopped via 14. In order to start oscillation again, it is necessary to write startup information to the control register 12 from the system. The control circuit 13 into which the activation information is written cancels the stop signal and restarts oscillation. Immediately after the oscillation starts, the oscillation is not yet stable, so the memory operation is started by an enable signal written into the control register 12 from the system after a certain period of time.

In this way, since the oscillation operation of the oscillation circuit is selectively stopped by system control, it is possible to realize lower power consumption in the negative layer.

[Effects of the Invention] As described above, according to the present invention, there is provided a gate circuit that permits/disables the supply of a clock generated by an oscillation circuit to a system according to information written in a control register by the system, and By being equipped with a memory access control circuit that controls memory access according to the clock supplied through the circuit, it is possible to reduce the power consumption of the − layer, and furthermore, it is possible to selectively stop the oscillation operation of the oscillation circuit. By configuring the peripheral circuits with CMOS circuits, it is possible to obtain the effect that almost no power is consumed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Gate array, 2... Oscillation circuit, 3... Memory, 4... System bus, 12... Control register, 13... Control circuit, 14... AND gate, 15
...Inverter gate, 27...Resonator.

Claims (2)

[Claims] (1) An oscillation circuit that generates a system operating clock;
A control register that allows the system to write start and stop operation information for this oscillation circuit, and a gate that allows or prohibits the supply of clock signals generated by the oscillation circuit to the system according to the information written to this control register. 1. A personal computer comprising: a circuit; and a memory access control circuit that controls memory access in accordance with a clock supplied via the gate circuit. (2) The personal computer according to claim (1), wherein the control circuit starts the memory operation according to permission information written to the control register by the system after a certain period of time after the oscillation circuit starts oscillating. .