JPH04133342A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH04133342A
JPH04133342A JP25585090A JP25585090A JPH04133342A JP H04133342 A JPH04133342 A JP H04133342A JP 25585090 A JP25585090 A JP 25585090A JP 25585090 A JP25585090 A JP 25585090A JP H04133342 A JPH04133342 A JP H04133342A
Authority
JP
Japan
Prior art keywords
package substrate
insulating film
circuits
semiconductor chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25585090A
Other languages
Japanese (ja)
Other versions
JPH0732211B2 (en
Inventor
Koji Minami
Akitsugu Maeda
Masaharu Ishikawa
Takeshi Kano
Toru Higuchi
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP25585090A priority Critical patent/JPH0732211B2/en
Publication of JPH04133342A publication Critical patent/JPH04133342A/en
Publication of JPH0732211B2 publication Critical patent/JPH0732211B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To attach a terminal pin to a package substrate even at a part where a semiconductor mounting part has been formed by a method wherein nearly the whole surface including the semiconductor mounting part on one face of the package substrate is covered with an insulating film. CONSTITUTION:A recessed part 14 at an insulating film 5 is fitted into a semiconductor mounting part 2 of a package substrate 1; outer-lead parts 16, 16,... protruding from the edges of the insulating film 5 are bonded to respective pads 13, 13,... of the package substrate 1 by using solder or the like; the insulating film 5 is bonded to the surface of the package substrate 1 by using resin adhesive and can be fixed to the package substrate 1. At the recessed part 14, a semiconductor chip 7 such as an IC is mounted on the semiconductor mounting part 2; wires 11 such as gold wires are bonded between the semiconductor chip 7 and inner-lead parts 15 of connecting circuits 6, 6,... formed on the insulating film 5. Thereby, the semiconductor chip 7 is connected to the connecting circuits 6, 6,.... Consequently, the semiconductor chip 7 is connected electrically to terminal pins 4 through circuits 12 formed on the package substrate 1 via the pads 13 from the connecting circuits 6.
JP25585090A 1990-09-25 1990-09-25 Semiconductor package Expired - Lifetime JPH0732211B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25585090A JPH0732211B2 (en) 1990-09-25 1990-09-25 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25585090A JPH0732211B2 (en) 1990-09-25 1990-09-25 Semiconductor package

Publications (2)

Publication Number Publication Date
JPH04133342A true JPH04133342A (en) 1992-05-07
JPH0732211B2 JPH0732211B2 (en) 1995-04-10

Family

ID=17284461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25585090A Expired - Lifetime JPH0732211B2 (en) 1990-09-25 1990-09-25 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH0732211B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7239024B2 (en) * 2003-04-04 2007-07-03 Thomas Joel Massingill Semiconductor package with recess for die

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7239024B2 (en) * 2003-04-04 2007-07-03 Thomas Joel Massingill Semiconductor package with recess for die

Also Published As

Publication number Publication date
JPH0732211B2 (en) 1995-04-10

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