JPH04132258A - Connecting body for semiconductor substrate and its connection - Google Patents
Connecting body for semiconductor substrate and its connectionInfo
- Publication number
- JPH04132258A JPH04132258A JP2254420A JP25442090A JPH04132258A JP H04132258 A JPH04132258 A JP H04132258A JP 2254420 A JP2254420 A JP 2254420A JP 25442090 A JP25442090 A JP 25442090A JP H04132258 A JPH04132258 A JP H04132258A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide resin
- silicon substrate
- semiconductor substrate
- layer
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 229920001721 polyimide Polymers 0.000 claims abstract description 28
- 239000009719 polyimide resin Substances 0.000 claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 43
- 229910052710 silicon Inorganic materials 0.000 abstract description 43
- 239000010703 silicon Substances 0.000 abstract description 43
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000002904 solvent Substances 0.000 abstract description 2
- 230000000593 degrading effect Effects 0.000 abstract 1
- 230000001066 destructive effect Effects 0.000 abstract 1
- 239000012298 atmosphere Substances 0.000 description 3
- 230000009477 glass transition Effects 0.000 description 3
- 125000005372 silanol group Chemical group 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920006259 thermoplastic polyimide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910008051 Si-OH Inorganic materials 0.000 description 1
- 229910006358 Si—OH Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006482 condensation reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920000592 inorganic polymer Polymers 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体基板の接続体およびその接続方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor substrate connection body and a connection method thereof.
従来のシリコン半導体基板どうしを接続する方法を図面
を用いて説明する。A conventional method for connecting silicon semiconductor substrates will be explained using drawings.
シラノール接合を利用して半導体基板を接続する方法は
、たとえば、新保により電子情報通信学会ｖｏ、１．７
０、Ｎｏ、６．ｐｐ５９３ （１９８７）に報告されて
いる。この方法では、第２図に示すように、鏡面研磨さ
れた第１および第２のシリコン基板１１．１２の表面に
シラノール基（Ｓｉ−ＯＨ）１３を吸着させたのち、こ
のシリコン基板を密着させた状態で加熱・加圧する。こ
の加熱・加圧処理によりＳ ｉ −ＯＨ＋ＨＯ−Ｓ ｉ
→５ｉ−０−８ｉなる反応が生じ、シリコン基板が接続
される。For example, a method of connecting semiconductor substrates using silanol bonding is described by Shinbo, Institute of Electronics, Information and Communication Engineers vo, 1.7.
0, No, 6. Reported in pp. 593 (1987). In this method, as shown in FIG. 2, silanol groups (Si-OH) 13 are adsorbed onto the mirror-polished surfaces of first and second silicon substrates 11 and 12, and then the silicon substrates are brought into close contact with each other. Heat and pressurize. Through this heating and pressure treatment, S i -OH+HO-S i
→5i-0-8i reaction occurs and the silicon substrate is connected.
またスピンオングラス（ＳｏＧ）層を介してシリコン基
板どうしを熱圧着する方法が山田、川崎により１９８６
年秋季第４７回応用物理学関連講演会講演予稿集ｐｐ４
９５に報告されている。この方法は、まず第３図（ａ）
に示すように、８００層５が形成された第１および第２
のシリコン基板ＩＡ、ＩＢをベークとしたのち密着させ
、第３図（ｂ）に示すように、大気中で加熱・加圧する
ことによりこのシリコン基板を接続するものである。Furthermore, in 1986, Yamada and Kawasaki developed a method of bonding silicon substrates together by thermocompression via a spin-on-glass (SoG) layer.
Proceedings of the 47th Applied Physics Related Lectures Fall 2019 pp4
It has been reported in 95. This method is first shown in Figure 3(a).
As shown in FIG.
After baking the silicon substrates IA and IB, they are brought into close contact with each other, and as shown in FIG. 3(b), the silicon substrates are connected by heating and pressurizing them in the atmosphere.
しかしながら、第２図に示したシラノール基１３の化学
反応を利用する場合には、シリコン基板表面どうしが接
触されている必要があるため、表面に凹凸のあるシリコ
ン基板を接続することはできない、また、接続温度が８
００”Ｃ以上であることから、すでにデバイスの形成さ
れているシリコン基板どうしを接続する目的には不向き
である。However, when using the chemical reaction of the silanol groups 13 shown in FIG. 2, the surfaces of the silicon substrates must be in contact with each other, so it is not possible to connect silicon substrates with uneven surfaces. , the connection temperature is 8
Since it is 00''C or more, it is not suitable for the purpose of connecting silicon substrates on which devices have already been formed.
一方、接着剤として熱硬化性の無機高分子材料である３
００層をスピンコードにより形成したシリコン基板どう
しを大気中で熱圧着する場合には、４００℃でシリコン
基板どうしを接続できる。この方法では８００層５によ
りシリコン基板表面の凸部３Ａ、３Ｂの段差をある程度
緩和することが可能であるが、完全に平坦面な８００層
５の表面を得ることはできない、この３００層の表面が
完全に平坦面でないシリコン基板どうしを大気中で熱圧
着した場合、熱硬化性である８００層５は粘性流動によ
り変形することができないため、第３図（ｂ）に示した
ように、ＳＯＧ層界面どうしの未接触部に気泡６が存在
してしまう、この気泡６の存在により、シリコン基板全
面にわたる均一な接続を得ることができないため、シリ
コン基板の接続強度が低下する。On the other hand, 3 is a thermosetting inorganic polymer material used as an adhesive.
When silicon substrates on which the 00 layer is formed using a spin cord are bonded together by thermocompression in the atmosphere, the silicon substrates can be bonded together at 400°C. In this method, it is possible to reduce the level difference between the convex portions 3A and 3B on the silicon substrate surface to some extent by using the 800 layer 5, but it is not possible to obtain a completely flat surface of the 800 layer 5. When silicon substrates that are not completely flat surfaces are bonded together by thermocompression in the atmosphere, the thermosetting 800 layer 5 cannot be deformed by viscous flow, so the SOG Air bubbles 6 are present in non-contact areas between layer interfaces. Due to the presence of air bubbles 6, it is not possible to obtain a uniform connection over the entire surface of the silicon substrate, thereby reducing the connection strength of the silicon substrate.
また、エポキシ樹脂接着剤を用いて半導体基板を接続す
ることも可能であるが、その接着耐熱性は１４０℃程度
であり耐熱性に劣る。It is also possible to connect semiconductor substrates using an epoxy resin adhesive, but its adhesive heat resistance is about 140° C., which is poor in heat resistance.
本発明の目的は既にデバイスの作り込まれていることに
より表面に凹凸の存在するシリコン基板どうしを、素子
の劣化や破壊をきたす恐れのない４５０℃以下の温度で
均一に接続し、かつその基板が２００°Ｃ以上の温度に
保持されても接続強度の低下しない半導体基板の接続体
およびその接続方法を提供することである。The purpose of the present invention is to uniformly connect silicon substrates, which have uneven surfaces due to device fabrication, at a temperature of 450 degrees Celsius or lower without causing any risk of deterioration or destruction of the elements, and to An object of the present invention is to provide a connecting body of semiconductor substrates that does not reduce the connection strength even when the semiconductor substrate is maintained at a temperature of 200° C. or higher, and a method for connecting the same.
（課題を解決するための手段）
本発明の半導体基板の接続体は、デバイスが形成され表
面に凹凸が存在する第１の半導体基板と、この第１の半
導体基板上に熱軟化性ポリイミド樹脂による接続された
第２の半導体基板とを有するものである。(Means for Solving the Problems) A semiconductor substrate connection body of the present invention includes a first semiconductor substrate on which a device is formed and has an uneven surface, and a thermoplastic polyimide resin formed on the first semiconductor substrate. and a second semiconductor substrate connected thereto.
また本発明の半導体基板の接続方法は、デバイスが形成
され表面に凹凸が存在する第１の半導体基板と第２の半
導体基板の少なくとも一方の半導体基板表面に熱軟化性
ポリイミド樹脂を塗布する工程と、前記第１の半導体基
板と第２の半導体基板表面を前記熱軟化性ポリイミド樹
脂層を介して真空中で密着させたのち、少なくとも熱軟
化性ポリイミド樹脂の軟化温度以上の温度に加熱し加工
する工程とを含んで構成される。Further, the method for connecting semiconductor substrates of the present invention includes a step of applying a thermosoftening polyimide resin to the surface of at least one of the first semiconductor substrate and the second semiconductor substrate on which a device is formed and which has irregularities. , After the surfaces of the first semiconductor substrate and the second semiconductor substrate are brought into close contact with each other in a vacuum via the thermosoftening polyimide resin layer, processing is performed by heating to a temperature at least higher than the softening temperature of the thermosoftening polyimide resin. It consists of a process.
（作用）
本発明に係る半導体基板の接続方法においては、熱軟化
温度がデバイスの熱破壊温度よりも低い熱軟化性ポリイ
ミド樹脂を使用することにより、すでにデバイスの形成
されている半導体基板どうしを接続することが可能とな
る。ポリイミド樹脂を接着剤として用いているため、高
温耐熱特性に優れた接続が得られる。また、熱圧着を真
空中で行っているため接着界面に気泡が存在することは
ない。さらに、下地デバイスの存在により塗布したポリ
イミド樹脂の表面に凹凸があったとしても、熱軟化温度
以上ではポリイミド樹脂の粘性流動が生じるため均一の
接続界面を得ることができる。(Function) In the method for connecting semiconductor substrates according to the present invention, semiconductor substrates on which devices have already been formed are connected by using a thermosoftening polyimide resin whose thermal softening temperature is lower than the thermal breakdown temperature of the device. It becomes possible to do so. Since polyimide resin is used as the adhesive, a connection with excellent high-temperature resistance can be obtained. Furthermore, since thermocompression bonding is performed in a vacuum, there are no air bubbles at the bonding interface. Furthermore, even if the surface of the applied polyimide resin is uneven due to the presence of the underlying device, a uniform connection interface can be obtained because viscous flow of the polyimide resin occurs above the thermal softening temperature.
（実施例）
以下に本発明の実施例を図面にもとすいて詳細に説明す
る。(Example) Examples of the present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を説明するための半導体チッ
プの断面図であり、ここでは熱軟化温度（ガラス転移温
度）が２５０〜３５０°Ｃの縮金型ポリイミド樹脂（耐
熱温度４２０°Ｃ程度）を用いた場合を例にとって述べ
る。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining one embodiment of the present invention. Here, a shrink mold polyimide resin having a thermal softening temperature (glass transition temperature) of 250 to 350°C (heat resistant temperature 420° An example will be described using a case where a
まず第１図（ａ）に示すように、表面に凸部３Ａが形成
された第１のシリコン基板１と表面に凸部３Ｂが形成さ
れた第２のシリコン基板２上にそれぞれ熱軟化性ポリイ
ミド樹脂層４をスピンコーティング法により形成する。First, as shown in FIG. 1(a), a thermoplastic polyimide film is placed on a first silicon substrate 1 having a convex portion 3A formed on its surface and a second silicon substrate 2 having a convex portion 3B formed on its surface. The resin layer 4 is formed by a spin coating method.
次いでポリイミド樹脂層４中の溶媒除去を目的とし、窒
素雰囲気中１００〜１５０°Ｃの温度で第１のシリコン
基板１と第２のシリコン基板２とを１時間程度ベークす
る。さらに、ポリイミド樹脂のイミド化反応（縮合反応
）を生じさせるため、窒素雰囲気中２５０〜３５０°Ｃ
の温度でキュアーする。次に第１のシリコン基板ｌと第
２のシリコン基板２とのポリイミド塗布面を向かい合わ
せる。Next, for the purpose of removing the solvent in the polyimide resin layer 4, the first silicon substrate 1 and the second silicon substrate 2 are baked at a temperature of 100 to 150° C. for about one hour in a nitrogen atmosphere. Furthermore, in order to cause an imidization reaction (condensation reaction) of the polyimide resin, the temperature was set at 250 to 350°C in a nitrogen atmosphere.
Cure at a temperature of Next, the polyimide coated surfaces of the first silicon substrate 1 and the second silicon substrate 2 are faced to each other.
次に第１図（ｂ）に示すように、向い合わせた第１及び
第２のシリコン基板１，２を真空室中に設置されている
下部加圧ヘッドＩＯＡ上に置く。しかる後、真空ポンプ
により真空室を１Ｏ−３Ｔｏｒｒ以下に減圧し、上部加
圧ヘッドＩＯＢおよび下部加圧ヘッドＩＯＡを介して第
１のシリコン基板１と第２のシリコン基板２とを加圧・
密着さ、せ、さらに上部加圧ヘッドＩＯＢおよび下部加
圧ヘッドＩＯＡに埋め込まれている発熱体により昇温、
加熱する。シリコン基板に加える圧力は１〜２０ｋｇ／
ａｍとし、また保持温度は少なくともシリコン基板に塗
布したポリイミド樹脂のガラス転移温度よりも高く、か
つその熱分解温度よりも低い温度としくここでは３５０
〜４００°Ｃ）、その温度で５分から３０分保持する。Next, as shown in FIG. 1(b), the first and second silicon substrates 1 and 2 facing each other are placed on the lower pressure head IOA installed in the vacuum chamber. Thereafter, the pressure in the vacuum chamber is reduced to 10-3 Torr or less using a vacuum pump, and the first silicon substrate 1 and the second silicon substrate 2 are pressurized via the upper pressure head IOB and the lower pressure head IOA.
The heating elements embedded in the upper pressure head IOB and the lower pressure head IOA raise the temperature.
Heat. The pressure applied to the silicon substrate is 1 to 20 kg/
am, and the holding temperature is at least higher than the glass transition temperature of the polyimide resin coated on the silicon substrate, and lower than its thermal decomposition temperature, and here, 350
~400°C) and hold at that temperature for 5 to 30 minutes.
その後、真空中で室温までシリコン基板１，２を冷却し
、さらに加圧ヘッドＩＯＡ、ＩＯＢへの荷重を解除し、
真空室を常圧にした後シリコン基板を取り出す。After that, the silicon substrates 1 and 2 are cooled to room temperature in a vacuum, and the load on the pressure heads IOA and IOB is released.
After the vacuum chamber is brought to normal pressure, the silicon substrate is taken out.
上述した本実施例によるシリコン基板の接続方法により
、引っ張り強度１９０ｋｇ／ｃｍ２以上のシリコン基板
接続体かえられた。By using the method for connecting silicon substrates according to the present embodiment described above, a silicon substrate connected body having a tensile strength of 190 kg/cm 2 or more was obtained.
キュアーした後の熱軟化性ポリイミド樹脂層４の表面は
デバイス層存在部分が凸状となっており、シリコン基板
どうしを密着させると、熱軟化性ポリイミド樹脂表面ど
うしが接触していない領域が存在してしまう。しかし本
実施例による方法では、真空中でシリコン基板どうしの
密着を行っているため、この未接触領域が気体で満たさ
れていることはない。さらに、真空室中で加圧ヘッド１
０Ａ、 ＩＯＢを介して加熱・加圧してゆくと、ポリイ
ミド樹脂のガラス転移温度を越えると粘性流動が生じ、
未接触領域に熱軟化性ポリイミド樹脂の一部が回り込む
ことにより、第１及び第２のシリコン基板１．２の全面
で均一な接続構造を得ることができる。なお、ポリイミ
ド樹脂は４００’Ｃ以上の耐熱温度を有することから、
本実施例により接続された半導体基板は高温耐熱性を有
する。After curing, the surface of the heat-softening polyimide resin layer 4 has a convex shape in the area where the device layer is present, and when the silicon substrates are brought into close contact with each other, there are regions where the heat-softening polyimide resin surfaces are not in contact with each other. It ends up. However, in the method according to this embodiment, since the silicon substrates are brought into close contact with each other in vacuum, this non-contact area is not filled with gas. Furthermore, the pressurizing head 1 in the vacuum chamber
When heated and pressurized through 0A and IOB, viscous flow occurs when the glass transition temperature of the polyimide resin is exceeded.
By partially wrapping the thermosoftening polyimide resin into the non-contact area, a uniform connection structure can be obtained over the entire surfaces of the first and second silicon substrates 1.2. In addition, since polyimide resin has a heat resistance temperature of 400'C or more,
The semiconductor substrate connected according to this embodiment has high temperature resistance.
ここに示した実施例では、すでにデバイスが形成され凹
凸のあるシリコン基板どうしを接続する場合を説明した
が、デバイスの形成されているシリコン基板のデバイス
の形成されていない基板上への接続や、凹凸のないシリ
コン基板どうしの接続も可能であることは自明である。In the embodiment shown here, a case has been described in which silicon substrates with unevenness on which devices have already been formed are connected to each other. It is obvious that it is also possible to connect silicon substrates without unevenness.
（発明の効果）
以上説明したように本発明によれば、表面に凹凸のある
、すなわちすでにデバイスの形成されてとなく接続でき
る効果がある。特にポリイミド樹脂を接着剤として用い
ているため、高温耐熱性の優れた接続体を得ることがで
きる。(Effects of the Invention) As described above, according to the present invention, there is an effect that connection is possible even when the surface is uneven, that is, a device has already been formed. In particular, since polyimide resin is used as the adhesive, a connection body with excellent high temperature resistance can be obtained.
第１図は本発明の一実施例を説明するための半導体チッ
プの断面図、第２図及び第３図は従来例を説明するため
の半導体チップの断面図である。
１、 ＩＡ、 １１−１・第１のシリコン基板、２．２
Ａ、 １２・・・第２のシリコン基板、３Ａ、 ３Ｂ・
・・凸部、４・・・ポリイミド樹脂層、５・・・ＳＯＧ
層、６・・・気泡、ＩＯＡ・・・下部加圧ヘッド、１０
Ｂ・・・上部加圧ヘッド、１３・・・シラノール基。FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a semiconductor chip for explaining a conventional example. 1. IA, 11-1・First silicon substrate, 2.2
A, 12... second silicon substrate, 3A, 3B.
...Convex portion, 4...Polyimide resin layer, 5...SOG
Layer, 6... Air bubble, IOA... Lower pressure head, 10
B... Upper pressure head, 13... Silanol group.
Claims (1)
導体基板、この第１の半導体基板上に熱軟化性ポリイミ
ド樹脂により接続された第２の半導体基板とを有するこ
とを特徴とする半導体基板の接続体。 ２、デバイスが形成され表面に凹凸が存在する第１の半
導体基板と第２の半導体基板の少なくとも一方の半導体
基板表面に熱軟化性ポリイミド樹脂を塗布する工程と、
前記第１の半導体基板と第２の半導体基板表面を前記熱
軟化性ポリイミド樹脂層を介して真空中で密着させたの
ち、少なくとも熱軟化性ポリイミド樹脂の軟化温度以上
の温度に加熱し加圧する工程とを含むことを特徴とする
半導体基板の接続方法。[Claims] 1. A first semiconductor substrate on which a device is formed and has an uneven surface, and a second semiconductor substrate connected to the first semiconductor substrate by a thermosoftening polyimide resin. A semiconductor substrate connection body characterized by: 2. Applying a thermosoftening polyimide resin to the surface of at least one of the first semiconductor substrate and the second semiconductor substrate on which a device is formed and which has irregularities;
After bringing the surfaces of the first semiconductor substrate and the second semiconductor substrate into close contact with each other in vacuum via the thermosoftening polyimide resin layer, heating and pressurizing the surfaces to a temperature at least equal to or higher than the softening temperature of the thermosoftening polyimide resin. A method for connecting a semiconductor substrate, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2254420A JPH04132258A (en) | 1990-09-25 | 1990-09-25 | Connecting body for semiconductor substrate and its connection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2254420A JPH04132258A (en) | 1990-09-25 | 1990-09-25 | Connecting body for semiconductor substrate and its connection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04132258A true JPH04132258A (en) | 1992-05-06 |
Family
ID=17264734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2254420A Pending JPH04132258A (en) | 1990-09-25 | 1990-09-25 | Connecting body for semiconductor substrate and its connection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04132258A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198159B1 (en) | 1997-03-28 | 2001-03-06 | Ube Industries, Ltd. | Bonded wafer, process for producing same and substrate |
| KR100462755B1 (en) * | 2001-12-11 | 2004-12-20 | 동부전자 주식회사 | Polyimide bake oven |
| US6940180B1 (en) * | 1996-09-05 | 2005-09-06 | Seiko Epson Corporation | Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit |
| JP2007513512A (en) * | 2003-12-08 | 2007-05-24 | コミッサリヤ ア レネルジ アトミック | Method for molecular crosslinking of electronic components on polymer films |
| JP2007208270A (en) * | 2007-02-15 | 2007-08-16 | Ube Ind Ltd | Stacked wafer, its manufacturing method, and substrate |
| JP2009147023A (en) * | 2007-12-12 | 2009-07-02 | Oki Semiconductor Co Ltd | Manufacturing method of semiconductor substrate |
| JP2015146337A (en) * | 2014-01-31 | 2015-08-13 | 東京エレクトロン株式会社 | Coating applicator and joint system |
| WO2018199117A1 (en) | 2017-04-28 | 2018-11-01 | 三井化学株式会社 | Substrate laminate and method for manufacturing substrate laminate |
| WO2020085183A1 (en) | 2018-10-26 | 2020-04-30 | 三井化学株式会社 | Substrate layered body manufacturing method and layered body |
| WO2022054839A1 (en) | 2020-09-10 | 2022-03-17 | 三井化学株式会社 | Composition, multilayer body and method for producing multilayer body |
| WO2023032923A1 (en) | 2021-09-06 | 2023-03-09 | 三井化学株式会社 | Composition for forming film for semiconductor, laminate, and substrate laminate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636136A (en) * | 1979-08-31 | 1981-04-09 | Fujitsu Ltd | Semiconductor device |
| JPS6130059A (en) * | 1984-07-20 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
| JPS62276581A (en) * | 1986-05-24 | 1987-12-01 | 株式会社日立製作所 | Liquid crystal display panel |
| JPS6355529A (en) * | 1986-08-25 | 1988-03-10 | Nec Corp | Active matrix liquid crystal display device and its production |
| JPS63142663A (en) * | 1986-12-04 | 1988-06-15 | Sharp Corp | Semiconductor device and its manufacture |
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1990
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636136A (en) * | 1979-08-31 | 1981-04-09 | Fujitsu Ltd | Semiconductor device |
| JPS6130059A (en) * | 1984-07-20 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
| JPS62276581A (en) * | 1986-05-24 | 1987-12-01 | 株式会社日立製作所 | Liquid crystal display panel |
| JPS6355529A (en) * | 1986-08-25 | 1988-03-10 | Nec Corp | Active matrix liquid crystal display device and its production |
| JPS63142663A (en) * | 1986-12-04 | 1988-06-15 | Sharp Corp | Semiconductor device and its manufacture |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6940180B1 (en) * | 1996-09-05 | 2005-09-06 | Seiko Epson Corporation | Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit |
| US7084517B2 (en) | 1996-09-05 | 2006-08-01 | Seiko Epson Corporation | Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit |
| US6198159B1 (en) | 1997-03-28 | 2001-03-06 | Ube Industries, Ltd. | Bonded wafer, process for producing same and substrate |
| KR100462755B1 (en) * | 2001-12-11 | 2004-12-20 | 동부전자 주식회사 | Polyimide bake oven |
| JP2007513512A (en) * | 2003-12-08 | 2007-05-24 | コミッサリヤ ア レネルジ アトミック | Method for molecular crosslinking of electronic components on polymer films |
| JP2007208270A (en) * | 2007-02-15 | 2007-08-16 | Ube Ind Ltd | Stacked wafer, its manufacturing method, and substrate |
| JP2009147023A (en) * | 2007-12-12 | 2009-07-02 | Oki Semiconductor Co Ltd | Manufacturing method of semiconductor substrate |
| JP2015146337A (en) * | 2014-01-31 | 2015-08-13 | 東京エレクトロン株式会社 | Coating applicator and joint system |
| WO2018199117A1 (en) | 2017-04-28 | 2018-11-01 | 三井化学株式会社 | Substrate laminate and method for manufacturing substrate laminate |
| KR20190136059A (en) | 2017-04-28 | 2019-12-09 | 미쓰이 가가쿠 가부시키가이샤 | Substrate laminated body and manufacturing method of a substrate laminated body |
| US11859110B2 (en) | 2017-04-28 | 2024-01-02 | Mitsui Chemicals, Inc. | Substrate laminated body and method of manufacturing substrate laminated body |
| WO2020085183A1 (en) | 2018-10-26 | 2020-04-30 | 三井化学株式会社 | Substrate layered body manufacturing method and layered body |
| KR20210060571A (en) | 2018-10-26 | 2021-05-26 | 미쓰이 가가쿠 가부시키가이샤 | Substrate laminate manufacturing method and laminate |
| WO2022054839A1 (en) | 2020-09-10 | 2022-03-17 | 三井化学株式会社 | Composition, multilayer body and method for producing multilayer body |
| WO2023032923A1 (en) | 2021-09-06 | 2023-03-09 | 三井化学株式会社 | Composition for forming film for semiconductor, laminate, and substrate laminate |
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