JPH04132231A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make the interface between a gate insulating film and a semiconductor clean and to enhance a transistor characteristic by a method wherein the gate insulating film and the semiconductor are formed continuously inside the same vacuum apparatus. CONSTITUTION:At least a gate electrode 2, a gate insulating film 3 and a non- single-crystal semiconductor layer 4 are formed on a substrate 1 in this order. In addition, a positive-type photoresist formed on the upper layer form the semiconductor layer is exposed from the rear of the substrate; and it is developed. Thereby, a photoresist pattern 5 whose pattern is the same as that of the gate electrode is formed. Impurity ions 6 are implanted into a source-drain region of the non-single-crystal semiconductor layer by using the pattern as a mask; after that, the photoresist pattern 5 is removed. Alternatively, an insulating film formed between the semiconductor layer and the photoresist pattern is etched by using the photoresist pattern 5 as a mask; the photo resist pattern is removed; and after that, impurity ions are implanted into the source-drain region of the semiconductor layer by using the insulating film as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor used for driving an image display device or the like.

[Prior Art] In recent years, thin film transistors (TPTs) have been actively developed for application to image display elements such as flat displays. In order to cope with the increase in the size of displays and the use of TFTs in peripheral drive circuits, it is desired to improve the TPT operating speed. Attempts have been made to reduce the parasitic capacitance between the gate and drain in order to improve the operating speed of the TPT, and forming the source train electrode in self-alignment with the gate electrode is an extremely effective method.

Taking laser polycrystalline semiconductor TPT as an example, we will explain the conventional manufacturing method of self-aligned TPT in which the source and drain regions are formed in self-alignment with the gate electrode by ion implantation.
This will be explained with reference to FIGS. 5(a) and 5(b).

A passivation film 52 is formed on a substrate 51 having insulating properties.
Stacking nine amorphous semiconductor layers 53 (FIG. 5(a)),
Polycrystalization is performed by laser beam irradiation, a pattern of a polycrystalline semiconductor thin film 56 is formed by photolithography, a gate insulating film 54 and a gate electrode material 55 are laminated thereon, and a gate electrode pattern is formed by photolithography again.

The gate insulating layer is also etched in the same pattern as the gate electrode (FIG. 5(b)). Here, impurity ions are doped into the polycrystalline semiconductor layer 56 using the gate electrode as a mask by ion implantation to activate the impurity ions. Heat treatment is performed to form source/drain regions. Furthermore, an interlayer insulating film is deposited, contact holes are formed on the source/drain regions, and source and drain electrodes are formed thereon.

[Problems to be Solved by the Invention] In the conventional method of using a gate electrode on a semiconductor layer as a mask for ion implantation, it is necessary to pattern the semiconductor layer into an island shape before forming the gate insulating film 54, which is difficult for transistor operation. The important interface between the semiconductor layer and the gate insulating film cannot be formed continuously. Therefore, it is difficult to make this interface clean and free from defects, and there is a problem in that it is difficult to obtain sufficient transistor characteristics and reliability.

[Means for Solving the Problems] The present invention has been made to solve the above problems, and includes a method for manufacturing a thin film transistor having an inverted staggered structure on an insulating substrate. , a gate insulating film, and a non-single-crystal semiconductor layer are formed in this order, and a positive photoresist formed above the semiconductor layer is exposed to light from the back side of the substrate and developed to form the same pattern as the gate electrode. A method for manufacturing a thin film transistor, characterized in that a photoresist pattern is formed, impurity ions are implanted into a source/drain region of a non-single crystal semiconductor layer using this pattern as a mask, and then the photoresist pattern is removed; In a method for manufacturing a thin film transistor with an inverted stagger structure on a substrate having a substrate, at least a gate electrode, a gate insulating film, and a non-single crystal semiconductor layer are formed in this order on the substrate, and a positive type thin film transistor formed above the semiconductor layer is further provided. A photoresist pattern identical to the gate electrode is formed by exposing and developing the photoresist from the back side of the substrate, and using this pattern as a mask, the insulating film formed between the semiconductor layer and the photoresist pattern is etched. The present invention also provides a method for manufacturing a thin film transistor, characterized in that after removing the photoresist pattern, impurity ions are implanted into the source/drain regions of the semiconductor layer using the insulating film as a mask.

The present invention will be explained below with reference to the drawings.

FIG. 1 shows a cross-sectional view of TPT showing the manufacturing method of the present invention, and the steps proceed in the order of FIGS. 1(a), (b), and (c). First, a gate electrode material such as chromium (Cr) or tantalum (Ta) is deposited on a transparent and insulating substrate 1 made of glass, ceramic, plastic, etc., as required, by an evaporation method such as an electron beam heating evaporation method. , a pattern of the gate electrode 2 is formed by photolithography, and SiO, 5iON, Si
A gate insulating film 3 made of N or the like and an amorphous semiconductor layer 4 made of SL, Ge or the like are deposited, and the amorphous semiconductor layer 4 is polycrystallized by irradiation with laser light if necessary. Note that if there is no need to polycrystallize the amorphous semiconductor layer 4, laser light irradiation is not performed.

Here, a positive photoresist is formed by a method such as coating,
By exposing and developing the substrate 1 from the back surface, a positive photoresist pattern 5 having the same pattern as the gate electrode is formed in a self-aligned manner (FIG. 1(a)). Using this photoresist pattern 5 as a mask, impurity ions 6 such as phosphorus (P), boron (B), and arsenic (As) are doped into the portions of the amorphous semiconductor layer 4 that will become the source and drain regions by ion implantation ( Figure 1(b)). After removing the photoresist pattern 5, heat treatment is performed to activate the impurity ions as necessary. Note that this heat treatment is not performed when the activation is not necessary.

A semiconductor thin film is patterned by photolithography, an insulating film 7 of SiO, 5iON, SiN, etc. is deposited thereon, a contact hole is formed on the source/drain region, and a source electrode/train electrode 8 is formed thereon. .

By the way, as shown in FIG. 2 in FIG. 1(b),
After patterning the amorphous semiconductor layer 4, a photoresist pattern 5 may be formed by backside exposure, ion implantation 6, and laser light irradiation may be performed. Alternatively, as shown in FIG. 3, an insulating film 7 may be deposited on the amorphous semiconductor layer 4, a photoresist pattern 5 may be formed thereon by back exposure, and ion implantation 6 may be performed from above the insulating film 7. However, ions may be implanted after etching the insulating film 7 using this photoresist pattern 5. Alternatively, as shown in FIG. 4, after etching the insulating film 7, removing the photoresist pattern 5,
Ion implantation may be performed using the insulating film 7 as a mask and reducing the ion implantation energy.

Note that the substrate 1 needs to have transparency for the wavelength used for the exposure. For example, when using visible light, the substrate 1 must be transparent.

As the semiconductor of the amorphous semiconductor layer 4, a so-called microcrystalline semiconductor or a polycrystalline semiconductor containing fine crystal grains with a grain size of less than 50 μm can be used instead of an amorphous semiconductor that is a non-single crystal semiconductor. When a polycrystalline semiconductor is used, if necessary, laser irradiation is performed later to improve crystallinity and improve the current amplification factor of TPT. Thus, amorphous semiconductors, microcrystalline semiconductors, and polycrystalline semiconductors are collectively referred to as non-single crystal semiconductors.

[Example] Example 1 The present embodiment will be described below with reference to FIG.

Cr 60 nu was deposited on the glass substrate 1 by electron beam heating evaporation method, and the gate electrode 2 was formed by photolithography.
A gate insulating film 3 made of 200 nm 5LON and an amorphous semiconductor layer 4 made of A-3I with a thickness of 100 I are laminated thereon by plasma CVD, and the semiconductor layer is irradiated with laser light. was polycrystallized. Here, a positive photoresist (OF P manufactured by Tokyo Ohka Co., Ltd.
A photoresist pattern 5 having the same pattern as the gate electrode was formed in a self-aligned manner by applying R-800), exposing it to light from the back surface of the substrate, and developing it. Using this photoresist pattern as a mask, P ions 6 were doped into the source/drain regions of the semiconductor layer using the ion implantation method at an acceleration voltage of 1 (l KeV and a dose of 2XlO).The photoresist pattern 5 was doped with oxygen. After removal by plasma, heat treatment was performed to activate impurity ions.Poly-3L was removed by photolithography.
was patterned into an island shape, an insulating film 7 made of 200 nm of 5LON was deposited thereon by plasma CVD, contact holes were formed on the source/drain regions, and source electrodes/train electrodes 8 were formed thereon. .

In this way, 100 TPTs were formed on the same substrate,
As a result of measuring the conductivity of the source/drain region, it was found that 100
All TPTs were greater than or equal to about 80 Ω-C-1.

Example 2 This embodiment will be described below with reference to FIG.

Cr 60r+a+ is deposited on a glass substrate 61 by electron beam heating evaporation, a gate electrode 62 pattern is formed by photolithography, and a Blaz? Gate insulating film 6 made of 5iON 200nm is formed by CVD method.
3. Amorphous semiconductor layer (a
-Si) 64 and 200 as the protective insulating film 65
5iON was laminated to a certain thickness. Here, a positive type photoresist (OF PR-800 manufactured by Tokyo Ohka Co., Ltd.) is applied, exposed to light from the back surface of the glass substrate 61, and developed to form a photoresist with the same pattern as the gate electrode 63 in a self-aligned manner. A protective insulating film 65 of 5iON was etched onto the mask.

After removing the photoresist with a resist stripping solution, P ions 6 are injected into the source/drain regions of the a-SL layer 64 using an ion implantation method using the protective insulating film as a mask.
Doping was performed under the conditions of an accelerating voltage of 5 KeV and a dose of 2×10”.

Protective insulation 11165, a- by photolithography
The Si layer 64 is patterned into an island shape, and BRAZE vC is formed on it.
An insulating film 67 made of 5LON 300 nm is deposited by the VD method, contact holes are formed on the source/drain regions, and source/drain electrodes 68 are formed on the contact holes.
was formed.

[Effects of the Invention] The thin film transistor of the present invention has an inverted staggered structure, and since the gate insulating film and the semiconductor can be formed continuously in the same vacuum device, the interface between them can be made clean, and the transistor Characteristics can be improved.

The field effect mobility of TPT with a conventional structure is approximately 15 cm”/
Vs, whereas in the TPT according to the present invention, it is 50
cm”/Vs or more, an improvement of more than three times.

[Brief explanation of the drawing]

Figure 1 (a), (b), and (c) show the TP of the present invention.
FIGS. 2A and 2B are cross-sectional views sequentially showing a method for manufacturing a TPT, and FIGS. 2 to 4 are cross-sectional views showing a method for manufacturing a TPT according to the present invention. Fifth
Figures (a) and (b) are cross-sectional views sequentially showing a conventional TPT (7) manufacturing method. Figure 6(a). (b) is a cross-sectional view sequentially showing a method for manufacturing TPT according to Example 2. 1: Substrate 2: Gate electrode 3: Gate insulating film 4: Amorphous semiconductor layer 6: Impurity ion 52: Passivation film 2 (support) Ru ↓ ↓ ~ 6 ↓

Claims (3)

[Claims] (1) In a method for manufacturing a thin film transistor with an inverted staggered structure on an insulating substrate, at least a gate electrode, a gate insulating film, and a non-single crystal semiconductor layer are formed in this order on the substrate, and further formed in a layer above the semiconductor layer. The positive photoresist thus prepared is exposed to light from the back side of the substrate and developed to form a photoresist pattern with the same pattern as the gate electrode, and using this pattern as a mask, the source/drain regions of the non-single crystal semiconductor layer are exposed. 1. A method of manufacturing a thin film transistor, comprising removing the photoresist pattern after implanting impurity ions. (2) In a method for manufacturing a thin film transistor with an inverted staggered structure on an insulating substrate, at least a gate electrode, a gate insulating film, and a non-single crystal semiconductor layer are formed in this order on the substrate, and further formed in a layer above the semiconductor layer. A photoresist pattern identical to the gate electrode is formed by exposing and developing the positive photoresist from the back side of the substrate, and using this pattern as a mask, a pattern is formed between the semiconductor layer and the photoresist pattern. A method for manufacturing a thin film transistor, comprising: etching the insulating film, removing the photoresist pattern, and implanting impurity ions into the source/drain regions of the semiconductor layer using the insulating film as a mask. (3) A thin film transistor manufactured by the manufacturing method according to claim (1) or claim (2).