JPH04129258A - Surface mounting type semiconductor device - Google Patents

Surface mounting type semiconductor device

Info

Publication number
JPH04129258A
JPH04129258A JP2250591A JP25059190A JPH04129258A JP H04129258 A JPH04129258 A JP H04129258A JP 2250591 A JP2250591 A JP 2250591A JP 25059190 A JP25059190 A JP 25059190A JP H04129258 A JPH04129258 A JP H04129258A
Authority
JP
Japan
Prior art keywords
outside lead
lead terminals
semiconductor device
external lead
alternately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2250591A
Other languages
Japanese (ja)
Inventor
Tomoaki Kato
友明 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP2250591A priority Critical patent/JPH04129258A/en
Publication of JPH04129258A publication Critical patent/JPH04129258A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H10W74/00—

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To alternately shift the positions of the outside lead terminal tip parts to be connected to a substrate for mounting in order to prevent a short- circuit accident of the lead terminals by making the length of the outside lead terminals projected from an element sealing member of the outside lead terminals to be alternately different. CONSTITUTION:A short outside lead terminal 5 and a long outside lead terminal 6 are alternately used as the outside lead terminals to be mounted of a sealing material 4 of a semiconductor device 1 to alternately arrange the tip parts 3 thereof. As this result, an interval, L1 between the neighboring outside lead terminal tip parts 3 in mounting at the time of connection to a substrate for mounting is widened. Thereby, poor connection such as solder bridging due to a connection material such as solder at the time of mounting becomes hard to be generated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は表面実装型半導体装置に関し、特にその外部リ
ード端子の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a surface-mounted semiconductor device, and particularly to the structure of its external lead terminal.

〔従来の技術〕[Conventional technology]

従来の表面実装型半導体装置は、第２図（ａ）。 A conventional surface-mounted semiconductor device is shown in FIG. 2(a).

（ｂ）に示すように、半導体装置１の封止材料４に取付
けられた外部リード端子６の長さが同一で、実装用基板
に接合される外部リード端子６の長さが同一で実装用基
板に接合される外部リード端子先端部３の位置が平行位
置にあり、その先端部の間隔Ｌ２が一定となる構造であ
った。As shown in (b), the lengths of the external lead terminals 6 attached to the sealing material 4 of the semiconductor device 1 are the same, and the lengths of the external lead terminals 6 bonded to the mounting board are the same, The structure was such that the positions of the external lead terminal tip portions 3 to be bonded to the substrate were in parallel positions, and the distance L2 between the tip portions was constant.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来の表面実装型半導体装置は、外部リード端子６
の長さが一定であるなめ、実装用基板に接合される外部
リード端子先端部３の位置が全て平行位置で、かつ外部
リード端子先端部の間隔Ｌ２が狭い状態であるため、そ
の実装の際に外部リード端子先端部同志が半田等の接合
材料により短絡するブリッジという接合不良になり易い
問題があった。特に、半導体装置の端子数が多くなり、
外部リード端子間隔Ｌ２が狭くなるにつれて、この問題
は大きくなる。This conventional surface-mounted semiconductor device has an external lead terminal 6
Since the length is constant, the positions of the external lead terminal tips 3 to be bonded to the mounting board are all in parallel positions, and the interval L2 between the external lead terminal tips is narrow, so when mounting However, there is a problem in that the tip ends of external lead terminals are easily short-circuited by a bonding material such as solder, resulting in a bonding defect called bridge. In particular, as the number of terminals on semiconductor devices increases,
This problem becomes more serious as the external lead terminal interval L2 becomes narrower.

本発明の目的は、このような欠点を除き、外部リード端
子の間隔を実質的に広くでき、リード端子の短絡事故を
防止できるようにした半導体装置を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which eliminates such drawbacks, allows the interval between external lead terminals to be substantially widened, and prevents short-circuit accidents of the lead terminals.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の表面実装型半導体装置の構成は、外部リード端
子の素子封止部材から突出した長さを交互に異ならせる
ことにより、実装用基板に接続される外部リード端子先
端部の位置を交互にずらせるようにしたことを特徴とす
る。The structure of the surface-mounted semiconductor device of the present invention is such that the lengths of the external lead terminals protruding from the element sealing member are alternately varied, thereby alternating the positions of the tips of the external lead terminals connected to the mounting board. It is characterized by being made to shift.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の一実施例の表面実装型
半導体装置の平面図およびその拡大断面図である０本実
施例は、半導体装置１の封止材料４に取付けられる外部
リード端子として短い外部リード端子５と長い外部リー
ド端子６とを交互に用いて、その先端部３が互い違いに
配置されることにより、実装用基板に接合される際の実
際に隣り合う外部リード端子先端部３の間隔Ｌ１を広く
することができるようにしたものである。FIGS. 1(a) and 1(b) are a plan view and an enlarged cross-sectional view of a surface-mounted semiconductor device according to an embodiment of the present invention. By alternately using short external lead terminals 5 and long external lead terminals 6 as external lead terminals, and arranging their tips 3 alternately, the external leads that are actually adjacent to each other when bonded to the mounting board are The space L1 between the terminal tips 3 can be widened.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、表面実装型半導体装置の
外部リード端子の長いものと短かいものとを互い違いに
配置することにより、実装用基板に接合される際の実装
に隣り合う外部リード端子先端部の間隔を広くすること
ができ、実装時に半田等の接合材料による半田ブリッジ
等の接合不良が発生しにくいという効果がある。特に外
部リード端子間の間隔が狭くなった場合、その効果は大
きい。As explained above, the present invention has the advantage of alternately arranging the long and short external lead terminals of a surface-mounted semiconductor device so that the external lead terminals adjacent to the mounting board when bonded to a mounting board are arranged alternately. It is possible to widen the distance between the tips, and this has the effect that bonding defects such as solder bridging due to bonding materials such as solder are less likely to occur during mounting. This effect is particularly significant when the distance between the external lead terminals becomes narrow.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は本発明の一実施例の表面実装型
半導体装置の平面図およびその拡大断面図、第２図（ａ
）、（ｂ）は従来の表面実装型半導体装置の一例の平面
図およびその拡大断面図である。 １・・・半導体装置、２・・・外部リード端子部、３・
・・外部リード端子先端部、４・・・封止材料、５・・
・短い外部リード端子、６・・・長い外部リード端子、
Ｌ１＋Ｌ２・・・リード端子先端間隔。FIGS. 1(a) and 1(b) are a plan view and an enlarged sectional view of a surface-mounted semiconductor device according to an embodiment of the present invention, and FIG.
) and (b) are a plan view and an enlarged sectional view of an example of a conventional surface-mounted semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... External lead terminal part, 3...
... External lead terminal tip, 4... Sealing material, 5...
・Short external lead terminal, 6...Long external lead terminal,
L1+L2... Distance between lead terminal tips.

Claims (1)

【特許請求の範囲】[Claims] 外部リード端子の素子封止部材から突出した長さを交互
に異ならせることにより、実装用基板に接続される外部
リード端子先端部の位置を交互にずらせるようにしたこ
とを特徴とする表面実装型半導体装置。A surface mount device characterized in that the lengths of the external lead terminals protruding from the element sealing member are alternately varied so that the positions of the tips of the external lead terminals connected to the mounting board are alternately shifted. type semiconductor device.
JP2250591A 1990-09-20 1990-09-20 Surface mounting type semiconductor device Pending JPH04129258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2250591A JPH04129258A (en) 1990-09-20 1990-09-20 Surface mounting type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2250591A JPH04129258A (en) 1990-09-20 1990-09-20 Surface mounting type semiconductor device

Publications (1)

Publication Number Publication Date
JPH04129258A true JPH04129258A (en) 1992-04-30

Family

ID=17210169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2250591A Pending JPH04129258A (en) 1990-09-20 1990-09-20 Surface mounting type semiconductor device

Country Status (1)

Country Link
JP (1) JPH04129258A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557143A (en) * 1993-09-16 1996-09-17 Rohm Co., Ltd. Semiconductor device having two staggered lead frame stages
KR20030053161A (en) * 2001-12-22 2003-06-28 삼성전자주식회사 Semiconductor device and method for manufacturing thereof
US7723834B2 (en) * 2006-09-06 2010-05-25 Samsung Electronics Co., Ltd. POP package and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557143A (en) * 1993-09-16 1996-09-17 Rohm Co., Ltd. Semiconductor device having two staggered lead frame stages
KR20030053161A (en) * 2001-12-22 2003-06-28 삼성전자주식회사 Semiconductor device and method for manufacturing thereof
US7723834B2 (en) * 2006-09-06 2010-05-25 Samsung Electronics Co., Ltd. POP package and method of fabricating the same

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