JPH04129241A - Inspection device - Google Patents

Inspection device

Info

Publication number
JPH04129241A
JPH04129241A JP25058190A JP25058190A JPH04129241A JP H04129241 A JPH04129241 A JP H04129241A JP 25058190 A JP25058190 A JP 25058190A JP 25058190 A JP25058190 A JP 25058190A JP H04129241 A JPH04129241 A JP H04129241A
Authority
JP
Japan
Prior art keywords
master image
section
defect
semiconductor substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25058190A
Other languages
Japanese (ja)
Inventor
Satoyuki Yanase
簗瀬 聡之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25058190A priority Critical patent/JPH04129241A/en
Publication of JPH04129241A publication Critical patent/JPH04129241A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To inspect a semiconductor device without being subject to the influence of the defect of an exposure device or the defect of a reticle by installing a simulator section preparing master image patterns color-coded from the quality of materials and thickness of each layer and a comparison checking section comparing and checking the master image patterns and the patterns of pellets displayed as the master image patterns. CONSTITUTION:When a defect inspection in the gate wiring process of a dynamic RAM is performed, the mask pattern data of each layer up to a gate wiring from the formation of a field are added in a simulator section 6 first, and the added data are stained by using a refractive index, etc., from the quality of materials and thickness of each layer. Master image patterns formed by the simulator section 6 are used as master patterns, and semiconductor pellets 8 on a semiconductor substrate 4 placed on a stage 3 and pattern images acquired by observing the pellets 8 by an optical system 2 and a camera 1 are compared and checked by employing a comparison checking section 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造工程の拡散工程中で、ある
特定工程までの半導体基板における構造上の欠陥〈例え
ば塵の付着など)の数やその大きさを検査する欠陥検査
装置に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the number of structural defects (such as adhesion of dust) on a semiconductor substrate up to a certain step during the diffusion step of the manufacturing process of a semiconductor device. The present invention relates to a defect inspection device that inspects defects and their sizes.

〔従来の技術〕[Conventional technology]

第2図は従来の欠陥検査装置の一例における概略を示す
図である。従来、この種の欠陥検査装置は、第2図に示
すように、半導体装置4は搭載し、X、Y方向に移動す
るステージ3と、半導体ペレット8(一つの集積回路領
域)の一部あるいは全部を観察するための光学系2及び
カメラ1と、隣接する二つの半導体ベレット8の同一部
分を観察して得られた画像を蓄積するメモリー部9と、
この二つの画像を画素毎に信号化して、それぞれを比較
検査する比較検査部10と、比較検査した結果を蓄積す
るデータ拡納部11とを有している。
FIG. 2 is a diagram schematically showing an example of a conventional defect inspection apparatus. Conventionally, this type of defect inspection apparatus, as shown in FIG. 2, has a semiconductor device 4 mounted thereon, a stage 3 that moves in the an optical system 2 and a camera 1 for observing the whole, a memory section 9 for storing images obtained by observing the same part of two adjacent semiconductor pellets 8;
It has a comparison inspection section 10 that converts these two images into signals for each pixel and compares and inspects them, and a data expansion section 11 that stores the results of the comparison inspection.

次に、この欠陥検査装置の動作について説明する。まず
ステージ3に載置された半導体基板4をX、Y方向に移
動し、となり合った二つの半導体ベレット8の同一部分
を光学系2とカメラ1により撮像する。次に、カメラ1
で観察して得られた二つの像を比較検査部10で、カメ
ラ1の画素毎に信号レベルについて比較し、その違いや
異なる信号レベルを有する画素の拡がりから欠陥の有無
と欠陥の寸法を判断する。第3図は従来の欠陥検査装置
の他の一例における概略を示す図である。
Next, the operation of this defect inspection device will be explained. First, the semiconductor substrate 4 placed on the stage 3 is moved in the X and Y directions, and the optical system 2 and camera 1 take images of the same portion of two adjacent semiconductor pellets 8. Next, camera 1
The comparison inspection unit 10 compares the two images obtained by observing the signal level for each pixel of the camera 1, and determines the presence or absence of a defect and the size of the defect based on the difference and the spread of pixels with different signal levels. do. FIG. 3 is a diagram schematically showing another example of a conventional defect inspection device.

また、他の欠陥検査装置は、第3図に示すように、半導
体基板4をX、Y方向に移動するステージ3と、半導体
ペレット8の一部あるいは全部を観察するための光学系
2及びカメラ1と、同種の半導体ペレット8の同一部分
の像を複数積算、蓄積するための積算メモリー部12と
、検出される半導体ペレット8の像と蓄積された像との
比較検査を行う検査部13とからなるものがある。この
装置の検査方法は、まずステージ3に載置された半導体
基板4をX、Y方向に移動し、同種の半導体ペレット8
の同一部分につき、ベレットを変えて最低50個以上観
察しその度に得られた像を積算し、さらに平均化して積
算メモリー部12に格納する。この平均化像をマスター
イメージとして検査すべき半導体ペレット8の像を取り
込み、得られた像との比較検査を行う。
Further, as shown in FIG. 3, another defect inspection apparatus includes a stage 3 that moves the semiconductor substrate 4 in the X and Y directions, an optical system 2 and a camera for observing part or all of the semiconductor pellet 8. 1, an integration memory unit 12 for integrating and storing a plurality of images of the same portion of the same type of semiconductor pellet 8, and an inspection unit 13 for performing a comparative inspection between the detected image of the semiconductor pellet 8 and the accumulated image. There is something that consists of The inspection method of this device is to first move the semiconductor substrate 4 placed on the stage 3 in the X and Y directions, and then
At least 50 images are observed for the same part of the image using different pellets, and the images obtained each time are integrated, further averaged, and stored in the integration memory section 12. Using this averaged image as a master image, an image of the semiconductor pellet 8 to be inspected is captured, and a comparison inspection with the obtained image is performed.

この検査は実際の半導体ペレット8の像とマスターイメ
ージとを画素毎に比較し、信号レベルの違いと異なる信
号レベルの画素の拡がりから欠陥の有無及びその大きさ
を判断していた。
In this inspection, the image of the actual semiconductor pellet 8 and the master image are compared pixel by pixel, and the presence or absence of a defect and its size are determined from the difference in signal level and the spread of pixels with different signal levels.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上述べた前記欠陥検査装置では、それぞれに共通の問
題点がある。例えば、前者の欠陥検査装置では、半導体
基板上の隣接し合うベレットを比較検査を行うことによ
って、検査を行っているが、もしベレットの製造過程で
用いられるレジストに転写するための縮小投影露光装置
のレチクルのパターンが一つしかなく、かつ異物等の欠
陥がこのパターンに存在したとすると、このレチクルに
よりパターンを転写されたベレットは全て同一の欠陥を
有することとなり本装置ではこの種の欠陥は検知できな
いという問題がある。しかし、縮小投影露光装置で用い
られるレチクルには、複数個分の半導体ベレット用のパ
ターンが刻まれているため、その各々の同一箇所に同じ
形状の欠陥が発生する確率は皆無に近いので、本装置に
よる二つのベレットの比較検査でも対処できる。一方、
今後の大規模集積化された半導体装置、例えば、10M
b i tDRAMなどでは、その外形寸法が縮小投影
露光装置の露光領域(20+uX20mm程度)とほぼ
同じくらいになり、複数個分のパターンをレチクル毎に
刻み同時に露光することが不可能となる。また、マイコ
ンのゲートアレイのように現在でも寸法の大きいものは
本装置のような欠陥検査を行うことができないのが現状
である。この点は後者の装置でも同じことが言える。た
だし、後者の装置の場合複数のレチクルを用い、それぞ
れのレチクルで露光された半導体基板上のベレットにつ
き画像を積算してゆけば、マスターイメージを作成する
ことが可能である。しかしながら縮小投影露光装置の光
学系自体に異物が付着しておこる同様な欠陥については
検出能力は全くない 本発明の目的は、かかる問題を解消する欠陥検査装置を
提供することである。
The defect inspection apparatuses described above have common problems. For example, the former type of defect inspection equipment performs inspection by comparatively inspecting adjacent pellets on a semiconductor substrate. If there is only one reticle pattern, and this pattern has a defect such as a foreign object, all the pellets to which the pattern has been transferred by this reticle will have the same defect, and this device will not be able to handle this type of defect. The problem is that it cannot be detected. However, since the reticle used in a reduction projection exposure system is engraved with patterns for multiple semiconductor bullets, the probability that a defect with the same shape will occur in the same location on each of the reticles is almost zero, so Comparative inspection of two pellets using a device can also be used. on the other hand,
Future large-scale integrated semiconductor devices, e.g. 10M
In a bit DRAM, the external dimensions are almost the same as the exposure area of a reduction projection exposure device (approximately 20+u×20 mm), making it impossible to inscribe a plurality of patterns for each reticle and expose them simultaneously. Furthermore, even now, it is not possible to perform defect inspection on large-sized items such as gate arrays of microcomputers as with this device. The same can be said for the latter device. However, in the case of the latter device, it is possible to create a master image by using a plurality of reticles and integrating images of the pellets on the semiconductor substrate exposed by each reticle. However, there is no ability to detect similar defects caused by foreign matter adhering to the optical system itself of the reduction projection exposure apparatus.An object of the present invention is to provide a defect inspection apparatus that solves this problem.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の欠陥検査装置は、半導体基板上に種々の微細な
マスクパターンを転写して集積回路を作製する拡散工程
における前記半導体基板の構造上の欠陥の数及び大きさ
を検査する欠陥検査装置において、製造過程により形成
される各層のマスクパターンを記憶保持するメモリー部
と、前記マスクパターンを製造工程に従って重ね合せ、
各層の材質及び厚さから重ね合せたパターンを色分けし
てマスターイメージパターンを作製するシミュレータ部
と、このマスターイメージパターンと前記半導体基板よ
り得られる撮像パターンとを比較検査する比較検査部を
備えて構成される。
The defect inspection apparatus of the present invention is a defect inspection apparatus that inspects the number and size of structural defects of a semiconductor substrate in a diffusion process in which an integrated circuit is fabricated by transferring various fine mask patterns onto a semiconductor substrate. , a memory section that stores and holds the mask pattern of each layer formed in the manufacturing process, and the mask pattern is superimposed according to the manufacturing process,
Consisting of a simulator section that creates a master image pattern by color-coding superimposed patterns based on the material and thickness of each layer, and a comparison inspection section that compares and inspects this master image pattern with the imaged pattern obtained from the semiconductor substrate. be done.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の欠陥検査装置の一実施例における概略
を示す図である。この欠陥検査装置は、同図に示すよう
に、半導体基板に形成される形成層毎の複数のパターン
を格納するメモリー部5と、このメモリー部5のパター
ンを重ね合せて、マスターイメージパターンを作成する
シミュレーション部6と、半導体ベレット8のパターン
とマスターイメージパターンと比較検査する比較検査部
7とを設けたことである。それ以外のカメラ1、光学系
2及びステージ3は従来と同じである。
FIG. 1 is a diagram schematically showing an embodiment of the defect inspection apparatus of the present invention. As shown in the figure, this defect inspection device has a memory section 5 that stores a plurality of patterns for each layer formed on a semiconductor substrate, and creates a master image pattern by overlapping the patterns in this memory section 5. The present invention is provided with a simulation section 6 for performing a comparison inspection with the pattern of the semiconductor pellet 8 and a master image pattern. Other than that, the camera 1, optical system 2, and stage 3 are the same as before.

このような欠陥検査装置を用いて、例えば、ダイナミッ
クRAMのゲート・配線工程での欠陥検査を行うとすれ
ば、まずシミュレータ部で、フィールド形成からゲート
配線までの各層のマスクパターンデータを重ね合わせ、
これに各層の材質及び厚みから屈折率等を用いて色づけ
を行う。次に、このシミュレータ部6により生成された
マスイメージパターンをマスターパターンとして用い、
ステージ3に載置された半導体基板4上の半導体ベレッ
ト8を光学系2及びカメラ1により観察して得られたパ
ターン像との比較検査を比較検査部7を用いて行う。な
お、検査の手段としては両方の像を画素毎に信号化し、
それらの強度臼をとる方法が有効である。
For example, if such defect inspection equipment is used to inspect defects in the gate/wiring process of a dynamic RAM, first, in the simulator section, mask pattern data for each layer from field formation to gate wiring is superimposed,
This is then colored using the refractive index and the like based on the material and thickness of each layer. Next, using the mass image pattern generated by this simulator section 6 as a master pattern,
The semiconductor pellet 8 on the semiconductor substrate 4 placed on the stage 3 is observed by the optical system 2 and the camera 1, and a comparison inspection with a pattern image obtained is performed using the comparison inspection section 7. In addition, as a means of inspection, both images are converted into signals for each pixel,
The method of taking those strength mortar is effective.

一方、本実施例の装置で単層のマスクパターンの検査を
行うとしても可能である。すなわち、この場合は、まだ
半導体装置8のパターンを転写していない半導体基板4
にフォトレジストを塗布しこれをある工程のレチクルを
用いて露光、現像を行う。この半導体基板5を本発明の
装置で同一工程のパターン情報を用いて比較検査を行う
ことで、レチクル上の異物等による欠陥の有無を実際の
半導体基板を作業する前に確認することができる。
On the other hand, it is possible to inspect a single layer mask pattern using the apparatus of this embodiment. That is, in this case, the semiconductor substrate 4 on which the pattern of the semiconductor device 8 has not yet been transferred is
A photoresist is applied to the surface, which is exposed and developed using a reticle in a certain process. By performing a comparative inspection of this semiconductor substrate 5 using the apparatus of the present invention using pattern information from the same process, it is possible to check whether there are defects due to foreign matter on the reticle or the like before actually working on the semiconductor substrate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、各層におけるパターンを
重ね合せて、各層の材質及び厚みから色分けされるマス
ターイメージパターンを作成するシミュレータ部と、マ
スターイメージパターンで写し出されるペレットのパタ
ーンと比較検査する比較検査部を設けることによって、
露光装置の欠陥あるいはレチクルの欠陥の影響を受けず
に、半導体装置の欠陥を検査出来る欠陥検査装置が得ら
れるという効果がある。
As explained above, the present invention includes a simulator unit that superimposes patterns in each layer to create a master image pattern that is color-coded based on the material and thickness of each layer, and a comparison unit that performs comparative inspection with the pellet pattern projected by the master image pattern. By providing an inspection department,
This has the effect of providing a defect inspection apparatus that can inspect defects in semiconductor devices without being affected by defects in the exposure apparatus or defects in the reticle.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の欠陥検査装置の一実施例における概略
を示す図、第2図及び第3図は従来の欠陥検査装置の例
における概略を示す図である。 1・・・カメラ、2・・・光学系、3・・・ステージ、
4・・・半導体基板、5,9・・・メモリ部、6・・・
シミュレータ部、7,10・・・比較検査部、8・・・
半導体ベレット、11・・・データ拡納部、12・・・
積算メモリー部、13・・・検査部。
FIG. 1 is a diagram showing an outline of an embodiment of a defect inspection apparatus of the present invention, and FIGS. 2 and 3 are diagrams showing an outline of an example of a conventional defect inspection apparatus. 1...Camera, 2...Optical system, 3...Stage,
4... Semiconductor substrate, 5, 9... Memory section, 6...
Simulator section, 7, 10... Comparison inspection section, 8...
Semiconductor pellet, 11...Data expansion section, 12...
Integration memory section, 13...inspection section.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に種々の微細なマスクパターンを転写し
て集積回路を作製する拡散工程における前記半導体基板
の構造上の欠陥の数及び大きさを検査する欠陥検査装置
において、製造過程により形成される各層のマスクパタ
ーンを記憶保持するメモリー部と、前記マスクパターン
を製造工程に従って重ね合せ、各層の材質及び厚さから
重ね合せたパターンを色分けしてマスターイメージパタ
ーンを作製するシミュレータ部と、このマスターイメー
ジパターンと前記半導体基板より得られる撮像パターン
とを比較検査する比較検査部を備えることを特徴とする
欠陥検査装置。
In a defect inspection device that inspects the number and size of structural defects on a semiconductor substrate during a diffusion process in which various fine mask patterns are transferred onto a semiconductor substrate to fabricate an integrated circuit, each layer formed during the manufacturing process is used. a simulator section that creates a master image pattern by superimposing the mask patterns according to the manufacturing process and color-coding the superimposed patterns based on the material and thickness of each layer, and the master image pattern. A defect inspection apparatus comprising: a comparison inspection section that compares and inspects the imaged pattern obtained from the semiconductor substrate.
JP25058190A 1990-09-20 1990-09-20 Inspection device Pending JPH04129241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25058190A JPH04129241A (en) 1990-09-20 1990-09-20 Inspection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25058190A JPH04129241A (en) 1990-09-20 1990-09-20 Inspection device

Publications (1)

Publication Number Publication Date
JPH04129241A true JPH04129241A (en) 1992-04-30

Family

ID=17210021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25058190A Pending JPH04129241A (en) 1990-09-20 1990-09-20 Inspection device

Country Status (1)

Country Link
JP (1) JPH04129241A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008128866A (en) * 2006-11-22 2008-06-05 Olympus Corp Substrate inspecting device and substrate inspection method
US7616805B2 (en) 2003-11-28 2009-11-10 Hitachi High-Technologies Corporation Pattern defect inspection method and apparatus
CN103969853A (en) * 2013-02-05 2014-08-06 北京京东方光电科技有限公司 Array substrate, detecting method and detecting device of array substrate
JP2017162930A (en) * 2016-03-08 2017-09-14 東芝メモリ株式会社 Imprint method, imprint device and computer program for control thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7616805B2 (en) 2003-11-28 2009-11-10 Hitachi High-Technologies Corporation Pattern defect inspection method and apparatus
US7853068B2 (en) 2003-11-28 2010-12-14 Hitachi High-Technologies Corporation Pattern defect inspection method and apparatus
JP2008128866A (en) * 2006-11-22 2008-06-05 Olympus Corp Substrate inspecting device and substrate inspection method
CN103969853A (en) * 2013-02-05 2014-08-06 北京京东方光电科技有限公司 Array substrate, detecting method and detecting device of array substrate
JP2017162930A (en) * 2016-03-08 2017-09-14 東芝メモリ株式会社 Imprint method, imprint device and computer program for control thereof

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