JPH0412573A - Nonvolatile semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the gate length on a plane and facilitate miniaturization, by making all the gate insulating film exist in a trench part on the boundary region of a selective oxide film on the periphery, and preventing the gate insulating film from climbing onto the peripheral selective oxide film. CONSTITUTION:The gate part of an MNOS transistor 2 is formed in a trench 6 arranged on the surface of a substrate 1, and the gate part 11 of an MOS transistor 3, which does not contain a silicon nitride film 8 in the gate insulating film, is formed on the substrate 1 adjacent to the gate part. The gate part 11 of an MOS transistor 33 forming the peripheral circuit part is formed at the same time as the gate part 9 of the MOS transistor 2 formed to be adjacent to the gate part of the MNOS transistor 33. Finally a structure is constituted in the manner in which, in the boundary region where the gate part of the MNOS transistor 2 comes into contact with a selective oxide film 4 on the periphery, the gate insulating film 11 of the MNOS transistor 2 does not climb onto the selective oxide film 4 on the periphery. Thus the gate length bridges the bottom surface and both side surfaces of the trench part, the channel length is kept when the size on the plane is reduced, and miniaturization is advanced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor device having an electrically programmable and erasable nonvolatile semiconductor memory element, and a method for manufacturing the same.

Conventional technology Demand for semiconductor memory has increased rapidly in recent years, and non-volatile semiconductor memory devices, which can be electrically written and erased and retain their memory even when the power is turned off, are expected to be used in a variety of industrial fields. It is.

In particular, MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) type non-volatile semiconductor memory devices have excellent repeat write/erase times and are expected to be used in applications that require frequent rewriting of memory contents. .

The structure of a conventional MNOS type nonvolatile semiconductor memory device and its manufacturing method will be described below with reference to FIG.

As shown in FIG. 2(a), two mutually independent P well regions 2 and 3 are formed on an N type semiconductor substrate 1. Furthermore, an element isolation region made of a selective oxide film 4 is provided for element isolation. Next, as shown in FIG. 2(b), for example, at 900°C.
Oxidized for about 30 minutes in a pyrogenic atmosphere, resulting in about 600
A first gate oxide film 15 is formed. Then, for example, 6
A polycrystalline silicon film 16 of approximately 4000A is formed by thermally decomposing the silane gas at a temperature of 0.000C. After phosphorus addition (doping), only the gate portion of the peripheral transistor is formed on the P well region 3 using a photoresist 17 by ordinary lithography and etching techniques. Thereafter, the photoresist 17 is removed. Next, as shown in FIG. 2(C), oxidation is performed for about 10 minutes at 900°C in a pyrogenic atmosphere to oxidize the area around the polycrystalline silicon film at the gate of the peripheral transistor, and at the same time form an MNOS transistor. P well area 2
The upper substrate 1 is oxidized to form a protective oxide film 18 of approximately 350A. Subsequently, a silicon nitride film of about 1000 A is grown by a reaction of silane dichloride gas and ammonia gas at about 750° C. under a reduced pressure of, for example, 300 mTorr. Thereafter, using the photoresist 20, the silicon nitride film other than the region 19 forming the gate portion of the MNOS transistor is removed by ordinary lithography and etching techniques.

After that, the photoresist 20 is removed. Next, Figure 2 (
As shown in d), the second gate oxide film 2 of the thick film enhancement type transistor adjacent to the MNOS transistor is oxidized for about 20 minutes at 900° C. in a pyrogenic atmosphere, and has a current of about 1000 A including the protective oxide film 18.
form 1. Thereafter, the silicon nitride film 19 is removed using phosphoric acid, and the MN is removed using buffered hydrofluoric acid.
The oxide film is etched until the region where the OS gate portion is to be formed is etched off, thereby forming the substrate region 22.

Next, as shown in FIG. 2(e), oxidation is carried out at, for example, 600 DEG C. in a dry oxygen atmosphere for about 4 hours to form an extremely thin oxide film 23 of 20A to 25A. Then, for example, 300m
Dichloride silane gas and ammonia gas are reacted at a ratio of 1=30 at about 750°C under reduced pressure of Torr,
A silicon nitride film 24 of A is grown. Next, for example, 90
Oxidation is carried out at 0°C for about 30 minutes in a pyrogenic atmosphere, and the temperature is about 600 A on the substrate 1 and about 20 A on the silicon nitride film 24.
A top oxide film 25 is formed. Then, for example, 60
A polycrystalline silicon film 26 of about 4000 A is formed at 0° C. by thermal decomposition of silane gas. After phosphorus doping, only the gate portions of the MNOS transistor and the adjacent MOS transistor are formed on the P well region 2 by using a photoresist 27 and ordinary photolithography and etching techniques.

After that, the photoresist 27 is removed. Next, as shown in FIG.
MNO by implanting ×1015CI11-2 arsenic ions.
S) Form the source and drain regions 28 of the transistor and peripheral transistors to complete the transistor structure. To complete the product, an insulating film between the eyebrows, a contact window, and a protective film on the surface of the wiring 2 are further formed.

Problems to be Solved by the Invention Conventional structures and manufacturing methods have the following drawbacks.

First, in the conventional configuration, an MNOS (MNOS) transistor and an enhancement type transistor adjacent thereto are formed in parallel on a substrate, which increases the overall transistor length, making miniaturization difficult.

Second, enhancement-type transistors have a structure that includes a silicon nitride film in their gate insulating film, which causes charge trapping (carrier trapping) during repeated writing and erasing.
Therefore, there is a possibility that the threshold voltage of the enhancement transistor changes.

Third, since the MNOS transistor and the enhancement type transistor adjacent thereto are not formed at the same time as the peripheral transistors forming the peripheral circuit, the number of masking steps and etching steps increases. Therefore, process control becomes complicated, the number of factors decreasing yield increases, and costs increase.

Fourth, as shown in FIG. 3(b), the transistor width direction of the conventional MNOS transistor (cross-sectional view of FIG. 2 and 9
At both ends, the silicon nitride film 24 in the gate insulating film of the MNOS transistor rides on the peripheral selective oxide film 4, resulting in a sharp end of the selective oxide film 41, a so-called bird's beak ( bi
If there is an abnormality in the shape of the rd beak, the side walk described below will occur due to the memory characteristics.
The possibility of the phenomenon occurring increases.

The sidewalk phenomenon is a phenomenon in which the bird's beak part of the selective oxide film 4 shown in FIG. concentration impurity region) 29
Combined with the effect of , this means a phenomenon in which the transistor characteristics in this region exhibit enhancement type transistor characteristics with low channel conductance. When the sidewalk phenomenon occurs, the vG-
The characteristic 31 becomes a voile characteristic partially mixed with an enhancement type transistor characteristic 32 having a low channel conductance and a threshold voltage that does not change during writing, as shown in FIG. 4(b). If the read detection current after writing is set low because of this added enhancement type transistor characteristic 32,
If the writing is insufficient, it will be judged as a defective product, resulting in an extremely low yield. Note that 30 is Vo SrV'o in the erased state.
It is a characteristic.

Means for Solving Problems In order to solve the conventional drawbacks, the structure and manufacturing method of the present invention are as follows.

First, the gate portion of the MNOS transistor is formed in a groove provided on the surface of the substrate.

Second, a gate portion of a MOS transistor that does not include a silicon nitride film in the gate insulating film is formed on the substrate adjacent to the gate portion of the MNOS transistor provided in the trench.

Third, the gate portion of the MOS transistor forming the peripheral circuit is formed simultaneously with the gate portion of the MO8 transistor formed adjacent to the gate portion of the MNOS transistor.

Fourth, in the boundary region where the gate portion of the MNOS transistor provided in the trench comes into contact with the surrounding selective oxide film,
The structure is such that the gate insulating film of the MNOS transistor does not ride on the surrounding selective oxide film.

Effects The above structure and manufacturing method provide the effects described below.

First, when the gate portion of an MNOS transistor is formed in a trench, the gate length spans the bottom and both side surfaces of the trench, so even if the planar dimension (the width of the trench) is reduced, the channel length of the conventional level can be maintained and miniaturization is promoted.

Second, since a MOS transistor that does not include a silicon nitride film in the gate insulating film is formed on the substrate adjacent to the gate part of the MNOS transistor, charge trapping in the silicon nitride film due to repeated writing and erasing does not occur. ,
Therefore, fluctuations in the threshold voltage in this MOS transistor portion are prevented.

Third, the MO3 adjacent to the MNOS transistor
) Since transistors can be formed at the same time as MOS transistors that form the peripheral circuit, the number of masking steps and etching steps can be reduced compared to conventional manufacturing methods, simplifying the process and reducing costs. becomes.

Fourthly, since the gate insulating film of the MNOS transistor does not ride on the surrounding selective oxide film and does not overlap with the bird's beak portion, the sidewalk phenomenon is prevented from occurring.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

As shown in FIG. 1(a), two mutually independent P well regions 2 and 3 are formed on an N-type semiconductor substrate 1. As shown in FIG. Further, a selective oxide film 4 is used to provide an element isolation region. Next, as shown in FIG. 1(b), the MNOS transistor forming portion is opened by photolithography using a photoresist 5. Then, as shown in FIG.

For example, the opening width is 0.5 μm. Subsequently, by anisotropic dry etching using silane tetrachloride gas and chlorine gas under an output of 500 W and a pressure of 100 mTorr, for example, the substrate under the opening is dug to a depth of about 0.3 μm to 0.4 μm to form a groove 6. After that, the photoresist 5 is removed. Next, as shown in FIG. 1(C), using the same growth conditions and operating procedures as in the conventional method, an ultra-thin oxide film 7. Approximately 30
0A silicon nitride film8. and this silicon nitride film 8
A top oxide film 9 of approximately 20A is grown on top.

Furthermore, approximately 1.
Coat with a film thickness of 0 μm. Next, as shown in FIG. 1(d), the photoresist 10 is etched using a plasma etching method.
By combining etching conditions such that the selectivity ratio between the photoresist 10 and the oxide films 7 and 9 is 1, and etching conditions such that the selectivity ratio between the photoresist 10 and the silicon nitride film 8 is 1, the surface excluding the inside of the groove 6 is etched. Top oxide layer in area 9. The silicon nitride film 8° and the ultra-thin oxide film 7 are removed by etching back.

Next, as shown in FIG. 1(e), the MNOS is oxidized for about 30 minutes at 900°C in a pyrogenic atmosphere.
A gate oxide film 11 of about 600A for a MOS transistor is placed on the substrate 1 adjacent to the gate part of the transistor, and
A top oxide film 9 of approximately 20A is grown on each silicon nitride film 8 in the gate insulating film of the S transistor. At this time, the gate oxide film 11 of the transistor (MOS) of the peripheral circuit is also grown at the same time. Subsequently, the silane gas is thermally decomposed at, for example, 600° C. to grow a polycrystalline silicon film 12 of about 4000 A. After phosphorus doping, the MNOS transistor, the MOS transistor adjacent thereto, and all MOS transistors in the peripheral circuit are simultaneously patterned using the photoresist 13 by ordinary photolithography and etching techniques. After that, the photoresist 13 is removed. Next, as shown in FIG. 1(f), the source and drain regions 14 of all transistors are formed by arsenic ion implantation using the self-line method, just as in the conventional method, to complete the transistor structure. After that, the product is completed through the same process as the conventional method.

In the description of this embodiment, P-channel type MO of the peripheral circuit
Although no particular mention was made of the method for manufacturing the S transistor, the gate portion may be formed at the same time as the N-channel MOS transistor and the MNOS transistor. Although a polycrystalline silicon film is used as the gate electrode, it is also possible to use an aluminum electrode or even a high melting point electrode such as tungsten silicide.

Next, cross-sectional views in the transistor radiation direction of an MNOS transistor formed by the manufacturing method of the present invention and an MNOS transistor formed by the conventional method are shown in FIGS. 3(a) and 3(b), respectively. (This figure shows a cross-sectional view of the figure rotated by 90 degrees.) In the conventional method, the third
As shown in Figure (b), the silicon nitride film 24 in the gate insulating film rides on the peripheral selective oxide film 4 and exists so as to cover the bird's beak and the channel stopper region 29 therebelow, so that the sidewalk phenomenon occurs. The structure is such that it is easy for this to occur. On the other hand, in the configuration of the present invention, as shown in FIG.
As shown in a), the gate insulating film is connected to the surrounding selective oxide film 4.
Since all of the boundary region between the oxide layer and the oxide layer exists within the groove, it does not run onto the peripheral selective oxide film 4, and there is no interaction with the channel stopper region 29 under the bird's beak, resulting in a structure that can prevent the sidewalk phenomenon.

Effects of the Invention As described above, the present invention relates to an MNOS type nonvolatile semiconductor memory device, and firstly, by forming the gate portion of the MNOS transistor within the trench, the planar gate length can be shortened. Miniaturization is promoted.

Second, since the gate insulating film of the MOS transistor formed adjacent to the MNOS transistor does not include a silicon nitride film, fluctuations in the threshold voltage of this portion can be prevented.

Thirdly, the MOS transistor adjacent to the MNOS transistor can be formed at the same time as the MOS transistor in the peripheral circuit, and the number of circuits in the masking process and etching process can be reduced, which simplifies the process.

Cost reduction can be achieved.

Fourthly, since the gate insulating film of the MNOS transistor does not ride on the surrounding selective oxide film and does not overlap with the bird's beak, the sidewalk phenomenon can be prevented.

This makes it possible to realize a nonvolatile semiconductor memory device having excellent characteristics as described above.

[Brief explanation of drawings]

FIGS. 1(a) to (f) show M in an embodiment of the present invention.
2(a) to 2(f) are process sectional views of the method for manufacturing an NOS type nonvolatile semiconductor memory device, and FIGS. 3(a) and (b) are process sectional views of the manufacturing method of the present invention, respectively. Cross-sectional views in the transistor width direction of MNOS type nonvolatile semiconductor memory devices according to the method and the conventional method, FIGS. 4(a) and 4(b)
) are memory characteristic diagrams showing the normal a-E7 characteristic and the vo-4T characteristic when the sidewalk phenomenon occurs in the write/erase state of the MNOS transistor. 1...N-type semiconductor substrate, 2...P well region (MNOS transistor formation), 3...
P-well region (peripheral MO8 transistor formation), 4...
...Selective oxide film (element isolation region), 5...
Photoresist, 6...Groove, 7...
Ultra-thin oxide film, 8...Silicon nitride film, 9...
... Top oxide film, 10 ... Photoresist, 11 ... Gate oxide film, 12 ... Polycrystalline silicon film, 13 ... Photoresist, 1
4... Source region and drain region, 29.
...Channel stopper region (P-type cavity concentration impurity region). Figure 1 Figure 1 Figure 1

Claims (2)

[Claims] (1) a semiconductor substrate of one conductivity type, a source region of a conductivity type opposite to the one conductivity type, which is provided inside the semiconductor substrate in contact with one main surface of the semiconductor substrate and spaced apart from each other by a certain distance; a drain region, a gate insulating film provided on the surface of the semiconductor substrate between the source region and the drain region, and a polycrystalline silicon gate provided on the gate insulating film, the gate insulating film is composed of three layers consisting of an oxide film, a silicon nitride film, and an oxide film in order from the surface side of the semiconductor substrate, and the silicon nitride film is located closer to the inside of the semiconductor substrate than the surface of the source and drain regions. Characteristic non-volatile semiconductor memory device. (2) forming a well region on the surface of the semiconductor substrate; forming a groove in the well region by selective etching; sequentially forming a first oxide film, a silicon nitride film, and a second oxide film in the groove; forming a gate of a polycrystalline silicon film on the second oxide film; and forming a source region and a drain region of a conductivity type opposite to that of the well in the well on both sides of the gate. A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a nonvolatile semiconductor memory device.