JPH04117169A - Switching power supply - Google Patents

Abstract

PURPOSE:To reduce loss in the secondary rectifying circuit of a DC/DC converter by an arrangement wherein a FET driving circuit controls the ON/OFF timing of a FET, based on outputs from a main transformer and a feedback control circuit, such that the loss of a diode is reduced. CONSTITUTION:Gate voltage of FET Q5 is sustained at High level by a driving signal fed from a FET driving circuit 3 during an interval from falling time point of the output from a main transformer TR to a rising time point of an output from a feedback control circuit 2. Q5 and a diode D2 are connected in parallel and when Q5 is turned ON, current flows on the Q% side whereas current flows only during short intervals tau3, tau4 into the diode D2. The time lags tau3, tau4 can be set so short as negligible when compared with ON/OFF period of switching element. Consequently, loss in a rectifying diode can be reduced.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a switching power supply device configured using a DC/DC converter, and more specifically, to a switching power supply device configured using a DC/DC converter.
The present invention relates to a switching power supply device that can reduce loss in a secondary rectifier circuit of a C converter.

<Prior Art> FIG. 4 is a block diagram showing an example of a conventional switching power supply of this type. This device was published in the Technical Research Report of the Institute of Electronics, Information and Communication Engineers, Vo 1゜88 No. 30.
6 Published on November 30, 1988.

In the figure, TR is a main transformer, a switching element Qo is turned on/off by a pulse width signal from a pulse width modulation circuit (not shown), and a DC/DC converter is driven.

MOSFET Q with low on-resistance and no offset voltage is used as the secondary rectifier circuit of the DC/DC converter.
A synchronous rectifier circuit consisting of Q2 and Q2 is used.

Here, Ql is turned on/off by the voltage generated in the transformer TR. A diode D is connected in series to the gate of Q2, and it is turned on by the voltage generated in the transformer, and even after the magnetic flux of the lance is set,
The gate voltage is held by the input capacitance of Q2.

An auxiliary switch Q3 is connected to the gate of Q2, and is configured to turn off Q2 by turning on the switch Q3 immediately before the main switching element Qo turns on.

According to the device configured in this manner, the FET synchronous rectifier circuit can be driven in a state close to the ideal, so that efficiency can be improved.

<Problem to be solved by the invention> However, in these conventional devices, ■, FE
The switching element is large due to the long reverse recovery time of the FET on the forward side 5. Design of the drive circuit to reduce the period during which the FETs on the flywheel side are simultaneously on and off as much as possible. There were some problems, such as difficulty.

The present invention has been made in view of these points, and it is an object of the present invention to provide an efficient switching power supply device that reduces the loss of the secondary side rectifier circuit of a DC/DC converter with an easy-to-design configuration. purpose.

<Means for Solving the Problems> FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 1 is a DC/DC converter, which has a main transformer TR and a DC voltage E1 on the primary side of this main transformer.
a switching element Qo that turns on and off the output, a diode DI that rectifies the secondary output of the main transformer TR,
It has D2.

Q5 is a FET connected in parallel to the secondary side rectifier diode D2, and 2 is an FET that turns on/off the switching element QO so that the DC output voltage EO of the DC/DC converter 1 is constant.
Feedback control circuit that controls off, 3 is main transformer TR
The output of FETQ5 and the output of feedback control circuit 2 are manually connected.
This is an FET drive circuit that generates a drive signal.

Function> The DC/DC converter 1 is driven by turning on/off the switching element Qo, and rectifies and smoothes the secondary output of the main transformer TR to obtain a DC output voltage EO.

Feedback control circuit 2 controls the on/off duty ratio of switching element Qo so that DC output voltage Eo is maintained at a constant value.

The FET drive circuit 3 controls the on/off timing of the FET using the output of the main transformer TR and the output of the feedback control circuit so as to reduce the loss of the diode.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals.

In the DC/DC converter 1, the main transformer TR
The rectifier circuit for the secondary output is composed of diodes DI and D2, has an inductance, is smoothed by a capacitor C2, and a DC output voltage Eo is obtained across the capacitor C2.

The feedback control circuit 2 generates a voltage e corresponding to the DC output voltage Eo.
an error amplifier 21 that amplifies the difference between o and reference voltage ES;
The pulse width modulation circuit 22 outputs a pulse width signal whose duty ratio changes according to the output of the error amplifier 21, and the pulse width signal from this circuit passes through the signal isolation transformer TR2 and the switching element. Qo is applied.

The FET drive circuit 3 includes a resistor R and a Zener diode Dz for taking out the output of the main transformer TR.

It consists of an inverter 31, an inverter 32 that takes out the output from the feedback control circuit 2 (pulse width modulation circuit 22), and an antgelt 33 that takes the AND of the output from each inverter, so that the signal from the AND gate is applied to the FETQ5. It is composed of

The operation of the device configured as described above will be explained as follows.

FIG. 3 is a time chart showing the operation.

The feedback control circuit 2 outputs a pulse width signal as shown in (a) to the switching element QO in accordance with the magnitude of the overnight DC output voltage Eo of the DC/DC converter. The switching element QO receives this pulse width signal and turns on/off.
As shown in (b), the voltage Vcl between its drain and source
s or change. Here, τ1 is the signal isolation transformer TR
The delay time is the sum of the delay time of the drive circuit including the leakage inductance of 2 and the rise time of Qo.

In the main transformer TR, a DC voltage is applied to the primary winding n1 in response to on/off of the switching element QO,
An output as shown in (c) is generated in the secondary winding n2.

Here, τ2 is the delay time due to the leakage inductance of the main transformer TR, and rl+r2 is approximately to On
It is S.

The output shown in (C) obtained at the secondary winding of the main transformer TR flows through the diode D1 for the period I shown in (d), and flows through the diodes D2 and Q5 for the period I shown in (e). flows.

Here, the gate voltage of FET Q5 is determined by the drive signal from the FET drive circuit 3, as shown in (f), from the fall of the output of the main transformer TR to the rise of the output from the feedback control circuit 2. It has been at a high level up to this point.

Q5 and diode D2 are connected in parallel with each other, and when Q5 is turned on by applying the gate voltage shown in (f), current flows to the Q5 side, and diode D
2, there is a short period τ3.2 shown in (g). τ4 flows.

Here, τ3 is the fall time of τ1 + τ2 + τ5 + Q5 (τ5 is from the rise of the output of the feedback control circuit,
(delay time until the output of the drive circuit 3 falls). In addition, τ4 is the rise time of Q5 + τ6 (τ6 is from the fall of the output of the main transformer TR to the drive circuit 3
This is the delay time until the output rises.

These delay times τ3. τ4 can be made so small that it can be ignored compared to the on/off period of the switching element.

In the device of the invention, τ3−τ4−0. Forward voltage VF-0.5V of diodes DI and D2.

The on-resistance of FET Q5 is set to 10 mΩ, which is so small that the switching loss of Q5 is ignored (because switching is performed with the drain and source voltage Vds equal to the forward voltage VF of diode D2), and the duty ratio in steady state is 1/3 and the output current is, for example, 18A, each period! , II losses with and without FET Q5 are shown in the table below.

Therefore, by applying the present invention, it is possible to reduce the loss by 40% or more.

In the above embodiment, the FET is connected in parallel to the diode D2, or the FET is connected in parallel to the diode D1, and the output of the main transformer TR is at a high level, and the feedback control circuit The loss of the diode D1 can be similarly reduced by setting the gate voltage to a high level and driving this FET when the output of the FET is at a high level.

<Effects of the Invention> As explained in detail above, according to the present invention, the FET on/off timing settings can be arbitrarily selected by paying attention only to the loss, so the FET drive circuit can be easily constructed. , the degree of freedom in design can be increased. Further, the loss in the rectifier diode and the loss in the FET can be reduced, and a switching power supply with good efficiency as a whole can be provided.

[Brief explanation of drawings]

Fig. 1 is a professional diagram showing the basic configuration of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a time chart showing the operation, and Fig. 4 is a conventional switching power supply. FIG. 1 is a configuration block diagram showing an example of a device. 1... DC/DC converter TR... Main transformer QO... Switching element DI D2... Manufactured diode Q5... FET 2... Feedback control 1 circuit 3... FET drive circuit Fig. Q) Current of D2”■■■■■L

Claims (1)

[Claims] A main transformer, a switching element that turns on and off a DC voltage to the primary side of the main transformer, and a DC that has a diode that rectifies the secondary side output of the main transformer.
/ A switching power supply device including a DC converter, comprising: an FET connected in parallel with the secondary side rectifier diode, and a control circuit that controls on/off of the switching element so that the DC output voltage of the DC/DC converter is constant. and an FET drive circuit that receives the output of the main transformer and the output of the control circuit and generates a drive signal for the FET.