JPH04116688A - Gradation driving light valve device on frame thinning - Google Patents

Abstract

PURPOSE:To raise the frame frequency to display the gradation on the frame thinning system by constituting a switch element, which drives a picture element electrode group, of an insulated gate field-effect transistor of high responsiveness formed in a silicon single crystal thin film layer. CONSTITUTION:A composite substrate consisting of an electrically insulating carrier layer 6 and a semiconductor single crystal thin film layer 7 is used in a thin film type active matrix device. Picture element arrays 4, 5, 9, 11, and 12 are integratedly formed in the semiconductor single crystal thin film layer 7 by LSI technique. Thus, the switch element group very superior in quick responsiveness is obtained by using the composite substrate where the semiconductor single crystal thin film layer 7 is formed in this manner, and the frame frequency is raised from one digit to two digits, and gradation display on the frame thinning system is realized in the practical level.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention comprises a liquid crystal panel assembled using an integrated circuit board on which a pixel array consisting of a pixel electrode group, a switch element group, etc. is formed on a semiconductor thin film. The present invention relates to light valve devices, such as thin film active matrix devices. More specifically, the present invention relates to a gradation driving method for this type of active matrix device.

[Conventional technology]

Active matrix devices have a relatively simple structure. A switch element is provided in each pixel, and when a specific pixel is selected, the corresponding switch element is made conductive. When not selected, the switch element is kept in a non-conductive state. In thin film active matrix devices, this switching element usually consists of a thin film transistor.

That is, a group of switch elements is integrally formed on a semiconductor thin film coated on the surface of a glass substrate constituting a liquid crystal panel.

Conventionally, in thin film active matrix devices,
Thin film transistors have been formed on the surface of amorphous silicon thin films or polycrystalline silicon thin films deposited on glass substrates. Amorphous silicon thin films can be easily deposited on glass substrates, for example, by vacuum evaporation or sputtering. Also, polycrystalline silicon thin films can be easily deposited on glass substrates using, for example, chemical vapor deposition.

Thin film transistors formed in amorphous or polycrystalline silicon thin films are generally of the insulated gate field effect type.

[Invention or problem to be solved]

Incidentally, gradation driving has been conventionally performed in order to obtain high-quality image display with excellent fidelity. This gradation drive is
It is possible to display halftones of each pixel in two positions of the active matrix, and it is possible to impart shading to the image as a whole. In conventional gradation driving, an analog image signal is used, a voltage corresponding to the gradation level is written to each pixel, and the written voltage is held during one frame period to perform halftone display. Gradation control using voltage levels has the advantage that high-speed responsiveness of the switch element group is not required, and because analog image signals are used, continuous gradation is possible in principle. However, as long as analog image signals are used, there is a limit to how high the frame frequency can be increased, and there is a problem in that it is difficult to support non-inklace displays and HDTVs used in office automation equipment.

Incidentally, a "frame thinning" method has been proposed as a method for performing gradation control without using analog image signals. This method takes several frames, that is, several views as one unit, and distributes the ratio of black display and white display, which are binary displays, to each pixel in time series within this one unit. It performs gradation display. For example, if you focus on a certain pixel with four frames as one unit, the first frame displays black, the second frame displays white, and the third
If a black display is performed in one frame and a white display is performed in the fourth frame, a gray intermediate tone can be expressed when viewed as an average of one unit, that is, four frames.

Generally, if n frames are taken as one unit, n+1 gradation levels are obtained. By the way, if you increase the number of frames per unit while keeping the frame frequency fixed, 1
The frequency per unit decreases, causing screen flickering. Therefore, in order to prevent flicker, it is necessary to increase the frame frequency. For this reason, high-speed response of the switch element group that drives each pixel is required. However, there is a problem in that the switching elements used in conventional thin-film active matrix devices cannot satisfy the high-speed response required for the frame thinning gradation method. For example, when an amorphous silicon thin film is used as a material for a thin film transistor, field effect electron mobility is relatively small due to dangling bonds at silicon grain boundaries.

Its mobility value is approximately 1 cd/V see. Therefore, it is impossible to form an insulated gate field effect transistor that can operate at high speed. Furthermore, even when a polycrystalline silicon thin film is used, the field effect electron mobility is relatively small due to its polycrystalline nature, 20 cd/V S
It is about ee.

[Means to solve the problem]

In view of the above-mentioned problems of the conventional technology, an object of the present invention is to provide a thin film type active matrix device in which a group of switching elements is formed and has a high-speed response that enables gradation driving by frame thinning.

To achieve this objective, the thin film active matrix device of the present invention utilizes a composite substrate consisting of an electrically insulating carrier layer and a semiconductor single crystal thin film layer. A pixel array is integrally formed on this semiconductor single crystal thin film layer using LSI technology. That is, the pixel array includes a plurality of pixel electrodes defining pixels and a plurality of switch elements for supplying power to the corresponding pixel electrodes. This switch element consists of an insulated gate field effect transistor formed in a semiconductor single crystal thin film layer. A counter substrate is arranged to face the composite substrate with a predetermined gap therebetween.

This gap is filled with an electro-optic material layer, such as a liquid crystal layer, and electro-optic gradation display is performed for each pixel according to the amount of power supplied to each pixel electrode. Furthermore, this active matrix device includes a frame thinning gradation drive circuit, which drives a plurality of switch elements by frame thinning and controls the amount of power supplied to the corresponding pixel electrode.

Preferably, the composite substrate has a silicon monocrystalline thin film layer adhered to a carrier layer and polished thin. For example, a quartz glass substrate is used as a carrier layer, and high quality silicon single crystal urethane is adhered to the surface of the substrate. By polishing this silicon single crystal wafer into a thin film, a high quality silicon single crystal thin film layer can be obtained. LSI manufacturing technology can be directly applied to this thin film layer, and an extremely high-speed insulated gate field effect transistor can be formed.

[Action of the invention]

In the above-described configuration, since a composite substrate on which a semiconductor single-crystal thin film layer is formed is used, it is possible to realize a switch element group with extremely excellent high-speed response.

That is, for example, a silicon single crystal thin film has a field effect electron mobility value of approximately 400 cj/Vsee, which is two orders of magnitude higher than that of an amorphous silicon thin film and one order of magnitude higher than a silicon polycrystalline thin film. In proportion to this, a transistor formed in a silicon single crystal thin film has a high-speed response that is one or two orders of magnitude faster than the conventional transistor. Therefore, the frame frequency can be increased by one to two orders of magnitude, and it becomes possible to realize gradation display using the frame thinning method at a practical level.

〔Example〕

Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic exploded perspective view showing an embodiment of the frame thinning gradation driving light valve device according to the present invention. As shown in the figure, this light valve device includes a composite substrate 1 and a composite substrate 1.
The composite substrate 1 and the counter substrate 2 are arranged to face each other, and an electro-optic material layer such as a twisted nematic liquid crystal layer 3 is arranged between the composite substrate 1 and the counter substrate 2.

On the surface of the composite substrate 1 are a plurality of pixel electrodes 4 defining pixels arranged in a matrix, and a plurality of switch elements 5 for selectively supplying power to the pixel electrodes 4 according to a predetermined signal.
is formed. These pixel electrode groups and switch element groups constitute a pixel array.

The composite substrate 1 has a two-layer structure consisting of a carrier layer 6 made of quartz glass and a single crystal silicon thin film layer 7. In addition, a polarizing plate 8 is adhered to the back side of the quartz glass carrier layer 6. The aforementioned pixel array is integrally formed on this single crystal silicon thin film layer 7. The switch element 5 included in this pixel array is composed of an insulated gate field effect transistor. The source electrode of the transistor is connected to the corresponding pixel electrode 4, the gate electrode is similarly connected to the scanning line 9, and the drain electrode is similarly connected to the signal line 10. An X driver 11 is formed around the pixel array, and is connected to column-shaped signal lines 10. Furthermore, an X driver 12 is also formed and connected to the row scanning lines 9. In addition, a frame thinning gradation control circuit 13 is connected to the X driver 11 and the X driver 12. This control circuit 13 drives the plurality of switch elements 5 via the X driver 11 and the X driver 12, controls the amount of power supplied to the corresponding pixel electrode 4, and executes frame thinning gradation. These control circuit 13, X driver 11, and X driver 12 constitute a frame thinning gradation drive circuit, and in this embodiment, they are integrally formed in the single crystal silicon thin film layer 7 together with the pixel array. Therefore, this drive circuit can also be constructed using a silicon single crystal thin film insulated gate field effect transistor which has excellent high-speed response. In particular, by using a high-quality single-crystal silicon thin film layer, it is possible to directly apply VLSI technology, and high-density integration of these peripheral circuits can be realized. However, the present invention is not limited to this embodiment, and the frame thinning gradation control circuit 13
Of course, the external parts may be constructed from parts.

On the other hand, the counter substrate 2 is composed of a glass carrier 14, a polarizing plate 5 bonded to the outer surface of the glass carrier 14, and a common electrode 1B formed on the inner surface of the glass carrier 14.

Further, the surface of the common electrode 1B is covered with a uniaxial alignment film 17. Further, the inner surface of the composite substrate 1 is also covered with a uniaxial alignment film 18. The alignment directions of the pair of alignment films 17 and 18 are perpendicular to each other, and they are in surface contact with the upper and lower surfaces of the liquid crystal layer 3. As a result, the nematic liquid crystal layer 3 has a so-called 90"
are aligned in a twisted orientation state.

2(A) and 2(B) are schematic perspective views showing one pixel cut out of the light valve device shown in FIG. 1, and FIG. 2(A) shows the pixel at the lowest gray level. indicates a certain state, and the second
Figure (B) shows a state where the pixel is at the highest gradation level. In this example, the lowest gradation level is displayed by supplying a constant voltage below the threshold voltage of the liquid crystal to the pixel electrode, and the highest gradation level is displayed by applying a constant voltage above the threshold voltage of the liquid crystal to the pixel electrode. has been realized. Therefore, the state shown in FIG. 2(A) is considered to be substantially no voltage applied state. As shown in the figure, the nematic liquid crystal molecules 19 have the property that their long axes are easily oriented. The alignment of the liquid crystal molecules is controlled by a pair of alignment films 17 and 18 formed on the inner surfaces of the composite substrate 1 and the counter substrate 2, as described above. These alignment films 17 and 18 are obtained, for example, by rubbing the inner surface of each substrate. As mentioned above, since the rubbing direction differs by 90° between the upper and lower substrates, the liquid crystal molecule I9 also follows the rubbing direction by 90°.
Rotate.

As a result, the polarization axis of the light passing through the liquid crystal layer is rotated by 90''. However, as shown in the figure, a pair of polarizing plates 8
Since the polarization axes of and 15 coincide with each other, the incident light cannot pass through the pixel. As a result, the pixel displays complete black at the lowest gradation level.

On the other hand, in the state shown in FIG. 2(B), a voltage higher than the threshold of the liquid crystal is applied between the pixel electrode arranged on the inner surface of the composite substrate 1 and the common electrode arranged on the inner surface of the counter substrate 2. is being applied, the liquid crystal molecules 19 rise in the direction of voltage application, that is, in the direction perpendicular to the substrate, and lose their optical rotation. As a result, the linearly polarized incident light passes through the pixel as it is. That is, at the highest gradation level, the pixel displays complete white.

FIG. 3 is a graph showing the relationship between the voltage applied to the nematic liquid crystal constituting the pixels shown in FIGS. 2(A) and 2(B) and the transmittance of the nematic liquid crystal.

As shown in the figure, by applying a constant voltage equal to or higher than the threshold between the common electrode and the pixel electrode, the transmittance of the liquid crystal layer becomes substantially 100%, and the highest gray level can be obtained. or,
By applying a constant voltage below the threshold between the two electrodes, the transmittance of the liquid crystal layer becomes substantially 0% and the lowest gradation level can be obtained. By the way, the threshold value of the liquid crystal layer has a certain range, and in the example shown in FIG. 3, it rises between 3V and 5V. Therefore, by applying a voltage between 3V and 5V between the common electrode and the pixel electrode, an intermediate level of transmittance can be obtained. Therefore, halftones can be displayed.

In other words, a gradation display can be obtained by setting the voltage level applied to the liquid crystal in several levels.

In this embodiment, the effective level of the voltage applied to the liquid crystal is controlled by a frame thinning method.

Next, the operation of the above embodiment will be explained in detail with reference to FIGS. 1 to 3. The gate electrodes of the transistors constituting each switching element 5 are connected to a scanning line 9, and a scanning signal is applied by a Y driver 12 to control conduction and cutoff of each switching element 5 line sequentially. This line sequential scanning is repeated for each frame. The binary bit signal output from the X driver 11 is connected to the signal line 1.
o is applied to the selected switch element 5 which is in a conductive state. The applied binary bit signal is transmitted to the corresponding pixel electrode 4, and the value of the binary bit, ie O
A predetermined amount of electricity is supplied to the pixel electrode according to whether on the other hand,
When not selected, the switch element 5 becomes non-conductive and the amount of electricity supplied to the pixel electrode is maintained. The line sequential scanning described above can be repeated over several frames. The amount of electricity supplied in accordance with the numerical value of the binary bit for each frame is accumulated in each pixel electrode for several frames. The effective level of the voltage applied to the liquid crystal is set according to the accumulated amount, and a predetermined halftone is displayed. That is, when focusing on one pixel, if binary bit data 1 is always given over several frames, the highest gradation level will be displayed, and conversely, if all binary bit data 0 is given, the lowest gradation level will be displayed. The level will be displayed.

Furthermore, predetermined halftones are displayed depending on the combination of binary bit data values.

The on/off current ratio is used to express the switching performance of the transistor that constitutes the switching element. The current ratio required for liquid crystal operation can be easily determined from the write time and retention time. When the image signal is, for example, a television signal, one frame period is approximately 16 seconds, and one scanning period is approximately 80 μsec. When displaying, for example, five gradations using the frame thinning method, the frame frequency must be quadrupled. Therefore, when performing frame thinning gradation based on a television signal, one frame period must be set to 4 See and one scanning period must be set to 15 μ See (1° This shortened one scan period of 15 μ seconds (during this period), an invalid bit signal must be written. On the other hand, the written charge amount must be substantially retained during the shortened one-frame period 4s. The charge mobility is extremely high (since it is formed on a silicon single crystal thin film, an on/off ratio of more than 6 digits can be ensured. Therefore, it is possible to realize the frame thinning method at a practical level. At the same time, By utilizing the high mobility characteristics of silicon single crystal thin films, peripheral circuits such as driver circuits can be integrated at high density on the same silicon single crystal thin film.

Next, a method for manufacturing a substrate for a light valve device in which a pixel array consisting of a pixel electrode group and a switch element group is integrated will be described in detail with reference to FIGS. 4(^) to I(). First of all, the fourth
In the step shown in Figure (A), a quartz glass substrate 21 and a single crystal silicon substrate 22 are prepared. It is preferable to use a high quality silicon wafer used for LSI manufacturing as the single crystal silicon substrate 22, and its crystal orientation is < ioo
>o, o±1.0, and the single crystal lattice defect density is 500 defects/C- or less. Surface of prepared quartz glass substrate 21 and single crystal silicon substrate 2
First, the surface of 2 is precisely smoothed. Subsequently, the side substrates are thermocompression bonded by overlapping and heating the smoothed surfaces. By this thermocompression bonding process, the side substrates 2I and 2
2 are firmly fixed to each other.

In the step shown in FIG. 4(B), the surface of the single crystal silicon substrate 22 is polished. As a result, the quartz glass substrate 21
A monocrystalline silicon thin film layer 23 is formed on the surface of the substrate to a desired thickness, for example, to the bottom.

Accordingly, a composite substrate having a two-layer structure consisting of a carrier layer made of a quartz glass substrate and a monocrystalline silicon thin film layer is obtained. Note that in order to thin the single crystal silicon substrate 22, etching treatment may be performed instead of polishing treatment. Since the quality of the silicon wafer 122 is substantially preserved in the monocrystalline silicon thin film layer 23 obtained in this way, it is possible to obtain a thin film substrate material with extremely excellent crystal orientation uniformity and lattice defect density. can.

By the way, various types of thin film substrates having a two-layer structure consisting of a silicon single crystal thin film layer and an electrically insulating carrier layer are conventionally known. This is what is called a So1 substrate. For example, a Sol substrate is made by depositing a thin polycrystalline silicon film on the surface of a carrier made of an insulating material using a chemical vapor deposition method, etc., and then applying heat treatment such as laser beam irradiation to recrystallize the polycrystalline film to form a single crystal. It was obtained by converting the structure. However, in general, single crystals obtained by recrystallization of polycrystals do not necessarily have --like crystal orientation and have a large lattice defect density. For these reasons, it is difficult to apply LSI manufacturing technology to the conventional So1 substrate in the same way as to silicon single crystal wafers.

Next, in a step shown in FIG. 4C, the surface of the single crystal silicon thin film layer 23 is thermally oxidized to form a silicon oxide film 24 on the entire surface. A silicon nitride film 25 is deposited thereon using chemical vapor deposition. Furthermore, a resist 2B is coated. This resist 26 is patterned by photolithography and etching and removed leaving only the element region 27. In this state, an anisotropic etching process is performed to remove the silicon oxide film 24 and silicon nitride film 25 in the portions not covered by the resist 2B. Figure 4 (
C) shows the state of the semi-finished product obtained in this way.

Subsequently, in the step shown in FIG. 4(D), resist 2B is
After removing the silicon oxide film 2 covering the element region 27
4 and the silicon nitride film 25 as a mask, the single crystal silicon thin film layer 23 is thermally oxidized to form the field oxide film 2.
form 8. Single crystal silicon thin film layer 23 is left in device region 27 surrounded by field oxide film 28. Note that in the illustrated state, the silicon oxide film 24 and silicon nitride film 25 used as a mask have been removed.

Further, in the step shown in FIG. 4E, thermal oxidation treatment is performed again to form a gate oxide film 29 on the surface of the single crystal silicon thin film layer 23.

In the step shown in FIG. 4(F), a polycrystalline silicon film is deposited by chemical vapor deposition. This polycrystalline silicon film is selectively etched using a resist 30 patterned into a predetermined shape, and a gate electrode 31 made of a polycrystalline silicon film is formed on the gate oxide film 29.

Subsequently, in the step shown in FIG. 4(G), after removing the resist 30, impurity arsenic ions are implanted through the gate oxide film 29 using the gate electrode 31 as a mask to form a drain region in the silicon single crystal thin film layer 23. 32 and source region 33 are formed. As a result, a channel region 34 into which impurity arsenic is not implanted is provided between the drain region 32 and the source region 33 below the gate electrode 31.

Finally, in the step shown in FIG. 4(H), a part of the gate oxide film 29 above the drain region 32 is removed to form a contact hole, to which the drain electrode 3B is connected. Similarly, a part of the gate oxide film 29 above the source region 33 is removed to form a contact hole, and a pixel electrode 35 is formed to cover this part. Pixel electrode 3
Reference numeral 5 is made of a transparent electrode material such as ITO. In addition, the field oxide film 2 below the pixel electrode 35
8 is also transparent, and the quartz glass substrate 21 disposed below it is also transparent. Therefore, the pixel electrode 35,
The three-layer structure consisting of the field oxide film 2B and two quartz glass substrates is optically transparent, and a transmission type light valve device can be obtained.

As described above, according to the manufacturing method shown in FIGS. 4(A) to 4(H), a high-quality single-crystal silicon thin film is subjected to a film-forming process using high temperature, high-resolution photolithography etching, and ion implantation process. By performing the above steps, it is possible to form an insulated gate field effect transistor having a size on the micron order or submicron order and having extremely excellent high-speed response. This transistor is used as a switch element to selectively supply power to the corresponding pixel electrode. In addition, in the process shown in FIG. 4 (^) or I+), only the manufacturing method of the pixel electrode and the switch element is shown, but the frame thinning gradation control circuit is also made of monocrystalline silicon around the pixel array. It is possible to simultaneously form a thin film. This is because the frame thinning gradation control circuit can also be constructed from insulated gate field effect transistors like the switch elements.

Next, the configuration of the frame thinning gradation control circuit will be explained in detail with reference to FIG. As shown in the figure, this control circuit has a frame memory 5. This memory 51 has addresses arranged in a matrix, and each address corresponds to an individual pixel arranged in the matrix. The frame memory 51 stores image data VD and holds pixel gradation data GD for each address. In this example, the gradation data C and D are divided into five levels, and are expressed as CD to CD5 from the lowest level to the highest level.

A decoder 52 is also connected to the frame memory 51. This decoder 52 has a function of converting the gradation data GDI to GD5 into binary data consisting of 4 bits according to the level. For example, the lowest level gradation data CDI is converted into four O-bit data. The second level gradation data GD2 consists of three O-bit data and one 1
Converted to a set of bit data. The third level gradation data GD3 is converted into a set of two 0-bit data and two 1-bit data. The fourth level gradation data GD4 is converted into a set of one 0 bit data and three 1 bit data. The highest level gradation data GD5 is converted into four 1-bit data. The decoder 52 has a distributor 53
is connected.

Further, four subframe memories 54 to 57 are connected to the distributor 53. Each subframe memory has a frame memory 51 and a corresponding matrix address. The four subframe memories 54 to 57 correspond to four bit data components constituting one gradation data. The distributor 53 distributes the first bit data component to the first subframe memory 54, the second bit data component to the second subframe memory 55, and the third bit data component to the third subframe memory. 56, and the fourth bit data component is distributed to the fourth subframe memory 57. Each distributed bit data component is stored at an address corresponding to the original gradation data.

A memory selector 58 is connected to the four subframe memories 54 to 57. This memory selector 58
A controller 64 is connected to. The memory selector 58 receives the frame signal F sent from the controller 64.
Subframe memory 54 for each frame in response to LM
57 are selected in sequence. Memory selector 58 has an
A shift register 59 is connected. The memory selector 58 reads bit data line-sequentially from the selected subframe memory and transfers it to the X shift register 59. An X driver 60 is connected to the X shift register 59. The X driver 60 drives the pixel array 61 based on the bit data latched in the X shift register 59 in response to the synchronization signal 5INC sent from the controller 64.

A Y shift register 63 is connected to the controller 64 via a scan memory 62. scan memory 6
2 is a frame signal FLM sent from the controller 64
in response to the line sequential scanning data SCN for each frame.
Transfer to shift register 63.

A Y driver 65 is connected between the Y shift register 63 and the pixel array 61. This Y driver 65 controls line sequential scanning data SC latched in the Y shift register 63.
A plurality of scanning lines are sequentially selected based on N in synchronization with a line sequential synchronization signal 5YNC.

Finally, the operation of the frame thinning gradation drive circuit will be explained with reference to FIGS. 5 and 6. FIG. 6(A) shows the gradation data GDI held at each address of the frame memory 51.
FIG. 5 is a schematic diagram showing levels of GD5 to GD5. Gradation data CDI indicates pixel transmittance of 0%, tone data GD2 indicates transmittance of 25%, and tone data GD3 indicates transmittance of 50%.
The gradation data GD4 indicates a transmittance of 75%, and the gradation data GD5 indicates a transmittance of 100%. FIG. 6(B) shows the bit structure of the gradation data converted by the decoder 52. Both consist of 4-bit components. The first to fourth bit components of the converted tone data CDI are all 0. The first of the converted gradation data CD2
The bit component is 1 and the remaining bit components are 0. Similarly, the first and second of the converted gradation data GD3
The bit component is 1 and the third and fourth bit components are 0. The first to third bit components of the converted gradation data GD4 are 1, and the fourth bit component is O. The first to fourth bit components of the converted gradation data GD5 are all 1. For each pixel, the first bit component is transferred to the first subframe memory 54, the second bit component is transferred to the second subframe memory 55, and the third bit component is transferred to the third subframe memory 55.
The fourth bit component is transferred to the subframe memory 56, and the fourth bit component is transferred to the fourth subframe memory 57. The controller B4 outputs a frame signal FLM for each frame. The memory selector 58 sequentially selects four subframe memories 54 to 57 for each frame in response to the frame signal FLM. Therefore, all subframe memories are read out in four frames, and data constituting one screen is obtained. That is, the data constituting one screen was originally stored in the frame memory 51. In other words,
Four frames are required to display one screen. Therefore,
The frame frequency is four times faster than that of the conventional gradation display method.

First, in the first frame period, the bit data stored in the first subframe memory 54 is read out line sequentially and latched into the X shift register 59. The latched bit data is transferred to the corresponding pixel row via the X driver 6o in synchronization with the line sequential synchronization signal 5YNC. At this time, the Y driver 65 also receives the line sequential synchronization signal 5YN.
Each pixel row is selected in synchronization with C. In this manner, the amount of electricity corresponding to the first bit component is supplied to each pixel during the first frame period. Similarly, in the second frame period, the amount of electricity corresponding to the second bit component is supplied to each pixel. Subsequently, in the third frame, the amount of electricity corresponding to the third bit component is supplied to each pixel, and finally, in the fourth frame period, the amount of electricity corresponding to the fourth bit component is supplied to each pixel. In this way, at the end of one cycle consisting of the first to fourth frames, an amount of electricity proportional to the grayscale data GD is accumulated and held in each pixel. As a result, one gradation-displayed screen is displayed on the pixel array 61 in one cycle.

In this frame thinning gradation control, the frame frequency is fast, so screen flicker does not occur.

〔Effect of the invention〕

As described above, in the present invention, the switching element for driving the pixel electrode group is composed of a fast-responsive insulated gate field effect transistor formed in a silicon single crystal thin film layer. Therefore, the frame frequency can be made significantly higher than that of the conventional thin film type active matrix device, and there is an effect that gradation display by the so-called frame thinning method can be performed at a practical level.

[Brief explanation of drawings]

Fig. 1 is a schematic exploded perspective view of the frame thinning gradation drive light valve device, Figs. 2 (A) and (B) are schematic diagrams for explaining the operation of the light valve device, and Fig. 3 is the light valve device. A graph showing the voltage dependence of the transmittance of FIG.
FIG. 5 is a block diagram showing the configuration of the frame thinning gradation control circuit built into the light valve device, and FIG. It is a schematic diagram. 1... Composite substrate 3... Liquid crystal layer 5... Switch element 7... Single crystal silicon thin film layer 9... Scanning line 10... Signal line 11...
...X driver 12...Y driver driver 3
...Frame thinning gradation control circuit 14...Glass carrier I6...Common electrode 17...Alignment film
1g-0, alignment film 2... counter substrate 4... pixel electrode 6... carrier layer Fig. 2 (A) Fig. 2 (B) Haze pressure applied to glazing product (V) 1 to 3 Fig. Figure Figure

Claims (1)

[Scope of Claims] 1. A composite substrate comprising an electrically insulating carrier layer and a semiconductor single crystal thin film layer, a plurality of pixel electrodes defining pixels, and a plurality of switch elements for supplying power to the corresponding pixel electrodes. A pixel array integrally formed on the semiconductor single-crystal thin film layer, a counter substrate disposed opposite to the composite substrate with a predetermined gap in between, and a power supply amount held by each pixel electrode disposed in the gap. an electro-optical material layer for performing electro-optical gradation display for each pixel, and driving the plurality of switching elements by frame thinning;
A light valve device comprising a frame thinning gradation drive circuit for controlling the amount of power supplied to the corresponding pixel electrode. 2. The light valve device of claim 1, wherein the composite substrate has a semiconductor single crystal thin film layer adhered to the carrier layer and polished to thin film. 3. The light valve device according to claim 1, wherein the pixel array includes a switching element made of an insulated gate field effect single crystal thin film transistor. 4. The light valve device according to claim 1, wherein the electro-optic material layer is made of twisted nematic liquid crystal whose transmittance to incident light changes in proportion to the amount of power supplied to each pixel electrode. 5. The light valve device according to claim 1, wherein at least a portion of the frame thinning gradation drive circuit is formed in the semiconductor single crystal thin film layer.