JPH04115511A - Manufacture of soi substrate - Google Patents
Manufacture of soi substrateInfo
- Publication number
- JPH04115511A JPH04115511A JP23474290A JP23474290A JPH04115511A JP H04115511 A JPH04115511 A JP H04115511A JP 23474290 A JP23474290 A JP 23474290A JP 23474290 A JP23474290 A JP 23474290A JP H04115511 A JPH04115511 A JP H04115511A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- substrate
- oxide layer
- layer
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- -1 oxygen ion Chemical class 0.000 claims abstract description 6
- 230000002950 deficient Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 16
- 230000007704 transition Effects 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 239000013078 crystal Substances 0.000 description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[概要]
絶縁層上に単結晶シリコン層が形成されたSOI (S
ilicon On In5ulator)基板の製造
方法に関し、表面の不純物濃度を正確に把握でき、リー
ク電流が発生することがない良好な特性のSOI基板を
製造することができるSOI基板の製造方法を提供する
ことを目的とし、
シリコン基板内部に酸素をイオン注入した後に熱処理し
、前記シリコン基板表面の単結晶シリコン層下の内部に
埋込まれた埋込みシリコン酸化層を形成する工程と、前
記単結晶シリコン層表面を酸化して表面シリコン酸化層
を形成する工程と、前記表面シリコン酸化層が接着され
るように前記シリコン基板を支持基板に貼り合せる工程
と、前記シリコン基板の基板部分を前記埋込みシリコン
酸化層が露出するまで基板底面からエツチング除去する
工程と、前記埋込みシリコン酸化層を、前記単結晶シリ
コン層が露出するまでエツチング除去する工程と、前記
単結晶シリコン層の露出表面を酸化し、そのシリコン酸
化層をエツチング除去することにより、前記単結晶シリ
コン層の露出表面の欠陥領域を除去する工程とを有する
ように構成する。[Detailed Description of the Invention] [Summary] SOI (S
An object of the present invention is to provide a method for manufacturing an SOI substrate in which the impurity concentration on the surface can be accurately determined and an SOI substrate with good characteristics without leakage current can be manufactured. A step of implanting oxygen ions into a silicon substrate and then performing heat treatment to form a buried silicon oxide layer buried inside the single crystal silicon layer on the surface of the silicon substrate; a step of oxidizing to form a surface silicon oxide layer; a step of bonding the silicon substrate to a support substrate so that the surface silicon oxide layer is adhered; and a step of burying a substrate portion of the silicon substrate so that the silicon oxide layer is exposed. etching away the buried silicon oxide layer from the bottom surface of the substrate until the single crystal silicon layer is exposed; and oxidizing the exposed surface of the single crystal silicon layer to remove the silicon oxide layer. and removing defective regions on the exposed surface of the single crystal silicon layer by etching.
[産業上の利用分野コ
本発明は絶縁層上に単結晶シリコン層が形成されたS
OI (Silicon On In5ulator)
基板の製造方法に関する。[Industrial Application Fields] The present invention is directed to S in which a single crystal silicon layer is formed on an insulating layer.
OI (Silicon On In5ulator)
The present invention relates to a method for manufacturing a substrate.
SOI基板上に半導体素子を形成するSOI技術が、■
絶縁物による完全な素子間分離が可能である、■CMO
3におけるラッチアップがなく高密度化が可能である、
■寄生容量を低減できるので高速動作が期待できる技術
として注目されている。SOI基板を形成するための基
本的な方法としては、■絶縁物基板上に単結晶シリコン
層を形成する方法、■シリコン酸化層上の非晶質シリコ
ンを単結晶化させる方法、■シリコン基板表面に単結晶
層を残して埋込みシリコン酸化層を形成する方法、■支
持基板とシリコン基板を貼合わせてシリコン基板を底面
から除去して支持基板上に単結晶シリコン層を形成する
方法、がある。SOI technology, which forms semiconductor elements on SOI substrates, is
■CMO that allows complete isolation between elements using insulators
There is no latch-up in 3, and high density is possible.
■It is attracting attention as a technology that can be expected to achieve high-speed operation because it can reduce parasitic capacitance. The basic methods for forming an SOI substrate include: ■ forming a single crystal silicon layer on an insulating substrate; ■ forming a single crystal of amorphous silicon on a silicon oxide layer; and ■ forming a single crystal silicon layer on a silicon oxide layer. There are two methods: (1) forming a buried silicon oxide layer while leaving a single crystal layer; and (2) bonding a support substrate and a silicon substrate together, removing the silicon substrate from the bottom and forming a single crystal silicon layer on the support substrate.
[従来の技術]
シリコン基板表面に単結晶層を残して埋込みシリコン酸
化層を形成するSOI基板を製造する方法として、シリ
コン基板に高濃度の酸素イオンを高エネルギで打込んで
、シリコン基板内部に埋込みシリコン酸化層を形成する
S I M OX (Separation by I
mplanted Oxygen)技術が知られている
。[Prior Art] As a method of manufacturing an SOI substrate in which a buried silicon oxide layer is formed while leaving a single crystal layer on the surface of a silicon substrate, oxygen ions of high concentration are implanted into the silicon substrate with high energy to form a buried silicon oxide layer inside the silicon substrate. SIM OX (Separation by I) forming a buried silicon oxide layer
(planted Oxygen) technology is known.
しかしながら、SIMOX技術の場合、シリコン基板内
部に形成される埋込みシリコン酸化層がイオン注入によ
り形成されるため、埋込みシリコン酸化層と単結晶シリ
コン層との境界における遷移領域に欠陥が発生し、リー
ク電流が発生するという問題があった。However, in the case of SIMOX technology, the buried silicon oxide layer formed inside the silicon substrate is formed by ion implantation, so defects occur in the transition region at the boundary between the buried silicon oxide layer and the single crystal silicon layer, resulting in leakage current. There was a problem that occurred.
支持基板とシリコン基板を貼合わせてシリコン基板を底
面から除去して支持基板上に単結晶シリコン層を形成す
る方法として、不純物濃度によるエツチング率の違いを
利用してシリコン基板のエツチングストッパとする技術
がある。シリコン基板に不純物を添加して不純物濃度の
興なる層を形成しておき、不純物濃度によりエツチング
率が相違するエツチング液により、支持基板にはりあわ
せたシリコン基板を底面からエツチングし、不純物濃度
の興なる層でエツチングをストップさせる。A method of bonding a supporting substrate and a silicon substrate together and removing the silicon substrate from the bottom to form a single crystal silicon layer on the supporting substrate. A technique that uses the difference in etching rate depending on impurity concentration to act as an etching stopper for the silicon substrate. There is. An impurity is added to the silicon substrate to form a layer with a high impurity concentration, and the silicon substrate laminated to the support substrate is etched from the bottom using an etching solution whose etching rate differs depending on the impurity concentration. Stop the etching with a new layer.
しかしながら、この方法では高濃度不純物層から低濃度
不純物層への遷移領域でエツチングが停止してしまう、
このためエツチングにより露出しなSOI基板の表面の
不純物濃度が定まらないという問題があった。However, with this method, etching stops at the transition region from the high concentration impurity layer to the low concentration impurity layer.
For this reason, there is a problem in that the impurity concentration on the surface of the SOI substrate that is not exposed by etching is not determined.
[発明が解決しようとする課Il!]
このように従来は、S IMOX技術の場合、埋込みシ
リコン酸化層と単結晶シリコンとの境界における遷移領
域に欠陥が発生し、リーク電流が発生するという問題が
あった。また、貼合わせ技術の場合、SOI基板表面の
不純物濃度が定まらないという問題があった。[The problem that the invention seeks to solve! ] Conventionally, in the case of the SIMOX technology, there has been a problem in that defects occur in the transition region at the boundary between the buried silicon oxide layer and the single crystal silicon, resulting in leakage current. Further, in the case of the bonding technique, there is a problem that the impurity concentration on the surface of the SOI substrate is not determined.
本発明の目的は、表面の不純物濃度を正確に把握でき、
リーク電流が発生することがない良好な特性のSOI基
板を製造することができるSOI基板の製造方法を提供
することにある。The purpose of the present invention is to be able to accurately determine the impurity concentration on the surface;
An object of the present invention is to provide a method for manufacturing an SOI substrate that can manufacture an SOI substrate with good characteristics that does not generate leakage current.
[課題を解決するための手段]
上記目的は、シリコン基板内部に酸素をイオン注入した
後に熱処理し、前記シリコン基板表面の単結晶シリコン
層下の内部に埋込まれた埋込みシリコン酸化層を形成す
る工程と、前記単結晶シリコン層表面を酸化して表面シ
リコン酸化層を形成する工程と、前記表面シリコン酸化
層が接着されるように前記シリコン基板を支持基板に貼
り合せる工程と、前記シリコン基板の基板部分を前記埋
込みシリコン酸化層が露出するまで基板底面からエツチ
ング除去する工程と、前記埋込みシリコン酸化層を、前
記単結晶シリコン層が露出するまでエツチング除去する
工程と、前記単結晶シリコン層の露出表面を酸化し、そ
のシリコン酸化層をエツチング除去することにより、前
記単結晶シリコン層の露出表面の欠陥領域を除去する工
程とを有することを特徴とするSOI基板の製造方法に
よって達成される。[Means for Solving the Problem] The above object is to implant oxygen ions into a silicon substrate and then perform heat treatment to form a buried silicon oxide layer buried inside a single crystal silicon layer on the surface of the silicon substrate. a step of oxidizing the surface of the single crystal silicon layer to form a surface silicon oxide layer; a step of bonding the silicon substrate to a support substrate so that the surface silicon oxide layer is bonded; etching away the substrate portion from the bottom surface of the substrate until the buried silicon oxide layer is exposed; etching and removing the buried silicon oxide layer until the single crystal silicon layer is exposed; and exposing the single crystal silicon layer. This is achieved by a method for manufacturing an SOI substrate, which comprises the steps of: removing defective regions on the exposed surface of the single crystal silicon layer by oxidizing the surface and etching away the silicon oxide layer.
[作用]
本発明によれば、表面の不純物濃度を正確に把握でき、
リーク電流が発生することがない良好な特性のSOI基
板を製造する二かとができる。[Operation] According to the present invention, the impurity concentration on the surface can be accurately determined,
It is possible to manufacture an SOI substrate with good characteristics that does not cause leakage current.
[実施例]
本発明の一実施例によるSOI基板の製造方法を第1図
を用いて説明する。[Example] A method for manufacturing an SOI substrate according to an example of the present invention will be described with reference to FIG.
まず、シリコン基板10に酸素イオンを、加速エネルギ
が約200keVで、ドーズ量が1018cm−2の条
件でイオン注入し、その後、約1200℃の高温熱処理
を行う。すると、シリコン基板10表面の単結晶が維持
されたまま内部に埋込みシリコン酸化層12が形成され
る。しかし、シリコン基板10表面の単結晶シリコン層
14と埋込みシリコン酸化層12の間には欠陥の多い遷
移領域18が存在している。続いて、単結晶シリコン層
14の表面を酸化して約1100n厚のシリコン酸化層
16を形成する(第1図(a))。First, oxygen ions are implanted into the silicon substrate 10 at an acceleration energy of about 200 keV and a dose of 1018 cm-2, and then high-temperature heat treatment at about 1200° C. is performed. Then, a buried silicon oxide layer 12 is formed inside the silicon substrate 10 while maintaining the single crystal on the surface thereof. However, a transition region 18 with many defects exists between the single crystal silicon layer 14 and the buried silicon oxide layer 12 on the surface of the silicon substrate 10. Subsequently, the surface of the single crystal silicon layer 14 is oxidized to form a silicon oxide layer 16 with a thickness of approximately 1100 nm (FIG. 1(a)).
次に、支持用のシリコン基板20を用意し、その表面に
シリコン酸化層16が接着されるようにシリコン基板1
0を裏返して貼合わせる。続いて、フッ酸(HF)と硝
酸(HNO,)を主成分とするエツチング液により、シ
リコン基板10の基板部分を底面からエツチングする(
第1図(b))。埋込みシリコン酸化層12がエツチン
グストッパとなって、埋込みシリコン酸化1112が露
出するまでエツチングが進行する。Next, a silicon substrate 20 for support is prepared, and the silicon substrate 1 is placed so that the silicon oxide layer 16 is adhered to the surface thereof.
Turn 0 over and paste it together. Next, the substrate portion of the silicon substrate 10 is etched from the bottom using an etching solution mainly composed of hydrofluoric acid (HF) and nitric acid (HNO).
Figure 1(b)). The buried silicon oxide layer 12 serves as an etching stopper, and etching progresses until the buried silicon oxide layer 1112 is exposed.
次に、フッ酸(HF)を主成分とするエツチング液によ
り埋込みシリコン酸化層12をエツチング除去する(第
1図(C))。単結晶シリコン層14がエツチングスト
ッパとなり、単結晶シリコン層14が露出するまでエツ
チングが進行し、単結晶シリコン層14の欠陥の多い遷
移領域18が表面に露出している。Next, the buried silicon oxide layer 12 is etched away using an etching solution containing hydrofluoric acid (HF) as a main component (FIG. 1(C)). The single-crystal silicon layer 14 serves as an etching stopper, and etching progresses until the single-crystal silicon layer 14 is exposed, and the transition region 18 of the single-crystal silicon layer 14, which has many defects, is exposed at the surface.
次に、欠陥の多い遷移領域18が全て酸化されるように
所定時間ウェット酸化を行いシリコン酸化層18′を形
成する(第1図(d))。続いて、そのシリコン酸化層
18′をフッ酸(HF)を主成分とするエツチング液に
より選択的にエツチング除去する(第1図(e))、こ
のようにして露出された単結晶シリコン層14は、表面
における欠陥の多い遷移領域18が除去され、良好な単
結晶シリコン層14がシリコン酸化層16上に形成され
たSOI基板となる。また、単結晶シリコン層14はシ
リコン基板10の不純物濃度と同じ値であるので予め正
確に把握できる。Next, wet oxidation is performed for a predetermined time so that the transition region 18 with many defects is completely oxidized to form a silicon oxide layer 18' (FIG. 1(d)). Subsequently, the silicon oxide layer 18' is selectively etched away using an etching solution containing hydrofluoric acid (HF) as a main component (FIG. 1(e)), and the single crystal silicon layer 14 exposed in this way is removed. In this case, the transition region 18 with many defects on the surface is removed, and a good single crystal silicon layer 14 is formed on the silicon oxide layer 16, resulting in an SOI substrate. Further, since the impurity concentration of the single crystal silicon layer 14 is the same as the impurity concentration of the silicon substrate 10, it can be accurately determined in advance.
本発明は上記実施例に限らず種々の変形が可能である。The present invention is not limited to the above embodiments, and various modifications are possible.
例えば、支持基板としてはシリコン基板を支持できるも
のであれば、いかなる種類の基板を用いてもよい。For example, any type of substrate may be used as the support substrate as long as it can support a silicon substrate.
[発明の効果]
以上の通り、本発明によれば、表面の不純物濃度を正確
に把握でき、リーク電流が発生することがない良好な特
性のSOI基板を製造することができる。[Effects of the Invention] As described above, according to the present invention, the impurity concentration on the surface can be accurately determined, and an SOI substrate with good characteristics without leakage current can be manufactured.
第1図は本発明の一実施例によるSOI基板の製造方法
の工程断面図である。
図において、
10・・・シリコン基板
12・・・埋込みシリコン酸化層
14・・・単結晶シリコン層
16・・・シリコン酸化層
18・・・遷移領域
18′・・・シリコン酸化層
20・・・シリコン基板FIG. 1 is a process sectional view of a method for manufacturing an SOI substrate according to an embodiment of the present invention. In the figure, 10...Silicon substrate 12...Buried silicon oxide layer 14...Single crystal silicon layer 16...Silicon oxide layer 18...Transition region 18'...Silicon oxide layer 20... silicon substrate
Claims (1)
理し、前記シリコン基板表面の単結晶シリコン層下の内
部に埋込まれた埋込みシリコン酸化層を形成する工程と
、 前記単結晶シリコン層表面を酸化して表面シリコン酸化
層を形成する工程と、 前記表面シリコン酸化層が接着されるように前記シリコ
ン基板を支持基板に貼り合せる工程と、前記シリコン基
板の基板部分を前記埋込みシリコン酸化層が露出するま
で基板底面からエッチング除去する工程と、 前記埋込みシリコン酸化層を、前記単結晶シリコン層が
露出するまでエッチング除去する工程と、前記単結晶シ
リコン層の露出表面を酸化し、そのシリコン酸化層をエ
ッチング除去することにより、前記単結晶シリコン層の
露出表面の欠陥領域を除去する工程と を有することを特徴とするSOI基板の製造方法。[Claims] 1. A step of implanting oxygen ions into the silicon substrate and then performing heat treatment to form a buried silicon oxide layer buried inside the single crystal silicon layer on the surface of the silicon substrate; oxidizing the surface of the crystalline silicon layer to form a surface silicon oxide layer; bonding the silicon substrate to a support substrate so that the surface silicon oxide layer is adhered; and embedding the substrate portion of the silicon substrate. etching away the silicon oxide layer from the bottom surface of the substrate until the silicon oxide layer is exposed; etching away the buried silicon oxide layer until the single crystal silicon layer is exposed; oxidizing the exposed surface of the single crystal silicon layer; A method for manufacturing an SOI substrate, comprising the step of removing a defective region on an exposed surface of the single crystal silicon layer by etching away the silicon oxide layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23474290A JPH04115511A (en) | 1990-09-05 | 1990-09-05 | Manufacture of soi substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23474290A JPH04115511A (en) | 1990-09-05 | 1990-09-05 | Manufacture of soi substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04115511A true JPH04115511A (en) | 1992-04-16 |
Family
ID=16975650
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23474290A Pending JPH04115511A (en) | 1990-09-05 | 1990-09-05 | Manufacture of soi substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04115511A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000024059A1 (en) * | 1998-10-16 | 2000-04-27 | Shin-Etsu Handotai Co., Ltd. | Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method |
WO2004010505A1 (en) * | 2002-07-18 | 2004-01-29 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and production method therefor |
WO2005074033A1 (en) | 2004-01-30 | 2005-08-11 | Sumco Corporation | Method for manufacturing soi wafer |
JP2006173568A (en) * | 2004-12-14 | 2006-06-29 | Korea Electronics Telecommun | Method of manufacturing soi substrate |
JP2006294957A (en) * | 2005-04-13 | 2006-10-26 | Shin Etsu Handotai Co Ltd | Joined soi wafer and method for manufacturing the same |
EP1914799A1 (en) * | 2005-07-29 | 2008-04-23 | Shanghai Simgui Technology Co., Ltd | Method for manufacturing silicon on insulator |
-
1990
- 1990-09-05 JP JP23474290A patent/JPH04115511A/en active Pending
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100607186B1 (en) * | 1998-10-16 | 2006-08-01 | 신에쯔 한도타이 가부시키가이샤 | Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method |
US6372609B1 (en) | 1998-10-16 | 2002-04-16 | Shin-Etsu Handotai Co., Ltd. | Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method |
WO2000024059A1 (en) * | 1998-10-16 | 2000-04-27 | Shin-Etsu Handotai Co., Ltd. | Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method |
WO2004010505A1 (en) * | 2002-07-18 | 2004-01-29 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and production method therefor |
EP1710836A1 (en) * | 2004-01-30 | 2006-10-11 | SUMCO Corporation | Method for manufacturing soi wafer |
WO2005074033A1 (en) | 2004-01-30 | 2005-08-11 | Sumco Corporation | Method for manufacturing soi wafer |
EP1710836A4 (en) * | 2004-01-30 | 2010-08-18 | Sumco Corp | Method for manufacturing soi wafer |
US7867877B2 (en) | 2004-01-30 | 2011-01-11 | Sumco Corporation | Method for manufacturing SOI wafer |
JP2006173568A (en) * | 2004-12-14 | 2006-06-29 | Korea Electronics Telecommun | Method of manufacturing soi substrate |
US7601614B2 (en) | 2004-12-14 | 2009-10-13 | Electronics And Telecommunications Research Institute | Manufacturing method of silicon on insulator wafer |
JP2006294957A (en) * | 2005-04-13 | 2006-10-26 | Shin Etsu Handotai Co Ltd | Joined soi wafer and method for manufacturing the same |
EP1914799A1 (en) * | 2005-07-29 | 2008-04-23 | Shanghai Simgui Technology Co., Ltd | Method for manufacturing silicon on insulator |
EP1914799A4 (en) * | 2005-07-29 | 2010-03-17 | Shanghai Simgui Technology Co | Method for manufacturing silicon on insulator |
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