JPH0411386A - Dynamic ram - Google Patents

Abstract

PURPOSE:To reduce the current consumption by providing a sense amplifier power source circuit which uses an internal supply voltage as the sense amplifier supply voltage in the restore period. CONSTITUTION:The sense amplifier power source circuit is provided with a comparator which compares a reference voltage signal VR and a sense amplifier voltage signal SAP with each other, a NAND gate 13 to which not only a signal CN is inputted through an inverter 12 but also a signal SEN is inputted, and a P-channel transistor TR QP11. Only in the restore period, the TR QP11 is turned off and the signal SAP is electrically disconnected from the external supply voltage, and meanwhile, a TR QN11 is turned on and the comparator starts the operation to start comparison between signals VR and SAP. Consequently, the potential drop of SAP is smaller than conventional, and the time required for completion of the restore operation is shortened. Thus, the current required for comparing operation and the current consumption are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic RAM, and more particularly to a one-transistor type dynamic RAM that uses an internal power supply voltage boosted from an external power supply voltage.

[Prior Art] As dynamic RAMs become more highly integrated, the size of individual transistors has also become smaller. However, making the transistor smaller leads to a decrease in reliability. Therefore, the voltage applied from the external power supply is still 5V,
3. The voltage of the internal power supply that boosted this voltage. 3VL/memories have appeared that aim to reduce stress on transistors and improve reliability.

However, if the voltage of the internal power source is lowered, the operating speed will decrease. To solve this problem, the conventional dynamic RAM described here reduces the size of only the transistors in the memory cells, which occupy most of the chip area and have little effect on the operating speed, and lowers the operating voltage. High integration is achieved without reducing operating speed.

Here, the above dynamic RAM will be explained using figures.

Fig. 4 is a block diagram of a conventionally known dynamic RAM, Fig. 5 is an operating waveform diagram explaining its operation, Fig. 6 is a block diagram of a conventional sense amplifier power supply circuit, and Fig. 7 is its control timing. It is a diagram.

As shown in FIG. 4, the dynamic RAM includes a large number of memory cells M each consisting of an N-channel type gate transistor QM and a capacitor C1, bit lines DC and D connected to the memory cells M, and an N-channel type QN3. ．． QN4
bit line DC,' through a transfer gate consisting of
Bit line DS on the sense amplifier side connected to 15'-
, DS and P-channel transistors QPI, QP
2. A sense amplifier SA consisting of N-channel transistors QNI and QN2 and connected between bit lines DS and DS, an N-channel transistor QN5゜QN6 for precharging the bit lines, and a transistor for balancing the bit lines. N-channel transistor QN7 and bit line DS,
■N-channel type transistor QN8゜QN9 which connects the terminal to the data input/output line, the reference voltage generation circuit 1 which generates the reference voltage signal VR of the internal type R voltage VINT, and the drive voltage signals SAP and SAN to the sense amplifier SA. A sense amplifier power supply circuit 2 supplies a control signal TG to a transfer gate, a transfer power supply circuit 3 supplies a control signal TG to a transfer gate, a decoder 4 selects a word line WL connected to the gate of a transistor QM of a memory cell M, and a selected A word line power supply circuit 5 that supplies a control voltage to the word line, and an intermediate potential power supply circuit 6 that supplies a precharge voltage to the bit line.
It is equipped with

In the above dynamic RAM, as shown in FIG.
First, the word line WL is boosted to a potential VTN+VINT higher than the potential VINT of the reference voltage signal VR by the threshold voltage VTN of the N-channel transistor QM. Then, charge is released from the memory cell M to the bit lines DC and DS, and the other bit line 2 is discharged.

A potential difference is created with DS. Next, the control signal TG becomes low level, and the transistor QN3. When QN4 is turned off, DC is electrically isolated from the bit lines DS and DS on the sense amplifier side, as well as the bit lines on the memory cell side. Then, the sense amplifier SA operates, and the potential difference between DS and DS is amplified. At this time, the sense amplifier power supply circuit 2 limits the sense amplifier power supply voltage signal SAP so that it does not exceed the internal power supply voltage VINT. Next, its operation will be explained.

As shown in FIG. 6, the output section of the sense amplifier power supply circuit 2 outputs a reference voltage signal VR and a sense amplifier power supply voltage signal SA.
A comparator 21 that compares P with P, a NAND gate 22 to which the output of the comparator and the control signal CN are input, and a NAND gate 22 to which the output of the NAND gate 22 and the control signal SEN are input.
A P-channel transistor Q P21 is interposed between the gate 23, the external power supply and the sense amplifier voltage SAP, and the output of the NAND gate 23 is input to the gate. signal CN to the gate
, and an N-channel transistor QN21 which is interposed between the other sense amplifier voltage SAN and the ground potential and whose gate receives a signal SEN.

The flow of the control signal for the sense amplifier power supply circuit 20 is as shown in FIG. The signal CN becomes high level and the comparison between SAP and VR begins.

Also, almost at the same time, SEN becomes high level and the sense amplifier SA starts operating. As this sensing operation progresses, the potentials of the bit line on the high level side and SAP become the same potential and slowly rise.

Then, when SAP reaches the same potential VINT as VR, the output signal CMP of the NAND gate 22 becomes low level, the transistor QP21 is turned off, and the power supply to SAP is cut off. Here, if the bit line is rewritten during the active period of the control signal RAS, the potential of SAP will drop a little, so in that case, CMP will be at a high level for the necessary period, turning on transistor Q P21, and SA
Return the potential of P to VINT. In this way, in order to keep the potential of SAP at VINT, CN is kept at a high level during the active period, transistor QN20 is turned on, and comparator 21 continues to flow current.

On the other hand, at the time of reset, after RAS becomes high level, the signal TG becomes VCC+VTN, the bit lines DS and DS are electrically connected to DC and N, and the data storage operation to the memory cell M begins. Now, the external power supply voltage vCC
5V, and the internal power supply voltage VINT is 3.3■, the bit line DS on the sense amplifier side.

■If the ratio of the capacitance tcI and the capacitance ff1c2 of the bit lines DC and D on the memory cell side is C1:C2=I:2, then immediately after the transfer gate is connected, the bit line on the high level side is divided into two capacitances. It becomes .2V, and SAP also becomes 2.2V.
V falls. Therefore, the signal CMP becomes high level, and the potential of SAP is raised to VINT.

Then, after SAP is sufficiently raised, the word line WL
becomes low level and the restore operation ends. here,
In the restore operation, transfer gate QN3. QN
4, the transfer gate of the bit line on the low level side is turned on first, so the transfer gate of the bit line on the high level side limits the completion of the operation.

[Problems to be Solved by the Invention] In this type of dynamic RAM, when the bit line on the sense amplifier side is connected to the bit line of the example memory cell, the potential of the bit line decreases, and the potential of S A P decreases accordingly. Dynamic R
The cycle time when actually using AM was long. Moreover, since the comparator of the sense amplifier power supply circuit is always operated during the active period, there is a problem in that a large amount of current is consumed.

[Means for Solving the Problems] The dynamic RAM of the present invention enables the bit line to be electrically separated into the sense amplifier side and the memory cell side by interposing a transfer gate, and reads data from the memory cell to the bit line. During the active period when data is amplified by the sense amplifier, the bit line is electrically separated between the sense amplifier side and the memory cell side, and the bit line between the sense amplifier side and the memory cell side is electrically connected using a transfer gate to sense the data. In a dynamic RAM in which a restore period in which data amplified by an amplifier is written into a memory cell follows the active period, the sense amplifier power supply voltage is set as an external power supply voltage during the active period, and the sense amplifier power supply voltage is set as an internal power supply voltage during the restore period. It is characterized by being equipped with a sense amplifier power supply circuit.

Further, in the dynamic RAM of the present invention, in the above invention, the sense amplifier power supply circuit includes a comparator that operates only during the restore period to compare the internal power supply voltage and the sense amplifier power supply voltage, and a comparator that is input to the gate. A transistor is connected to the power supply to boost the sense amplifier power supply voltage when the sense amplifier power supply voltage is lower than the internal power supply voltage based on the input of It is characterized by being equipped with a transistor.

That is, by raising the bit line on the sense amplifier side to the external power supply voltage VCC during the active period, the bit line of the example memory cell is charged at high speed during the store period after reset.

In addition, current consumption is reduced by comparing the sense amplifier power supply voltage and internal power supply voltage only during restoration.

[Example] An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a sense amplifier power supply circuit according to an embodiment of the present invention applied to the sense amplifier power supply circuit 2 of the dynamic RAM shown in FIG. 4, and FIG. 2 is a timing diagram of its control signals. Figure 3 shows the dynamic R according to this embodiment.
FIG. 3 is an operation waveform diagram illustrating the operation of AM.

As shown in FIG. 1, the sense amplifier power supply circuit of this embodiment includes a comparator 11 that compares a reference voltage signal VR and a sense amplifier voltage signal SAP, and a comparator 11 that is interposed between an external power supply voltage and SAP. P where the output of comparator 11 is input to the gate
A channel type transistor Q PI3, an N channel type transistor QNII which is interposed between the comparator 11 and the ground potential and whose gate receives the signal CN, and the other sense amplifier voltage signal SAN and the ground potential. An N-channel transistor QN12 is interposed and receives the signal SEN at its gate, and a NAND gate 1 receives the signal CN via the inverter 12 and receives the signal SEN.
3, and a P-channel transistor QPII which is interposed between the external power supply potential SAP and whose gate receives the output of the NAND gate 13.

The operation of the dynamic RAM equipped with the sense amplifier power supply circuit configured as described above will be explained with reference to FIGS. 2 and 3.

The signal RAS becomes low level, the word line WL becomes high level, the charge of the memory cell is released to the bit line, and the signal TG becomes low level, and the bit line is electrically connected to the memory cell side and the sense amplifier side. During the active period when the sense amplifier starts operating after being separated, the signal CN is at a low level.
The signal SEN becomes high level, and the transistor Q Ni
Since the comparator 11 stops operating because l is turned off, the transistor QPII is turned on and the sense amplifier power supply potential SAP is CC, so the sense amplifier side bit line DS rises to the external power supply voltage VCC. . After that, RAS is reset and a restore period begins, and the transfer gate control signal TG goes high to electrically connect the sense amplifier side and the bit line of the memory cell example, and at the same time, the signal CN goes high. level, the transistor QPII is turned off and SAP is electrically isolated from the external power supply voltage, while the transistor QNII is turned on and the comparator 11 starts operating to start comparing VR and SAP. At this time, since the signal TG becomes high level, the bit line DS on the sense amplifier side and the bit line DC on the memory cell side
is connected, the potential of SAP drops along with DS, but during the active period DS is connected to the external power supply voltage VC.
Since it was pulled to C, VCC=5VSVIN
T=3. 3V, C1: C2=I: 2, the bit line potential is approximately 2°8V, which is lower than before.
The difference up to +N is about half, 0.5V. As a result, the SAP potential drop is smaller than before,
The time it takes to complete a restore operation has been significantly shortened.

Furthermore, the period during which the signal CN goes high and the comparator 11 operates is from the time when the signal TG goes high until the word line WL
After a short period of storage until the level of
Since the operation of the comparator 11 is stopped during the active period, current consumption is significantly reduced.

[Effects of the Invention] As explained above, the present invention can secure the memory cell storage level in a short time by raising the bit line on the sense amplifier side to the power supply voltage during the active period, and the word line can be quickly activated. This has the effect of reducing the cycle time by lowering the level.

Further, by comparing the internal power supply voltage and the sense amplifier power supply voltage only during the restore period, the current required for this comparison operation can be reduced and the current consumption can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a sense amplifier power supply circuit according to an embodiment of the present invention, FIG. 2 is a control timing diagram thereof, FIG. 3 is an operation waveform diagram of a dynamic RAM according to an embodiment of the present invention, and FIG. The figure is a configuration diagram of a general dynamic RAM.
FIG. 6 is an operating waveform diagram of a conventional dynamic RAM, FIG. 6 is a configuration diagram of a sense amplifier power supply circuit according to the conventional example, and FIG. 7 is a control timing diagram thereof. 2...Sense amplifier power supply circuit, 11...
...Comparator, M-- and...Φ◆memory cell, SA...Sense amplifier, DS, DS''...Sense amplifier side bit line, DC
, D... Memory cell side bit line, QN3.
QN4...Transfer gate, QNII,
QPII, QP12...Transistor.

Claims (2)

[Claims] (1) The bit line can be electrically separated into the sense amplifier side and the memory cell side by interposing a transfer gate, and during the active period when the sense amplifier amplifies the data read from the memory cell to the bit line, the sense amplifier side During the restore period, the bit lines are electrically separated between the sense amplifier side and the memory cell side, the bit lines on the sense amplifier side and the memory cell side are electrically connected by a transfer gate, and the data amplified by the sense amplifier is written into the memory cell. The dynamic RAM is characterized in that the dynamic RAM performs the following following the active period, including a sense amplifier power supply circuit that uses the sense amplifier power supply voltage as an external power supply voltage during the active period and uses the sense amplifier power supply voltage as an internal power supply voltage during the restore period. Dynamic RAM. (2) The sense amplifier power supply circuit includes a comparator that operates only during the restore period to compare the internal power supply voltage and the sense amplifier power supply voltage, and a sense amplifier power supply voltage that is internally determined based on the input of the comparator that is input to the gate. A claim characterized in that the transistor includes a transistor that is connected to the power supply to boost the sense amplifier power supply voltage when it is lower than the power supply voltage, and a transistor that is connected to an external power supply and uses the sense amplifier power supply voltage as the external power supply voltage during an active period. 1. The dynamic RAM according to 1.