JPH0410541A - Formation of thin film wiring and manufacturing device - Google Patents

Formation of thin film wiring and manufacturing device

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Publication number
JPH0410541A
JPH0410541A JP11000290A JP11000290A JPH0410541A JP H0410541 A JPH0410541 A JP H0410541A JP 11000290 A JP11000290 A JP 11000290A JP 11000290 A JP11000290 A JP 11000290A JP H0410541 A JPH0410541 A JP H0410541A
Authority
JP
Japan
Prior art keywords
thin film
substrate
wiring
layer
film wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11000290A
Other languages
Japanese (ja)
Inventor
Kenji Hinode
憲治 日野出
Kenji Furusawa
健志 古澤
Natsuki Yokoyama
夏樹 横山
Yoshio Honma
喜夫 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11000290A priority Critical patent/JPH0410541A/en
Publication of JPH0410541A publication Critical patent/JPH0410541A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain an enhancement in the performance of a wiring by a method wherein a distortion of a proper amount is introduced in an Al layer and thereafter, a heat treatment is applied to this Al layer. CONSTITUTION:An insulating film 20 is formed on a semiconductor substrate 10 with an active part formed thereon and thereafter, a wiring layer is formed. A P-type or N-type high-concentration diffused region 11 is formed by an ion implantation performed selectively using a prescribed mask and a heat treatment performed subsequently to the ion implantation. The wiring layer consists of an Al layer 30 and W layers 40 and 41. A thin oxide film formed on the surface of the region 11 is removed using an aqueous solution containing a hydrofluoric acid. The W layer 40 of a film thickness of 100nm is formed on the substrate held at about 200 deg.C by a normal magnetron sputtering method, subsequently, the AlSi film 30 of a film thickness of 500nm is formed on the substrate held at about 200 deg.C and thereafter, the W film 41 of a film thickness of 50nm is again formed. In this state, the substrate with the wiring layer formed thereon is cooled at 0 deg.C or lower using a substrate installing chamber 110 for growing crystal grains to introduce a strain of a proper amount in the layer 30. After that, power which is supplied to a heater 143 is increased and a heat treatment of 200 to 500 deg.C is performed on the layer 30. The Al crystal grains are grown by this treatment.

Description

【発明の詳細な説明】 [産業上の利用分野1 本発明は高集積の半導体装置に係わり、特に高電流密度
用として好適な配線に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to highly integrated semiconductor devices, and particularly to wiring suitable for high current density.

[従来の技術] 半導体用Al合金配線については高信頼化、高性能化の
ために従来から積層化が試みられている。
[Prior Art] Lamination of Al alloy wiring for semiconductors has been attempted in order to improve reliability and performance.

代表的な従来例として、第26回アニュアルプロシーデ
ィングス・リライアビリティフィジックス(1988年
)第173頁から178頁(26th Annual 
Proceedings Re1iability  
Physics(1988)pp、]]73−178な
どを挙げることができる。
As a typical conventional example, 26th Annual Proceedings Reliability Physics (1988), pages 173 to 178 (26th Annual Proceedings Reliability Physics)
Proceedings
Physics (1988) pp, ]] 73-178, and the like.

[発明が解決しようとする課題] 上記従来技術では積層構造化による配線の性能向上率が
ホさく特にエレクトロマイグレーションの点でこれから
の高電流密度化には不十分である。
[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the performance improvement rate of wiring due to the layered structure is low and is insufficient for future high current densities, especially in terms of electromigration.

本発明の目的はこの問題点を解決し、配線の高性能化を
達成することにより微細で高信頼度の半導体配線を堤供
することにある。
An object of the present invention is to solve this problem and provide fine and highly reliable semiconductor wiring by achieving high performance wiring.

[課題を解決するための手段] 本発明においては、Al層に適切な量の歪を導入した後
、これに熱処理を加えることによって、結晶粒を成長さ
せ、上記問題点を解決したものである。
[Means for Solving the Problems] In the present invention, the above problems are solved by introducing an appropriate amount of strain into the Al layer and then applying heat treatment to the Al layer to grow crystal grains. .

[作用1 耐エレクトロマイグレーション性はAl膜の膜質に強く
依存することがわかってきた。上記従来例の場合、積層
配線の寿命は、単層膜配線より長寿命であるが、配線が
微細化してくると、Al単層膜の寿命と同程度か、場合
によってはそれよす短寿命である。
[Effect 1] It has been found that electromigration resistance strongly depends on the quality of the Al film. In the case of the conventional example above, the lifespan of the laminated wiring is longer than that of the single-layer film wiring, but as the wiring becomes finer, the lifespan may be as short as that of the single-layer Al film, or even shorter than that of the single-layer film. It is.

この場合には積層化によってAl膜質がむしろ劣化して
いるとみることができる。例えば通常の方法で作成した
配線では、積層構造の方が結晶粒径が小さく、配向性も
低い。結晶粒径は配線幅に依存し、幅が狭いほど粒径も
小さくなっている。
In this case, it can be considered that the quality of the Al film is rather deteriorated due to the layering. For example, in wiring created by a normal method, the laminated structure has a smaller crystal grain size and a lower orientation. The crystal grain size depends on the wiring width, and the narrower the width, the smaller the grain size.

Al合金と異種導電材料を積層した配線に通電するとA
l原子の移動によりAlの欠損領域(ボイド)が発生す
る。ボイドが成長して配線を横断すると電流は異種導電
材料層を通して流れるがこの部分では抵抗値が大きく電
流密度も高いためジュール熱により局所的に温度が上昇
する。ある限度以上に温度が上がると溶断、酸化等の劣
化過程が進行し、断線に至る。
When electricity is applied to a wiring layered with Al alloy and different conductive materials, A
Due to the movement of l atoms, an Al deficient region (void) is generated. When a void grows and crosses the wiring, current flows through the layer of different conductive materials, but this region has a large resistance and a high current density, causing a local temperature rise due to Joule heat. When the temperature rises above a certain limit, deterioration processes such as fusing and oxidation progress, leading to wire breakage.

Al原子の移動は主に結晶粒界を通じて起こるため、A
l層の結晶配向性をそろえ、結晶粒を粗大化するように
膜質を変化させることによって上記電気特性の劣化を防
止することができる。
Since the movement of Al atoms mainly occurs through grain boundaries, A
By adjusting the crystal orientation of the L layer and changing the film quality so as to coarsen the crystal grains, the above deterioration of the electrical properties can be prevented.

本発明においては、結晶粒を成長させるために、Al層
に適切な量の歪を導入した後、これを熱処理する方法が
有効であることを見出した。これにより従来生していた
AR金合金異種導電材料を積層した配線での両者間の相
互作用によるAff結晶の配向性の乱れ、結晶粒の微細
化による特性劣化の問題を解消することができる。
In the present invention, we have found that it is effective to introduce an appropriate amount of strain into the Al layer and then heat treat it in order to grow crystal grains. As a result, it is possible to solve the conventional problem of disordered orientation of Aff crystals due to interaction between AR gold alloys and deterioration of characteristics due to refinement of crystal grains in interconnects in which conductive materials of different types are laminated.

[実施例] 以下本発明を実施例をもって説明する。[Example] The present invention will be explained below with reference to examples.

実施例1 第1図は半導体素子の断面図を用いて示す本発明の素子
製造工程である。通常の半導体素子製造工程により能動
部分を形成した半導体基板10上に絶縁膜20を形成し
た後、配線層を形成する。
Example 1 FIG. 1 shows the device manufacturing process of the present invention using a cross-sectional view of a semiconductor device. After an insulating film 20 is formed on a semiconductor substrate 10 on which an active part is formed by a normal semiconductor device manufacturing process, a wiring layer is formed.

11は所定のマスクにより選択的におこなったイオンイ
ンプランテーションと引き続いておこなった熱処理によ
って形成した高濃度のP型もしくはN型拡散領域である
。配線はAl層3oとW層40.41とからなる。拡散
領域11表面に形成されている薄い酸化膜をフッ酸を含
む水溶液で除去する。約200℃に保った基板上に通常
のマグネトロンスパッタ法で膜厚1100nのW膜40
を形成し、約200℃に保った基板上に引き続き500
nmのA Q S i膜30を形成後、再度50nmの
W膜41を形成する(第1図a)。
Reference numeral 11 denotes a highly concentrated P-type or N-type diffusion region formed by selectively performing ion implantation using a predetermined mask and subsequent heat treatment. The wiring consists of an Al layer 3o and W layers 40 and 41. The thin oxide film formed on the surface of the diffusion region 11 is removed with an aqueous solution containing hydrofluoric acid. A W film 40 with a thickness of 1100 nm was deposited on a substrate kept at about 200°C by ordinary magnetron sputtering.
was formed on the substrate kept at about 200°C.
After forming the A Q Si film 30 with a thickness of 50 nm, a W film 41 with a thickness of 50 nm is formed again (FIG. 1a).

この状態の、配線層を形成した基板を摂氏零度以下に冷
却してAl層30に歪を導入する。Si基板に比べAl
の熱膨張率が太きく(Siの線膨張率=2.5ppm/
℃、Alの線膨張率=23ppm/’C)、またSi基
板がAlに比へて桁違いに厚いため(Si基板の厚さは
ほぼ500μm)、冷却時の両者の収縮量の差はほとん
どすべてAl層に歪として導入される。
In this state, the substrate on which the wiring layer is formed is cooled to below zero degrees Celsius to introduce strain into the Al layer 30. Compared to Si substrate, Al
has a large coefficient of thermal expansion (coefficient of linear expansion of Si = 2.5 ppm/
℃, coefficient of linear expansion of Al = 23 ppm/'C), and because the Si substrate is an order of magnitude thicker than Al (the thickness of the Si substrate is approximately 500 μm), there is almost no difference in the amount of shrinkage between the two upon cooling. All of this is introduced as strain into the Al layer.

導入する歪量を変えるため、第2図に示す装置を用いた
。この装置については実施例3で詳述する。熱伝導度の
高いAl金合金作られたウェハホルダー145にウェハ
を保持し、断熱層144の真空度とヒータ143の発熱
量を調整して、0℃から一200℃の間の冷却温度に基
板を約10分保持する。この状態でAlの結晶はほとん
ど粒成長せず、粒径は1100−500n程度であり、
Al中には多量の歪が導入される。図中の土の記号は転
位を現わし、歪が導入されていることを示している(第
1図b)。
In order to vary the amount of strain introduced, an apparatus shown in FIG. 2 was used. This device will be described in detail in Example 3. The wafer is held in a wafer holder 145 made of an Al-gold alloy with high thermal conductivity, and the vacuum level of the heat insulating layer 144 and the amount of heat generated by the heater 143 are adjusted to cool the substrate to a cooling temperature between 0°C and -200°C. Hold for about 10 minutes. In this state, Al crystals hardly grow, and the grain size is about 1100-500n.
A large amount of strain is introduced into Al. The soil symbol in the figure represents a dislocation, indicating that strain has been introduced (Figure 1b).

その後、この装置のヒータ143に供給するパワーを増
加させて200°C〜500°Cの熱処理を施す。この
処理によってAlの結晶粒が成長するが、冷却工程を施
して歪を導入したAlでは、この処理を施さないものに
比べて最終の結晶粒径が大きくなる(第1図C)。結晶
粒が大きくなる度合いは、冷却温度、加熱処理温度によ
って異なるが、冷却工程を設けることにより、冷却しな
い場合に比べて、Alの粒径が20〜]−00%大きく
なる。
Thereafter, the power supplied to the heater 143 of this device is increased to perform heat treatment at 200°C to 500°C. This treatment causes Al crystal grains to grow, and the final crystal grain size of Al that has been strained through a cooling process is larger than that of Al that is not subjected to this treatment (FIG. 1C). Although the degree to which the crystal grains become larger varies depending on the cooling temperature and the heat treatment temperature, by providing a cooling step, the grain size of Al becomes larger by 20 to ]-00% compared to the case without cooling.

通常のフォトエツチングプロセスを用いて配線の形状に
加工し、表面を絶縁膜50で覆った後、外部接続部51
のみ絶縁膜50を除去する(第1図d)。
After processing into a wiring shape using a normal photo-etching process and covering the surface with an insulating film 50, an external connection part 51 is formed.
Only the insulating film 50 is removed (FIG. 1d).

これらの配線に通電し、エレクトロマイグレーション1
性を測定した結果を、第1表および第3図に示す。
Electrify these wires and electromigration 1
The results of measuring the properties are shown in Table 1 and FIG.

従来の通常の処理を施したものでは配線が微細化するに
つれ急激に配線の信頼度が低下し、特に幅1.0μm以
下の配線での信頼度低下が著しいが、本発明の処理を施
すと、配線が微細化し、幅1.0μm以下になってもほ
ぼ一定の信頼度を保つことができる。
With conventional conventional processing, the reliability of the interconnects decreases rapidly as the interconnects become finer, and the decrease in reliability is particularly significant for interconnects with a width of 1.0 μm or less, but with the treatment of the present invention, Even when the wiring becomes finer and the width becomes less than 1.0 μm, almost constant reliability can be maintained.

第1表 換算配線寿命特性(単位:10G秒)配線構造
: W/ A Q S i / W (501500/
 loOnm厚)冷却工程の保持温度は配線寿命に強い
影響を与える。第3図に見られるように冷却温度が低い
ほど配線は長寿命化し、−50’C以下でその効果が明
瞭であり、特に−100℃以下で顕著である。
Table 1 Converted wiring life characteristics (unit: 10G seconds) Wiring structure: W/ A Q Si / W (501500/
(loOnm thickness) The holding temperature during the cooling process has a strong influence on the wiring life. As seen in FIG. 3, the lower the cooling temperature, the longer the life of the wiring, and this effect is clear at -50'C or lower, and especially noticeable at -100C or lower.

またAlの結晶粒成長は200℃以上で活発化するため
熱処理はすくなくともこの温度以上で行う必要がある。
Furthermore, since Al crystal grain growth becomes active at temperatures above 200° C., the heat treatment must be performed at at least this temperature or above.

さらに、Alの上層のWの形成をAlの結晶粒がほとん
ど成長しない200℃以下で行ない、その後の工程に供
することにより、配線寿命をさらに数10%から数倍改
善することができる。その際このW膜が強い圧縮応力を
有するほど結晶粒成長を促進する効果が大きい。
Furthermore, by forming W on the upper layer of Al at a temperature below 200° C., at which almost no Al crystal grains grow, and subjecting it to subsequent steps, the wiring life can be further improved by several tens of percent to several times. At this time, the stronger the compressive stress of this W film, the greater the effect of promoting crystal grain growth.

また、この製造方法は第1図に示したサンドイッチ構造
の配線だけでなく、Al層の下側だけ、もしくは上側だ
けに高融点金属層を設けた構造の配線に適用しても同程
度の長寿命化効果がある。
In addition, this manufacturing method can be applied not only to wiring in the sandwich structure shown in Figure 1, but also to wiring in a structure in which a high-melting point metal layer is provided only below or only above the Al layer, and the same length can be applied. It has a lifespan extension effect.

さらにAl単層の配線に適用しても同等の効果が得られ
るが、この際は大きなヒロックが形成されやすいため、
加熱工程が比較的低温(300’C以下)の場合やヒロ
ックが重要な問題になりにくい1層配線の素子等の場合
に限って有効である。
Furthermore, the same effect can be obtained by applying it to single-layer Al wiring, but in this case large hillocks are likely to be formed.
This method is effective only when the heating process is performed at a relatively low temperature (below 300'C) or when the device has a single layer interconnection where hillocks are unlikely to be a serious problem.

以上説明してきた方法は、Al金合金種類や積層する高
融点材料の種類によらない。すなわち、Al層が純Al
であっても、Cu、Si等を高々数%含む合金であって
もよく、高融点材料がW。
The method described above does not depend on the type of Al-gold alloy or the type of high melting point material to be laminated. That is, the Al layer is pure Al.
It may be an alloy containing at most several percent of Cu, Si, etc., and the high melting point material is W.

Mo、Tiやこれらの合金(たとえば、W−10wt%
Ti) 、化合物(たとえば、TiN)のどれであって
も同程度の効果が得られる。第2表にこれらの材料を用
いて上記と同等の製造工程で作成した配線の特性評価結
果を示す。
Mo, Ti and alloys thereof (for example, W-10wt%
Similar effects can be obtained with any of Ti) and compounds (eg, TiN). Table 2 shows the results of evaluating the characteristics of interconnects made using these materials in the same manufacturing process as above.

第2表 換算配線寿命特性(単位:106秒)[A)配
線構造: A fl S i−0,5w%Cu /W 
: (500/1100n厚)CB)配線構造: A 
Q S i / T i W : (500/1100
n厚)〔C〕配線構造:AlSi/TiN: (500
/100止厚)加熱熱処理も冷却工程後にすぐ引き続い
て行う必要はない。パターニング以降に施してもほぼ同
等の効果が得られる。
Table 2 Converted wiring life characteristics (unit: 106 seconds) [A) Wiring structure: A fl Si-0,5w%Cu /W
: (500/1100n thickness) CB) Wiring structure: A
Q S i / T i W: (500/1100
n thickness) [C] Wiring structure: AlSi/TiN: (500
/100 thickness) It is not necessary to perform the heating heat treatment immediately after the cooling step. Almost the same effect can be obtained even if it is applied after patterning.

実施例2 第4図は半導体素子の断面図を用いて示す本発明の素子
製造工程である。実施例1では膜形成後引き続いて基板
の冷却処理を施したがこの実施例では配線形成工程の最
後で行っている。
Embodiment 2 FIG. 4 shows the device manufacturing process of the present invention using a cross-sectional view of a semiconductor device. In Example 1, the substrate was cooled after the film was formed, but in this example, it was performed at the end of the wiring forming process.

実施例1と同様に通常の半導体素子製造工程により能動
部分を形成した半導体基板10上に絶縁膜20を形成し
た後、配線層を形成する。11は所定のマスクにより選
択的におこなったイオンインプランテーシゴンと引き続
いておこなった熱処理によって形成した高濃度のP型も
しくはN型拡散領域である。配線はAl層30とW層4
oとからなる。拡散領域11表面に形成されている薄い
酸化膜をフッ酸を含む水溶液で除去する。通常のマグネ
トロンスパッタ法で膜厚1100nのW膜4oを形成し
、引き続き500nmのAlSi膜30膜形0する。通
常のフォトエツチングプロセスを用いて配線の形状に加
工し、表面を酸化Si。
As in Example 1, an insulating film 20 is formed on a semiconductor substrate 10 on which an active part is formed by a normal semiconductor device manufacturing process, and then a wiring layer is formed. Reference numeral 11 denotes a highly concentrated P-type or N-type diffusion region formed by ion implantation selectively performed using a predetermined mask and subsequent heat treatment. The wiring is Al layer 30 and W layer 4
It consists of o. The thin oxide film formed on the surface of the diffusion region 11 is removed with an aqueous solution containing hydrofluoric acid. A W film 4o with a thickness of 1100 nm is formed by the usual magnetron sputtering method, and then an AlSi film 30 with a thickness of 500 nm is formed. It is processed into a wiring shape using a normal photo-etching process, and the surface is made of Si oxide.

もしくは窒化Si等Alと同等以上の機械的強さ(例え
ば、弾性率)を持つ絶縁膜50で覆う(第4図a)。
Alternatively, it is covered with an insulating film 50 such as Si nitride having a mechanical strength (eg, elastic modulus) equal to or higher than that of Al (FIG. 4a).

この状態の基板を摂氏零度以下に冷却してAl層30に
歪を導入する。Si基板、および酸化Sl、窒化S1に
比べAlの熱膨張率が太きく (SiO2の線膨張率〜
Q 、 35 p p m/’C15iNの線膨張率〜
5Ppm/°C)、またSi基板がAlに比べて桁違い
に厚いため(Si基板の厚さはほぼ500μm)、冷却
時の両者の収縮量の差はほとんどすべてAl層に歪とし
て導入される。実施例1と同様に、第2図に示す装置を
用いて、0°Cから一200℃の間の冷却温度に基板を
約10分保持する。この状態でAlの結晶はほとんど粒
成長しておらず、粒径は100〜500nm程度であり
、Al中には多量の歪が導入されている(第4図b)。
The substrate in this state is cooled to below zero degrees Celsius to introduce strain into the Al layer 30. The coefficient of thermal expansion of Al is larger than that of Si substrate, Sl oxide, and S1 nitride (linear expansion coefficient of SiO2 ~
Q, 35 p p m/' Linear expansion coefficient of C15iN ~
5Ppm/°C), and because the Si substrate is an order of magnitude thicker than Al (the thickness of the Si substrate is approximately 500 μm), almost all of the difference in the amount of shrinkage between the two during cooling is introduced as strain into the Al layer. . As in Example 1, using the apparatus shown in FIG. 2, the substrate is held at a cooling temperature between 0° C. and -200° C. for about 10 minutes. In this state, the Al crystals have hardly grown, and the grain size is about 100 to 500 nm, and a large amount of strain has been introduced into the Al (Fig. 4b).

その後、この装置のヒータパワーを増加させて200℃
〜500℃の熱処理を施す。この処理によってAnの結
晶粒が成長するが、冷却工程を施して歪を導入したAl
では、この処理を施さないものに比べて最終の結晶粒径
が大きくなっている(第4図C)。
After that, increase the heater power of this device to 200℃.
Heat treatment at ~500°C. Although this treatment causes the growth of An crystal grains, Al
In this case, the final crystal grain size is larger than that in the case without this treatment (Fig. 4C).

これらの配線に通電し、エレクトロマイグレーション耐
性を測定した結果を、第3表および第3図に示す。
The results of measuring electromigration resistance by applying current to these wirings are shown in Table 3 and FIG. 3.

第3表 換算配線寿命特性(単位=106秒)配線構造
: A Q S i /W : (500/1100n
厚)従来の通常の処理を施したものでは配線が微細化す
るにつれ急激に配線の信頼度が低下し、特に幅1.0μ
m以下の配線での信頼度低下が著しいが、本発明の処理
を施すと、実施例1と同様に配線が微細化し、幅1.0
μm以下になってもほぼ一定の信頼度を保つことができ
る。
Table 3 Converted wiring life characteristics (unit = 106 seconds) Wiring structure: A Q Si /W : (500/1100n
Thickness) With conventional conventional processing, the reliability of the wiring decreases rapidly as the wiring becomes finer, especially for wires with a width of 1.0 μm.
Although the reliability of wiring with a width of less than
Almost constant reliability can be maintained even at micrometers or less.

冷却工程の保持温度は配線寿命に強い影響を与える。第
3図に見られるように冷却温度が低いほど配線は長寿命
化し、−50℃以下でその効果が明瞭であり、特に−1
00℃以下で顕著である。
The holding temperature during the cooling process has a strong influence on the wiring life. As shown in Figure 3, the lower the cooling temperature, the longer the life of the wiring, and this effect is clear below -50℃, especially at -1
It is noticeable at temperatures below 00°C.

配線の電気抵抗値も本発明の処理を導入することによっ
て増加することはない。
The electrical resistance value of the wiring also does not increase by introducing the treatment of the present invention.

以上、Alを主体とする配線について説明してきたが、
W等の高融点金属を主体としその表面もしくは側面にA
lもしくはAl金合金領域が形成されている配線につい
てもこの方法が有効なことはいうまでもない。
Above, we have explained wiring mainly made of Al, but
Mainly made of high melting point metal such as W, with A on its surface or side.
Needless to say, this method is also effective for wiring in which Al or Al gold alloy regions are formed.

実施例3 第2図に示した図は本発明の処理装置の基本的構成を説
明している。実施例1および実施例2で述べた処理はこ
の第2図の装置を用いて行った。
Embodiment 3 The diagram shown in FIG. 2 explains the basic configuration of a processing device of the present invention. The processes described in Examples 1 and 2 were carried out using the apparatus shown in FIG.

この装置は基板上に薄膜を形成し、同時に冷却と加熱と
の処理を可能にした装置である。基本的に5つの処理室
から構成され、基板は各処理室間で適切に搬送されて順
次処理される。実施例1の場合の基板処理を例にとって
装置の機能と構成を説明する。基板は基板導入室110
にセットされ真空排気されたのち、前処理室120に搬
送される。ここでは、加熱、スパッタ等の基板クリーニ
ング処理を施す。次に基板は成膜室130に搬送され、
所定の条件で被着する。成膜後、基板は熱処理室140
に導入され冷却または加熱の熱処理を施される。−20
0℃までの冷却は液体窒素を利用して実現できる。図中
、ヒータ143と、コンダクタンスフィン室144中の
圧力を圧力調整器141で調整して基板ホルダー145
の温度を所定の温度にする。熱処理完了後基板を取り出
し室150に搬送し一連の処理を終える。
This device forms a thin film on a substrate and is capable of cooling and heating at the same time. It basically consists of five processing chambers, and the substrates are appropriately transported between each processing chamber and sequentially processed. The functions and configuration of the apparatus will be explained by taking the substrate processing in Example 1 as an example. The substrate is placed in the substrate introduction chamber 110.
After being set and evacuated, it is transported to the preprocessing chamber 120. Here, substrate cleaning processing such as heating and sputtering is performed. Next, the substrate is transported to the film forming chamber 130,
Deposits under specified conditions. After film formation, the substrate is placed in a heat treatment chamber 140.
and is subjected to heat treatment by cooling or heating. -20
Cooling down to 0°C can be achieved using liquid nitrogen. In the figure, the pressure in the heater 143 and the conductance fin chamber 144 is adjusted by the pressure regulator 141, and the substrate holder 145 is heated.
temperature to a predetermined temperature. After the heat treatment is completed, the substrate is transferred to the take-out chamber 150 and the series of treatments is completed.

この様に真空を破ることなく連続的に処理できるため、
特にAI2合金の場合、大気中では急速に形成される表
面酸化皮膜の拘束なく結晶粒の成長を促進することがで
きる。このため大気中で処理した場合に比べて最終的に
大きな結晶粒径を得ることができる。
In this way, continuous processing is possible without breaking the vacuum,
Particularly in the case of AI2 alloy, growth of crystal grains can be promoted without being constrained by a surface oxide film that is rapidly formed in the atmosphere. Therefore, it is possible to finally obtain a larger crystal grain size than when processing in the atmosphere.

この図は装置の概念を説明したもので、成膜、冷却、加
熱等の構成は必ずしもここに示したような、スパッタ、
液体窒素冷却、ヒータ加熱である必要はない。
This figure explains the concept of the device, and the configurations for film formation, cooling, heating, etc. are not necessarily the same as those shown here.
It is not necessary to use liquid nitrogen cooling or heater heating.

実施例4 第5図は半導体素子の断面図を用いて示す本発明の素子
製造工程である。実施例1及び2と同様に、通常の半導
体素子製造工程により能動部分を形成した半導体基板1
0上に絶縁膜20を形成した後、配線層を形成する。1
1は所定のマスクにより選択的におこなったイオンイン
プランテーションと引き続いておこなった熱処理によっ
て形成した高濃度のP型もしくはN型拡散領域である。
Embodiment 4 FIG. 5 shows the device manufacturing process of the present invention using a cross-sectional view of a semiconductor device. As in Examples 1 and 2, a semiconductor substrate 1 with active parts formed by a normal semiconductor device manufacturing process.
After forming the insulating film 20 on the wiring layer 0, a wiring layer is formed. 1
Reference numeral 1 denotes a highly concentrated P-type or N-type diffusion region formed by selectively performing ion implantation using a predetermined mask and subsequent heat treatment.

配線はAl層30とW層40.41とからなる。The wiring consists of an Al layer 30 and W layers 40 and 41.

拡散領域11表面に形成されている薄い酸化膜をフッ酸
を含む水溶液で除去する。通常のマグネトロンスパッタ
法で膜厚1100nのW膜40を形成し、引き続き50
0nmのAR8i膜30膜形0後、再度500nmの厚
いW膜41を形成する(第5図a)。
The thin oxide film formed on the surface of the diffusion region 11 is removed with an aqueous solution containing hydrofluoric acid. A W film 40 with a film thickness of 1100 nm is formed by ordinary magnetron sputtering method, and then a W film 40 with a thickness of 50 nm is formed.
After forming the AR8i film 30 with a thickness of 0 nm, a thick W film 41 with a thickness of 500 nm is formed again (FIG. 5a).

この状態の配線層を形成した基板を摂氏零度以下に冷却
してAl層30に歪を導入する。Si基板に比べAlの
熱膨張率が太きく(Siの線膨張率=2.5ppm/℃
、Alの線膨張率=23Ppm/’C)、またSi基板
がAlに比べて桁違いに厚いこと(Si基板の厚さはほ
ぼ500μm)、および表面に設けた厚いW層もAlに
比べて熱膨張率が小さいこと(Wの線膨張率〜5ppm
/℃)のため、冷却時の両者の収縮量の差はほとんどす
べてAl層に歪として導入される。導入する歪量を変え
るため、実施例1及び2と同様に第2図に示す装置を用
いた(第5図b)。
The substrate on which the wiring layer is formed in this state is cooled to below zero degrees Celsius to introduce strain into the Al layer 30. The coefficient of thermal expansion of Al is larger than that of the Si substrate (coefficient of linear expansion of Si = 2.5 ppm/℃
, linear expansion coefficient of Al = 23 Ppm/'C), the Si substrate is an order of magnitude thicker than Al (the thickness of the Si substrate is approximately 500 μm), and the thick W layer provided on the surface is also thicker than Al. The coefficient of thermal expansion is small (coefficient of linear expansion of W ~ 5 ppm)
/°C), almost all of the difference in the amount of shrinkage between the two during cooling is introduced as strain into the Al layer. In order to vary the amount of strain introduced, the apparatus shown in FIG. 2 was used as in Examples 1 and 2 (FIG. 5b).

装置から取りだした後、表面に設けた500nm厚のW
を選択的に除去し、通常の熱処理炉を使って、400℃
で30分間のアニールを水素雰囲気で行った。この処理
によってAlの結晶粒が成長するが、表面に厚いW層を
設けることにより最終の結晶粒径を大きくすることがで
きる。その際このW膜が強い圧縮応力を有する膜である
ほどAlの結晶粒成長の促進効果が強い。熱処理後は電
気抵抗の高い表面W層を除くことにより微細化工の可能
な膜にすることができる(第5図C)。
After taking it out from the device, a 500 nm thick W layer was placed on the surface.
selectively removed and heated to 400°C using a normal heat treatment furnace.
Annealing was performed for 30 minutes in a hydrogen atmosphere. Although Al crystal grains grow through this treatment, the final crystal grain size can be increased by providing a thick W layer on the surface. At this time, the stronger the compressive stress of this W film, the stronger the effect of promoting Al crystal grain growth. After heat treatment, by removing the surface W layer with high electrical resistance, the film can be made into a film that can be microprocessed (FIG. 5C).

ついで通常のフォトエツチングプロセスを用いて配線の
形状に加工し、表面を絶縁膜5oで覆った後、外部接続
部のみ絶縁膜を除去する(第5図d)。
Next, it is processed into a wiring shape using a normal photoetching process, and after covering the surface with an insulating film 5o, the insulating film is removed only at the external connection portion (FIG. 5d).

これらの配線に通電し、エレクトロマイグレーション耐
性を測定した結果を、第4表に示す。
Table 4 shows the results of measuring electromigration resistance by applying electricity to these wirings.

従来の通常の処理を施したものでは配線が微細化するに
つれ急激に配線の信頼度が低下し、特に幅1.0μm以
下の配線での信頼度低下が著しいが、本発明の処理を施
すと、配線が微細化し、幅1.0μm以下になってもほ
ぼ一定の信頼度を保つことができる。同じように冷却処
理を施す場合でも、表面に厚いW層を設けた場合は更に
効果が著しい。
With conventional conventional processing, the reliability of the interconnects decreases rapidly as the interconnects become finer, and the decrease in reliability is particularly significant for interconnects with a width of 1.0 μm or less, but with the treatment of the present invention, Even when the wiring becomes finer and the width becomes less than 1.0 μm, almost constant reliability can be maintained. Even when cooling treatment is performed in the same way, the effect is even more significant when a thick W layer is provided on the surface.

第4表 換算配線寿命特性(単位=106秒)配線構造
: A Q S i /W(500/1100n厚)以
上説明してきた方法は、Al金合金種類や表面に設ける
材料の種類によらない。すなわち、Al層が純Alであ
っても、Cu、Si等を高々数%含む合金であってもよ
く、表面層材料は、W。
Table 4 Converted wiring life characteristics (unit = 106 seconds) Wiring structure: A Q S i /W (500/1100n thickness) The method described above does not depend on the type of Al-gold alloy or the type of material provided on the surface. That is, the Al layer may be pure Al or may be an alloy containing at most several percent of Cu, Si, etc., and the surface layer material may be W.

Mo、Tiやこれらの合金(たとえば、W−10wt%
Ti) 、化合物(たとえば、T i N)のどれであ
っても、また酸化S1.窒化Si等の絶縁膜であっても
同程度の効果が得られる。
Mo, Ti and alloys thereof (for example, W-10wt%
Ti), compounds (e.g. T i N), and oxidized S1. The same effect can be obtained even with an insulating film such as Si nitride.

さらに表面層材料が同一材料のAl金合金あっても構わ
ない。この場合についての例を次に説明する。
Furthermore, the surface layer material may be an Al-gold alloy of the same material. An example of this case will be described next.

実施例5 第6図は半導体素子の断面図を用いて示す本発明の素子
製造工程である。実施例4と同様に、通常の半導体素子
製造工程により能動部分を形成した半導体基板10上に
絶縁膜2oを形成した後、配線層を形成する。配線はA
l層30とW層40とからなる。
Embodiment 5 FIG. 6 shows the device manufacturing process of the present invention using a cross-sectional view of a semiconductor device. As in Example 4, after an insulating film 2o is formed on a semiconductor substrate 10 on which an active part is formed by a normal semiconductor device manufacturing process, a wiring layer is formed. Wiring is A
It consists of an L layer 30 and a W layer 40.

スパッタ法で膜厚30nmのW膜40を形成し、引き続
き900nmのAΩSiΩSi膜形0する(第6図a)
。 この状態の、配線層を形成した基板を摂氏零度以下
に冷却してAl層30に歪を導入する。導入する歪量を
変えるため、実施例1及び2と同様に第2図に示す装置
を用いた(第6図b)。10分間所定の温度に冷却した
後、この装置のヒータパワーを増加させて200°C〜
500℃の熱処理を施す。この処理によってAlの結晶
粒が成長する(第6図C)。装置から取りだした後、A
lS1層30層表0から一様にエツチングし、所定の厚
さ(今の場合300nm)まで膜厚を減らしたA(ls
i層30aを形成する(第6図d)。この工程ではAn
の結晶粒は変化しないため、最終的に結晶粒が大きく成
長し、かつ微細加工に適した薄膜を得ることができる。
A 30 nm thick W film 40 is formed by sputtering, followed by a 900 nm AΩSiΩSi film (Fig. 6a).
. In this state, the substrate on which the wiring layer is formed is cooled to below zero degrees Celsius to introduce strain into the Al layer 30. In order to vary the amount of strain introduced, the apparatus shown in FIG. 2 was used as in Examples 1 and 2 (FIG. 6b). After cooling to the desired temperature for 10 minutes, increase the heater power of this device to 200°C~
Heat treatment is performed at 500°C. This treatment causes Al crystal grains to grow (FIG. 6C). After taking it out from the device, A
lS1 layer 30 layers A (ls
An i-layer 30a is formed (FIG. 6d). In this process, An
Since the crystal grains do not change, the crystal grains eventually grow larger and a thin film suitable for microfabrication can be obtained.

電子線照射露光法を使ったレジストプロセスを用いて微
細な配線の形状に加工し、表面を絶縁膜50で覆った後
、外部接続部のみ絶縁膜を除去する(第6図e)。
After processing into a fine wiring shape using a resist process using an electron beam irradiation exposure method and covering the surface with an insulating film 50, the insulating film is removed only at the external connection portion (FIG. 6e).

これらの配線に通電し、エレクトロマイグレーション耐
性を測定した結果を、第5表に示す。なお、この表には
、最初からAIJSi層の膜厚を300nmに形成し、
同一の熱処理を施すが、膜厚を減らすエツチング処理だ
けを省いたものを、比較のためにのせた。
Table 5 shows the results of measuring electromigration resistance by applying electricity to these wirings. Note that this table shows that the thickness of the AIJSi layer is 300 nm from the beginning,
For comparison, a sample was subjected to the same heat treatment, but only the etching process to reduce the film thickness was omitted.

従来の通常の処理を施したものでは配線が微細化するに
つれ急激に配線の信頼度が低下する。実施例1〜4で説
明してきた方法を用いることによって、信頼度を回復で
きるが、幅や厚さが0.5μm以下の配線では必ずしも
十分とはいえない。
In the case of conventional conventional processing, the reliability of the wiring rapidly decreases as the wiring becomes finer. Reliability can be restored by using the methods described in Examples 1 to 4, but this is not necessarily sufficient for wiring with a width and thickness of 0.5 μm or less.

しかしこの方法を使うことにより、配線寿命にして2〜
3倍程度長寿命化できる効果がある。
However, by using this method, the wiring life is 2~2~
It has the effect of extending the lifespan by about three times.

第5表 換算配線寿命特性(単位:106秒)配線構造
: A n S i /W(300/30nm厚)実施
例6 本実施例を実施例5の第6図を用いて説明する。
Table 5 Converted wiring life characteristics (unit: 106 seconds) Wiring structure: A n S i /W (300/30 nm thickness) Example 6 This example will be explained using FIG. 6 of Example 5.

実施例5と同様に、通常の半導体素子製造工程により能
動部分を形成した半導体基板10上に絶縁膜20を形成
した後、配線層を形成する。配線はAl、層30とW層
40とからなる。
As in Example 5, after an insulating film 20 is formed on a semiconductor substrate 10 on which an active part is formed by a normal semiconductor device manufacturing process, a wiring layer is formed. The wiring consists of an Al layer 30 and a W layer 40.

スパッタ法で膜厚30nmのW膜40を形成し、引き続
き900nmのAlSi膜30膜形0する(第6図a)
。この状態の、配線層を形成した基板を、直径が1μm
以下の氷の微粒子をけん濁させたアルコール中に保持し
容器を通じて超音波を印加する。氷の微粒子は膜表面に
衝突し膜中には歪が導入される(第6図b)。歪量を適
正にするために氷粒子の径や超音波のパワー、印加時間
等を調整する必要がある。装置から取りだした後、通常
の熱処理炉を使って、400℃−30分のアニールを水
素雰囲気で行った。この処理によってAlの結晶粒が成
長する(第6図C)。引き続きAfiSi層30を層面
0ら一様にエツチングし、所定の厚さ(今の場合300
nm)まで膜厚を減らしたAJISi層30a層形0a
る(第6図d)。
A W film 40 with a thickness of 30 nm is formed by sputtering, and then an AlSi film 30 with a thickness of 900 nm is formed (FIG. 6a).
. In this state, the substrate with the wiring layer formed thereon has a diameter of 1 μm.
The following ice particles are held in suspended alcohol and ultrasonic waves are applied through the container. The ice particles collide with the film surface and introduce strain into the film (Figure 6b). In order to make the amount of strain appropriate, it is necessary to adjust the diameter of the ice particles, the power of the ultrasonic waves, the application time, etc. After taking it out from the apparatus, it was annealed at 400° C. for 30 minutes in a hydrogen atmosphere using a normal heat treatment furnace. This treatment causes Al crystal grains to grow (FIG. 6C). Subsequently, the AfiSi layer 30 is uniformly etched from layer surface 0 to a predetermined thickness (in this case, 300 mm).
AJISi layer 30a layer type 0a with film thickness reduced to nm)
(Figure 6d).

この工程ではAlの結晶粒は変化しないため、最終的に
結晶粒が大きく成長し、かつ微細加工に適した薄膜を得
ることができる。
Since the Al crystal grains do not change in this step, the crystal grains eventually grow to a large size and a thin film suitable for microfabrication can be obtained.

電子線照射露光法を使ったレジストプロセスを用いて微
細な配線の形状に加工し、表面を絶縁膜50で覆った後
、外部接続部のみ絶縁膜を除去する(第6図e)。
After processing into a fine wiring shape using a resist process using an electron beam irradiation exposure method and covering the surface with an insulating film 50, the insulating film is removed only at the external connection portion (FIG. 6e).

これらの配線に通電し、エレクトロマイグレーシゴン耐
性を測定した結果、はぼ第5表に示した実施例5と同程
度の長寿命化が達成できた。
As a result of energizing these wirings and measuring their resistance to electromigration, it was possible to achieve a long life comparable to that of Example 5 shown in Table 5.

なお、最初からAlSi層の膜厚を300nmに形成し
、同一の歪導入処理を施しても同程度の長寿命化が可能
である。ただ、その際は、歪導入処理により表面起伏が
激しくなるのをできるだけ抑制するよう最適化された条
件で実施する必要がある。
Note that even if the AlSi layer is formed to have a thickness of 300 nm from the beginning and the same strain introduction treatment is performed, the same level of longevity can be achieved. However, in this case, it is necessary to carry out the process under optimized conditions so as to suppress as much as possible the increase in surface undulation due to the strain introduction process.

また、歪導入の除用いた微粒子も氷に限らない。Furthermore, the fine particles used to introduce strain are not limited to ice.

常温で、Alを化学的に侵さないものであれば利用可能
である。ただし処理終了後、基板上から完全に除去でき
るためには、氷やアルコール等、常温で液体状のものが
望ましい。この微粒子も液体中にけん濁して用いる必要
はなく、気体中もしくは真空中で微粒子を基板表面に向
かって射出させてもよい。さらに、この場合は、熱処理
と歪の導入を同時に行うことが可能であるが、その際も
同等の効果が得られることは言うまでもない。
Any material that does not chemically attack Al at room temperature can be used. However, in order to be able to completely remove it from the substrate after processing, it is preferable to use something that is liquid at room temperature, such as ice or alcohol. These fine particles need not be suspended in a liquid and may be injected toward the substrate surface in a gas or vacuum. Further, in this case, it is possible to perform the heat treatment and the introduction of strain at the same time, and it goes without saying that the same effect can be obtained in that case as well.

さらに、AnSi層表面に設け、歪導入後除去する層を
十分厚くすれば、ローリング(圧延)等による歪導入も
可能である。
Furthermore, if the layer provided on the surface of the AnSi layer and removed after strain introduction is made sufficiently thick, strain introduction by rolling or the like is also possible.

【発明の効果1 以上説明したように本発明によれば、微細化によるAf
lマイグレーション配線性能の劣化を抑制でき、配線の
高信頼化を実現できる。
Effect of the invention 1 As explained above, according to the present invention, Af
l Deterioration of migration wiring performance can be suppressed and high reliability of wiring can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1.2.4.5.6図は本発明の実施例の配線構造形
成工程を示す素子断面図、第3図は本発明の実施例の配
線膜の寿命試験結果を示す特性図である。 符号の説明 10・・・Si基板、 11・・・高濃度不純物拡散領
域(N+またはP十)、20・・・Si酸化膜等絶縁膜
、  30,30a−Al合金配線、またはAl領領域
40,41・・・W層、 50・・・絶縁膜、 51・
・・開口部、 110・・・基板装着室、111・・・
基板ホルダー  110a=110e=一基板、120
・・・前処理室、121・・・RF電源、 122・・
・電極、130−・・成膜室、  131・DC電源、
132・・・ターゲット、 140・・・熱処理室、1
41・・・圧力調整器、 142・・・液体窒素、14
3・・・ヒータ、 144・・・コンダクタンスフィン
145・・・基板ホルダー 150・・・基板取り出し室151・・・〃 閉 (す) (C) 図 第1の (’d) 垢 図 /DO 〉や即過度じO) 第テ1 (d) (し) (C) (b) (0ン
Fig. 1.2.4.5.6 is a cross-sectional view of an element showing the process of forming a wiring structure according to an embodiment of the present invention, and Fig. 3 is a characteristic diagram showing the life test results of a wiring film according to an embodiment of the present invention. . Description of symbols 10...Si substrate, 11...High concentration impurity diffusion region (N+ or P10), 20...Insulating film such as Si oxide film, 30, 30a-Al alloy wiring or Al region 40 , 41... W layer, 50... Insulating film, 51...
...opening, 110...board mounting chamber, 111...
Substrate holder 110a=110e=one substrate, 120
...Pretreatment chamber, 121...RF power supply, 122...
・Electrode, 130-・Film forming chamber, 131・DC power supply,
132...Target, 140...Heat treatment chamber, 1
41...Pressure regulator, 142...Liquid nitrogen, 14
3...Heater, 144...Conductance fin 145...Substrate holder 150...Substrate removal chamber 151...Closed (C) Figure 1 ('d) or immediate pressure O) Step 1 (d) (shi) (C) (b) (0 n

Claims (1)

【特許請求の範囲】 1、基板上に形成される薄膜配線の形成法で、膜形成後
、制御して膜中に歪を導入する工程と、上記工程と同時
もしくはそれ以後に施される加熱工程とを含むことを特
徴とする薄膜配線形成方法。 2、制御した膜中への歪の導入が、基板上に膜を形成し
た後、 (1)摂氏零度以下に冷却すること、 (2)適切に加速された、原子、イオン、もしくは微粒
子を膜面に打ちつけること、 (3)圧延等の機械加工を施すことの、いずれかの方法
で行われることを特徴とする請求項1記載の薄膜配線形
成方法。 3、上記薄膜配線は、純AlもしくはAl合金を主成分
とする層を設けて形成することを特徴とする請求項1も
しくは2記載の薄膜配線形成方法。 4、上記薄膜配線は、純AlもしくはAl合金と、高融
点材料とを積層して形成することを特徴とする請求項1
もしくは2記載の薄膜配線形成方法。 5、上記高融点材料に、WまたはMoまたはTiもしく
はこれらを主成分とするTiW等の合金、もしくはTi
N等の化合物を用いたことを特徴とする請求項4記載の
薄膜配線形成方法。 6、上記冷却温度が−50℃以下であり、その後の加熱
温度が300℃以上であることを特徴とする請求項2な
いし5のいずれかに記載の薄膜配線形成方法。 7、上記冷却工程が配線のパターニング前、もしくは配
線を絶縁膜で被覆した後であることを特徴とする請求項
2ないし5のいずれかに記載の薄膜配線形成方法。 8、基板上に膜を形成する機構、基板を摂氏零度以下に
冷却する機構、基板を300℃以上に加熱する機構、お
よびこれらの機構間で必要に応じて基板を搬送する機構
を有してなることを特徴とする、基板処理装置。 9、基板上に形成される薄膜配線が半導体装置用薄膜配
線であるところ請求項1ないし7記載の薄膜配線形成方
法。 10、基板上に形成される薄膜配線の形成法で、制御し
て膜中に歪を導入する工程と、同時もしくはそれ以後に
施される加熱工程と、歪が導入された薄膜の表面に設け
た異種もしくは同種の材料の一部又は全部を除去する工
程を含むことを特徴とする薄膜配線形成方法。
[Claims] 1. A method for forming thin film wiring formed on a substrate, which includes a step of controlling and introducing strain into the film after film formation, and heating performed at the same time as or after the above step. A thin film wiring forming method characterized by comprising the steps of: 2. The controlled introduction of strain into the film is achieved by: (1) cooling it below zero degrees Celsius after forming the film on the substrate; (2) introducing appropriately accelerated atoms, ions, or microparticles into the film; 2. The thin film wiring forming method according to claim 1, wherein the thin film wiring forming method is carried out by one of the following methods: (3) machining such as rolling. 3. The thin film wiring forming method according to claim 1 or 2, wherein the thin film wiring is formed by providing a layer containing pure Al or an Al alloy as a main component. 4. Claim 1, wherein the thin film wiring is formed by laminating pure Al or an Al alloy and a high melting point material.
Or the thin film wiring forming method described in 2. 5. W, Mo, Ti, alloys such as TiW containing these as main components, or Ti
5. The thin film wiring forming method according to claim 4, wherein a compound such as N is used. 6. The thin film wiring forming method according to any one of claims 2 to 5, wherein the cooling temperature is -50°C or lower, and the subsequent heating temperature is 300°C or higher. 7. The thin film wiring forming method according to claim 2, wherein the cooling step is performed before patterning the wiring or after covering the wiring with an insulating film. 8. It has a mechanism for forming a film on the substrate, a mechanism for cooling the substrate to below zero degrees Celsius, a mechanism for heating the substrate to 300 degrees Celsius or higher, and a mechanism for transporting the substrate between these mechanisms as necessary. A substrate processing apparatus characterized by: 9. The thin film wiring forming method according to any one of claims 1 to 7, wherein the thin film wiring formed on the substrate is a thin film wiring for a semiconductor device. 10. A method for forming thin film wiring formed on a substrate, which includes a step of controlling and introducing strain into the film, a heating step performed at the same time or after that, and a heating step applied to the surface of the thin film into which strain has been introduced. 1. A method for forming thin film wiring, comprising a step of removing part or all of different or similar materials.
JP11000290A 1990-04-27 1990-04-27 Formation of thin film wiring and manufacturing device Pending JPH0410541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11000290A JPH0410541A (en) 1990-04-27 1990-04-27 Formation of thin film wiring and manufacturing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11000290A JPH0410541A (en) 1990-04-27 1990-04-27 Formation of thin film wiring and manufacturing device

Publications (1)

Publication Number Publication Date
JPH0410541A true JPH0410541A (en) 1992-01-14

Family

ID=14524612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11000290A Pending JPH0410541A (en) 1990-04-27 1990-04-27 Formation of thin film wiring and manufacturing device

Country Status (1)

Country Link
JP (1) JPH0410541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187247A (en) * 2013-03-25 2014-10-02 Fujitsu Ltd Process of manufacturing electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014187247A (en) * 2013-03-25 2014-10-02 Fujitsu Ltd Process of manufacturing electronic device

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