JPH04104521A - Phase lock loop - Google Patents

Abstract

PURPOSE:To shorten the time required for phase matching by storing information of the phase difference detected by phase comparison between an output signal and an input signal in a buffer in each phase difference detection period and reading this information from the buffer in the following phase difference non-detection period to stop clocks in a certain proportion. CONSTITUTION:A phase difference signal whose one period consists of the phase difference detection period and the phase difference non-detection period is outputted by a phase comparing circuit 1 which detects the phase difference between the input signal and the output signal. A buffer 4 is provided, and phase difference information is stored in the phase difference detection period of the phase difference signal and is read out in the following phase difference non-detection period, and the stop of clocks of a clock generator 2 is controlled in a certain proportion based on this information. Phase difference information is expressed with the number of clocks. Thus, the play time on the control is eliminated to considerably quickly match the phases because the phase difference reduction control dependent upon the clock stop in the certain proportion is performed without being limited to the phase difference detection period like a conventional system.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a phase synchronized circuit that outputs a signal whose phase is synchronized with an input signal.

The purpose is to shorten the time required for phase matching.

It has a clock generator, an output signal generation circuit that generates an output signal based on the clock, and a phase comparison circuit that detects a phase difference between the input signal and the output signal.

By controlling the clock generator during the phase difference detection period.

A buffer is provided for storing information on the phase difference detected during the phase difference detection period in a phase synchronization circuit that reduces the phase of the output signal in clock units at a constant rate during the phase difference detection period to achieve phase alignment.

During a period other than the phase difference detection period, refer to the phase difference information stored in the buffer.

The clock generator is controlled to control the phase of the output signal from the output signal generation circuit during periods other than the one phase difference detection period.
The configuration is such that the control to reduce the clock unit at a constant rate is continued until the phase difference is eliminated.

[Industrial application field]

The present invention relates to a phase-locked circuit that outputs a signal whose phase is synchronized with an input signal, and particularly to a phase-locked circuit that reduces the time required for phase synchronization.

In conventional phase synchronization circuits, the period in which the phase difference between the input signal and the output signal can be corrected is limited to the period in which a phase difference is detected between the input signal and the output signal and a phase difference signal is generated. In the present invention, the effective period during which the phase difference can be substantially corrected is extended to the period after the phase difference signal, so that phase synchronization control can be performed in a short time.

[Conventional technology]

FIG. 9 shows the basic configuration of a conventional phase-locked circuit.

FIG. 1O shows its operation timing diagram. In Figure 9, 1
2 is a phase comparison circuit that detects a phase difference between an input signal and an output signal, 2 is a clock generator that generates a clock, and 3 is an output signal generation circuit that generates an output signal.

The output signal generation circuit 3 is composed of a counter, and divides the frequency of the clock generated by the clock generator 2 to generate an output signal.

The phase comparator circuit 1 compares the phases of an input signal and an output signal and outputs one phase difference signal. (a) and (b) in Figure 10,
(C) shows an example of two output signals and two input signals and two phase difference signals.

The phase comparison is performed from the fall of the output signal to the fall of the input signal, and is called a two-phase difference detection period. On the other hand, the period from the fall of the input signal to the fall of the output signal is called a non-phase difference detection period.

The combined period of this phase difference detection period and the non-phase difference detection period constitutes one period of the phase difference signal.

When this phase difference signal is applied to the clock generator 2 shown in FIG. 9, the clock generator 2 stops the clock during the phase difference detection period shown in FIG. is delayed and synchronized to the input signal.

However, if there is a limit to the time width in which the clock can be stopped for some reason, the clock generator 2
Rather than completely stopping the clock during the phase difference detection period, a clock is generated that is stopped at a certain rate, for example, one clock every 10 clocks, as in the example shown in FIG. One phase adjustment is performed by delaying the phase of the output signal by a predetermined percentage every cycle and gradually reducing the phase difference over a long period of time.

An example of such a case is D with a three-phase synchronized signal.
- RAM may be controlled. Since the D-RAM must be refreshed at regular intervals, the control signal cannot be left unnecessarily stopped for a long time.

For example, in the case of IMbit D-RAM, at least 8
If the output signal generation circuit is designed such that 512 refreshes must be performed during 8ms, and therefore there are no clock stops and 1024 refreshes can be performed during 8ms, then the clock
It can be stopped once at a time.

[Problem to be solved by the invention]

In a conventional phase synchronization circuit, one phase adjustment is performed because the clock supplied to the output signal generation circuit is stopped at a constant rate only during the phase difference detection period of each phase difference signal output from the one phase comparator circuit. There was a problem in that it took a long time to complete.

An object of the present invention is to shorten the time required for phase alignment compared to the conventional art when stopping the clock at a constant rate in each cycle of nine phase difference signals.

[Means to solve the problem]

In order to solve the above problems, the present invention utilizes a non-phase difference detection period, which was conventionally not used for phase adjustment control by stopping the clock at a constant rate, as a phase adjustment control period in each period of one phase difference signal. This increases the effective control period and, as a result, shortens the time required for phase alignment.

As a means for this purpose, information on the phase difference detected by phase comparison between the output signal and the input signal in each period of one phase difference signal is stored in a buffer during each phase difference detection period, and the information is stored in a buffer during the subsequent non-phase difference detection period. The clock is stopped at a constant rate by reading the phase difference information from the buffer.

FIG. 1 shows the basic configuration of a phase-locked circuit according to the present invention.

In fig.

2 is a phase comparison circuit that detects a phase difference between an input signal and an output signal, and outputs a phase difference signal in which one cycle consists of a phase difference detection period and a non-phase difference detection period.

Reference numeral 2 denotes a clock generator, which generates a complete clock or stops the clock at a constant rate, depending on the size of the phase difference detection period of the two phase difference signals.

Reference numeral 3 denotes an output signal generation circuit which divides the frequency of the clock generated by the clock generator 2 to generate an output signal.

Reference numeral 4 denotes a buffer provided according to the present invention, which stores the magnitude of the phase difference signal as phase difference information during the phase difference detection period, reads it out during the following non-phase difference detection period, and adjusts the clock of the clock generator 2 based on this. control the stoppage of the system at a fixed rate. Phase difference information is expressed by the number of clocks.

[For production]

The operation of the circuit of the present invention shown in FIG. 1 will be explained using the operation timing diagram shown in FIG.

(a) in Figure 2 is the output signal waveform, and (a) in Figure 2 is the input signal waveform.0 Between the output signal and the input signal shown in the figure, a state in which the phase of the output signal leads occurs ing.

(C) in FIG. 2 is a phase difference signal output from the phase comparator circuit 1 in FIG. 1, and the phase difference detection period therein indicates the phase lead state of the output signal.

FIG. 2(d) shows the operation of setting and referring to the phase difference information in the buffer 4 of FIG. Each operation corresponds to a phase difference detection period and a non-phase difference detection period of one phase difference signal (C).

(el in FIG. 2 indicates a phase correction operation based on clock stop in the clock generator 2 of FIG. 1).

During the phase difference detection period of the phase difference signal (C), the phase difference signal output from the phase comparator circuit 1 of FIG. 1 is directly used to control the clock generator 2 to stop, thereby reducing the two phase differences. At this time, phase difference information is set for the buffer 4 in parallel.

Further, during the non-phase difference detection period of the phase difference signal (C), phase difference information is read from the buffer 4, and the clock stop control of the clock generator 2 is performed based on this.

Reduce phase difference.

In this way, the correction operation is performed over the entire period until the phase difference between the output signal and the input signal becomes zero.

〔Example〕

One embodiment of the present invention will be explained with reference to FIGS. 3 to 8.

Figure 3 is an example circuit diagram of a phase comparison circuit, Figure 4 is an example circuit diagram of a clock generator, Figure 5 is an example circuit diagram of a buffer, and Figure 6 is an example circuit diagram of an output signal generation circuit. , 7th
The figure is an operation timing diagram of an embodiment of the phase comparison circuit, and FIG. 8 is an operation timing diagram of an embodiment of the clock generator.

The illustrated embodiment is described as one in which a horizontal synchronizing signal NTSCHsync in an NTSC television signal is used as an input signal, and an output signal Hsync out phase-synchronized therewith is extracted, and a clock of 50 MH2 is used.

The phase comparison circuit shown in FIG. 3 is composed of a NAND gate 5.6 and a flip-flop D-FF7.

D-FF is a flip-flop that maintains the state during one phase difference detection period and the non-phase difference detection period.

The NAND gates 5 and 6 are as shown in FIG.

When the input signal χNTSCHsync is at H level, the output signal χT (when sync~out goes to L level, the output goes to H level)
SDLY is set to H level, set to D-FF, and one phase difference signal H3DLY is set to H level to start a phase difference detection period. After that, the input signal *NTS in Figure 7
When CHsync changes to L level, H3DLY goes to L level.
level, and the phase difference signal H3DLY output from the primary D-FF is set to L level to end the phase difference detection period and start a non-phase difference detection period. This operation is repeated thereafter.

The clock generator in Figure 4 is a two-man OR gate 8.2.
Human powered NAND gate 9.4bit power lid 10.3
Human-powered NAND gate 11. It is composed of D-FF12.

The clock generator in FIG. 4 generates a phase difference signal D HS output from the phase comparator circuit in FIG. 3 during one phase difference detection period.
Phase difference information NOT AJUST output from the buffer in FIG. 5, which will be described later, during the DLY or non-phase difference detection period.
(indicating that synchronization is not yet achieved) is input, generates a clock CLK that is controlled to stop a certain percentage of clocks according to the phase difference, and supplies it to the output signal generation circuit shown in Figure 6, which will be described later. do.

When the 4-bit counter IO in FIG. 4 is in the enabled (EN) state by the output of the NAND gate 9,
As shown in the operation timing in Figure 8, 50MHz is
MHz, 12.5MHz, 6.25MHz, and 12.5MHz is the clock CL.
It is output as K.

Also at this time, 25MHz, 12.5MHz, 6.25MHz
Match the MHz using NAND gate 11, and get 12.5
Instruction signal P CLK 5TOPPULS to stop 50 MHz by 1 pulse for 2 MHz CLK pulses
' is generated and D-FF12 is set.

The output of D-FFl 2 is *CLK 5TOP PU
LS and CLK 5TOP PULS, which are input to the buffer shown in FIG. CLK 5T shown in Figure 8
When OP PULS becomes H level, the output of NAND gate 9 in FIG. The counter is stopped by one pulse and the CLK output is delayed.

The buffer in Figure 5 is a three-man NAND gate 13.1
4.2 manual AND gate 15 4bit up /d
It consists of an own counter 16 and an OR gate 17 operated by four people.

When the NAND gate 13 or the NAND gate 14 detects a match based on the H level of each 3-man power +u
p/down counter 16 is enabled and 5
Count 0MHz pulses.

The up/down of the up/doien counter 16 is D
It is controlled depending on whether H3DLY is at H level or L level.

When DHS DLY is at H level, that is, during the phase difference detection period in FIG. 7, up/down counter 1
6 performs an up count, and in the NAND gate 14, the inverse of the carry output of the counter *Carry and D
HS DLY, Thu CLK 5TOP PUL
up/down during the period of phase difference, which is the period when S coincides with
The n counter 16 is enabled to count the number of 50 MHz pulses corresponding to the magnitude of 9 phase differences.

When DHS DLY changes to L level, that is, to the non-phase difference detection period in FIG. 7, + up/down counter 1
6 performs a down count operation, and the NAND gate 13
In, NOT AJUST, Book D H3DLY
, CLK 5TOP PULS (7) Enable the Uρ/down counter 16 during the period when each H level matches, and count down from the count value set in the preceding phase difference detection period using a 50 MHz pulse.

Each 4-bit output of the up/do@n counter 16 is
ORed by OR gate 17, 1 phase difference information N0TAJ
Produces UST. NOT AJUST.

It shows H level until the counter value reaches "O".

At NAND gate 13, CLK 5TOPPU
A match occurs every time LS goes to H level = up/
The down counter 16 is caused to perform a down count operation.

In this way, the up/down counter 16 stores the count value corresponding to the phase difference in the 9 phase difference detection period (D HS DLY="H"), and stores the count value corresponding to the phase difference in the 9 phase difference detection period (D
When SDLY="L"), the count is down each time clock stop control is performed.

Is the count value “0”, that is, phase alignment is complete?

The phase difference detection period (DHS DLY="H"/
down until the tree D HS DLY='L")
Continue counting.

The above operation is repeated until the output signal H5sync out is synchronized with the input signal NTSCHsync.

The output signal generation circuit shown in FIG. 6 is composed of a simple n-bit counter 18, and outputs a carry every time a certain number of clocks CLK output from the clock generator shown in FIG. 4 are counted. NTSCHs shown
Outputs H5yncout with the same duty as ync.

〔Effect of the invention〕

According to the present invention, the phase difference reduction control by stopping the clock at a fixed rate can be performed without being limited to the phase difference detection period as in the conventional method, so there is no idle time in control, and one phase It is possible to significantly speed up the adjustment.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is an operation timing diagram of the present invention, FIG. 3 is a circuit diagram of a phase comparator circuit according to an embodiment of the present invention, and FIG. 4 is a clock generation diagram according to an embodiment of the present invention. 5 is a circuit diagram of a buffer according to an embodiment of the present invention, FIG. 6 is a circuit diagram of an output signal generation circuit according to an embodiment of the present invention, and FIG. 7 is an operation of a phase comparator circuit according to an embodiment of the present invention. Timing diagram: FIG. 8 is an operation timing diagram of the clock generator according to the embodiment of the present invention, FIG. 9 is a basic configuration diagram of a conventional phase-locked circuit, and FIG. 10 is an operation timing of the conventional phase-locked circuit shown in FIG. 11 are explanatory diagrams of clock stop control. In Figure 1. 1: Phase comparison circuit 2: Clock generator 3: Output signal generation circuit 4: Buffer

Claims (1)

[Scope of Claims] A clock generator, an output signal generation circuit that generates an output signal based on the clock, and a phase comparison circuit that detects a phase difference between an input signal and an output signal, and includes a phase difference detection period. In a phase synchronization circuit that controls a clock generator to reduce the phase of an output signal to clock units at a constant rate during the detection period of the above phase difference and performs phase matching, the phase difference detected during the detection period of the above phase difference is A buffer for storing phase difference information is provided, and during a period other than the phase difference detection period, the clock generator is controlled by referring to the phase difference information stored in the buffer, and the phase difference is detected. Even during a period other than the period, control for reducing the phase of the output signal from the output signal generation circuit in clock units at a constant rate is continued until the phase difference is eliminated. synchronous circuit.