JPH04102290A - Fifo memory device - Google Patents

Fifo memory device

Info

Publication number
JPH04102290A
JPH04102290A JP2218612A JP21861290A JPH04102290A JP H04102290 A JPH04102290 A JP H04102290A JP 2218612 A JP2218612 A JP 2218612A JP 21861290 A JP21861290 A JP 21861290A JP H04102290 A JPH04102290 A JP H04102290A
Authority
JP
Japan
Prior art keywords
value
write
counter
reset signal
initial value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2218612A
Other languages
Japanese (ja)
Inventor
Kiyoyuki Kohiyama
Hidenaga Takahashi
Yukio Otobe
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2218612A priority Critical patent/JPH04102290A/en
Publication of JPH04102290A publication Critical patent/JPH04102290A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a discontinuous picture displayed as a sub picture by setting a value set as an initial value at a write side counter when a read reset signal is supplied to a read side counter as the initial value of the counter.
CONSTITUTION: As the initial value of the write side counter 15, the output value of an arithmetic means 20 i.e. a value in which a constant value is subtracted from the value of a read address being outputted from a counter 17 at that time is set as the initial value when a write reset signal is supplied, and also, a value held with a holding means 21 i.e. a value set on the write side counter 15 as the initial value previously is set as the initial value when a read reset signal is supplied. Therefore, the write reset signal and the read reset signal are supplied repeatedly at every field, and no passing between the readout and the write of image data occurs even when continuous write on a continuous field also with continuous readout on the continuous field is performed.
COPYRIGHT: (C)1992,JPO&Japio
JP2218612A 1990-08-20 1990-08-20 Fifo memory device Pending JPH04102290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2218612A JPH04102290A (en) 1990-08-20 1990-08-20 Fifo memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2218612A JPH04102290A (en) 1990-08-20 1990-08-20 Fifo memory device

Publications (1)

Publication Number Publication Date
JPH04102290A true JPH04102290A (en) 1992-04-03

Family

ID=16722686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2218612A Pending JPH04102290A (en) 1990-08-20 1990-08-20 Fifo memory device

Country Status (1)

Country Link
JP (1) JPH04102290A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010009094A (en) * 2008-06-24 2010-01-14 Fanuc Ltd Numerical control device having function of superimposing moving pulse used for high-speed cycle processing and nc program instruction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010009094A (en) * 2008-06-24 2010-01-14 Fanuc Ltd Numerical control device having function of superimposing moving pulse used for high-speed cycle processing and nc program instruction

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