JPH04100022A - Liquid crystal display device and its driving method - Google Patents

Abstract

PURPOSE:To reduce variance in the plane of the best common potential by setting the peripheral edge length mum of the capacity part of each complete holding capacity element to less than a specific multiple of the value obtained by dividing the area mum<2> of the capacity part by the diagonal length inches of an area where the picture elements of a thin film transistor drive type liquid crystal display device are arranged. CONSTITUTION:The line width of the common electrode signal line 303 of an intersection part 523 is set normally less than the line width at the capacity part 310. At the intersection part 523, for example, an amorphous Si layer 311 for short probability reduction is arranged between the common electrode signal line 303 and a video signal line 302. Further, a transfer electrode 323 is provided in order to connect transparent picture element electrodes 309 above and below an intersection step so that the breaking of the transparent picture element electrodes 30 due to the step formed at an end part of the common electrode signal line 303 is evaded. The relation between the area 5, peripheral edge length L of the complete holding capacity element 310 and the diagonal length D of the area satisfy an inequality I. Consequently, variance in capacity value due to element size variance is a little and such a defect as an afterimage and deterioration of liquid crystal is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device, and more particularly to the structure of a thin film transistor driven liquid crystal display device.

[Conventional technology]

Conventionally, thin film transistors (T
hin Film Transistor (hereinafter referred to as TFT)
A thin-film transistor-driven liquid crystal display device using a thin film transistor (abbreviated as ) is well known. This display device uses TPT provided on a transparent substrate such as glass to control the voltage applied to the liquid crystal of each pixel, so it is characterized by clear image quality and is suitable for terminals for office automation equipment. It is becoming widely used in TVs and other applications. These applications require a large screen of 10 inches or more from the viewpoint of workability. Furthermore, in order to clearly display characters and figures, it has become necessary to reduce the size of one pixel and increase the definition.

FIG. 11 shows an equivalent circuit of one pixel. A TPT 510 is arranged at the intersection of the scanning signal line 511 and the video signal line 512 with a gate electrode connected to the scanning signal line 511, and a liquid crystal capacitor 513 and a complete storage capacitor 514 are connected to the drain/source electrodes of the TFT 510. There is. When the TFT 510 is turned on by the signal from the scanning signal line 511, the potential of the video signal line 512 is written into the pixel electrode section 515, and charges are accumulated in the liquid crystal capacitor 513 and the complete storage capacitor 514. When the TFT 510 is turned off, the charges accumulated in the liquid crystal capacitor 513 and the complete storage capacitor 514 are held. Since liquid crystal deteriorates when a DC voltage is applied, the above writing and holding are performed alternately in positive and negative polarities with respect to the potential of the common electrode signal line 516. However, the potential of the pixel electrode section 515 changes due to capacitive coupling due to the parasitic capacitance Cgs 517 between the scanning signal line 511 and the pixel electrode section 515, which causes a potential fluctuation (jump voltage) that is synchronized with the fluctuation of the scanning signal. The potential of the signal line 516 is adjusted to a potential (optimum common potential) that makes the DC voltage component applied to the liquid crystal less than a permissible value.

Here, the permissible value of the DC voltage component applied to the liquid crystal varies depending on the liquid crystal material, but is approximately 200 mV for most materials. The voltage Vrms effectively applied to the liquid crystal capacitor 513 is determined by time-averaging the potential difference between the potential written and held in the pixel electrode portion 515 and the potential of the common electrode signal line 516 in this manner. The alignment state of the liquid crystal is determined by this effective voltage Vrms, and the light transmittance of the liquid crystal is controlled. Here, if the capacitance value of the complete storage capacitor 514 is made sufficiently larger than the parasitic capacitance fcgs 517, the fluctuation in the potential of the pixel electrode portion 515, that is, the jump voltage can be reduced. Furthermore, the reduction in accumulated charge due to leakage current from TFT Slo, the liquid crystal capacitor 513, etc. is suppressed, and fluctuations in the effective voltage Vrms are reduced. In addition, the complete holding capacity 51
The signal amplitude of the video signal line 512 can be reduced by driving the signal of the common electrode signal line 516, which is one electrode of the liquid crystal capacitor 513 and the video signal line 513, in an alternating current manner in synchronization with the signal of the video signal line 512. The pulse width (1/2 of one cycle) of this AC drive is usually set to be the same as the selection time of one scanning signal line. Because of the advantages described above, the complete storage capacitor 514 has become essential for pixels of thin film transistor driven liquid crystal display devices. An example of this type of device is the one disclosed in Japanese Patent Publication No. 2-10955.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration various conditions that must be satisfied by a complete storage capacity, particularly conditions that become important when increasing the screen size and high definition of a liquid crystal display device.

When the screen size of a liquid crystal display device is increased, it becomes difficult to make the processed shape of elements on a substrate uniform within the plane, and variations in element dimensions within the plane increase.

For example, in a case of 10 inches, a variation of about ±1.5 μm occurs. For this reason, in an element such as a perfect storage capacitor, in which the capacitance value is proportional to the element area, there is a problem that variations in the capacitance value tend to occur as the screen size increases. In particular, as the size of one pixel becomes smaller due to higher definition, and the area of a complete storage capacitor becomes smaller, the influence of variations becomes more noticeable. Furthermore, it is also susceptible to variations due to misalignment between two layers during device processing. Such variations in capacitance value within the display surface cause variations in the optimal common potential within the display surface, which causes excessive DC voltage to be applied to parts of the liquid crystal within the display surface, resulting in defects such as afterimages and deterioration of the liquid crystal. cause. Therefore, it has become necessary to reduce such in-plane variations in element dimensions and variations in capacitance values due to misalignment.

Furthermore, when a liquid crystal display device has a larger screen and higher definition, the number of pixel scanning signal lines (horizontal) and video signal lines (vertical) (the number of pixel repetitions) increases. The scanning period from the top scanning signal line to the bottom scanning signal line on the screen has a maximum value of about 1/6o second, which is not perceivable as flickering to the human eye, so the number of scanning signal lines is As the number increases, the selection time per line becomes shorter. For example, when forming a liquid crystal display device with 780 scanning signal lines and 3360 video signal lines on a 10-inch substrate, the selection time per scanning signal line is as short as about 20 μs. The pulse width of the drive signal for the video signal line and the common electrode signal line is approximately 20 μS since it is the same as the selection time for one scanning signal line, and is AC driven at a high frequency of about 25 kHz. For this reason, pixel characteristics such as writing and holding are likely to be affected by timing shifts, rounding, and noise of the drive waveform, and defects such as variations in the optimal common potential and threshold values are likely to occur. In particular, since the waveform of the common electrode signal line influences the potential of the pixel electrode portion, it has been necessary to appropriately set the motion method. Furthermore, as described above, the driving circuits for the common electrode signal line and the video signal line must be AC driven at a high frequency, which requires a high-speed driving IC and increases power consumption.

Furthermore, as the size of one pixel becomes smaller due to higher definition, the spacing between patterns becomes smaller, making short circuits between wires and watermarks more likely to occur at element step portions. In particular, in the case of a configuration in which the common electrode signal line is formed in the same plane as the scanning signal line, the number of wires per pixel is large, so the probability of short circuits between the wires and watermarks at the element step portions is high. increases. Therefore, there has been a need for a method of configuring the common electrode signal line in which these defects are less likely to occur.

Furthermore, as the size of one pixel decreases due to high definition, the thin film transistor part and the complete storage capacitor part, which do not transmit light and become a display part, become larger relative to the pixel, resulting in noticeable discontinuity in the display part. These parts cause the resolution to deteriorate.

A first object of the present invention is to provide a configuration of a perfect storage capacitor element suitable for reducing in-plane variations in optimal common potential.

A second object of the present invention is to provide a method for driving a complete storage capacitor element suitable for reducing fluctuations in the optimum common potential and fluctuations in the threshold value.

A third object of the present invention is to provide a structure of a complete storage capacitor element suitable for reducing short-circuits and water marks between wiring lines and improving yield.

A fourth object of the present invention is to provide a structure of a complete storage capacitor element suitable for avoiding discontinuity in the display section and deterioration of resolution.

[Means to solve the problem]

In order to achieve the configuration of a perfect storage capacitor element suitable for reducing the in-plane variation of the optimum common potential in the above-mentioned problem, a gate is connected to the first wiring forming the scanning signal line and the first wiring. a thin film transistor to which an electrode is connected; a second wiring connected to one of the drain/source electrodes of the thin film transistor to form a video signal line; and one electrode connected to the other of the drain/source electrodes of the thin film transistor. a liquid crystal capacitor element having one electrode connected to the other of the drain/source electrodes of the thin film transistor; a third electrode connected to the other electrode of the complete retention capacitor element; In a thin film transistor driven liquid crystal display device comprising a plurality of pixels each including a fourth electrode connected to the other electrode of the liquid crystal capacitive element and substantially connected to the third electrode, The value obtained by dividing the peripheral length μm of the capacitive part of the storage capacitor element by the area μth2 of the capacitive part by the diagonal length of the area where the pixels of the display part of the thin film transistor driven liquid crystal display device are arranged. The third and fourth electrodes are connected to a common electrode signal line. moreover,
The ends of the capacitive part of the complete retention capacitor element are terminated in the upper and lower directions and the left and right sides only by one end of the electrode of the complete retention capacitor element.

In addition, in order to achieve the third problem mentioned above, which is a perfect storage capacitor structure suitable for reducing short circuits and water marks between wiring lines and improving yield, the vertical width of the common electrode signal line is completely reduced. The area of the storage capacitor element is divided by the horizontal width of the transparent pixel electrode. It is placed almost in the center.

In addition, in order to achieve the fourth problem described above, which is a configuration of a complete storage capacitor element suitable for avoiding discontinuity in the display part and deterioration of resolution, the thin film transistor part and the complete storage capacitor element part are as follows: As a result, the width of the portion that does not transmit light and does not become a display portion is made almost the same. Further, the thin film transistor section that does not become a display section and the complete storage capacitor element are separated and arranged at approximately the same interval.

In addition, in order to achieve the second problem described above, which is a method of driving a perfect storage capacitor element suitable for reducing fluctuations in the optimal common potential and fluctuations in the threshold value, the signal on the common electrode signal line is transferred to the video signal line. The phase was shifted (made asynchronous) with respect to the signal. In other words, the timing at which the potential of the common electrode signal line starts to change is determined by the delay time from the one scanning signal line selection time to the delay time of the video signal line with respect to the scanning signal line, and the timing at which the potential of the video signal line starts to change. This is a delay within the range of less than the maximum delay time of the signal line and greater than zero. In addition, the pulse width of the common electrode signal line (1/1 period
2) is set to n times the one scanning signal line selection time.

Here, n is a divisor of the scanning signal lines.

[Effect]

The peripheral length μm of the capacitive part of the complete retention capacitor element is the value obtained by dividing the area μm2 of the complete retention capacitor element by the diagonal length in inches of the area in which the pixels of the display part of the thin film transistor dynamic type liquid crystal display device are arranged. If the value is set to 1.33 times or less, the variation in the area of the perfect storage capacitor due to dimensional variation, that is, the variation in capacitance value, will be ±20% of the center value.
It can be kept below. If the variation in the capacitance value of the perfect storage capacitor element is ±20% or less, the in-plane variation in the optimum common potential can be suppressed to 200 mV or less, so that defects such as afterimages and deterioration of the liquid crystal will not occur. Further, the capacitive part of the complete retention capacitor element has a quadrilateral shape, and one two sides of the quadrilateral that are opposite to each other coincide with both ends of one electrode forming the complete retention capacitor element, and the opposing sides Since the other two sides are both ends of the other electrode forming the perfect storage capacitor, the area of the perfect storage capacitor does not change even if misalignment occurs between the patterns forming each electrode.

Therefore, the capacitance value of the perfect storage capacitor element does not vary, and defects such as afterimages and deterioration of the liquid crystal do not occur.

Also, the timing at which the potential of the common electrode signal line starts to change is compared to the timing at which the potential of the video signal line starts to change.
If the delay is within the range of zero or more and less than the time obtained by subtracting the delay time of the video signal line with respect to the scanning signal line and the maximum delay time of the common electrode signal line from the 1 scanning signal line selection time, the common electrode signal line and In addition to reaching the desired value for the source electrode potential difference, during holding, after the source potential has finished changing due to jump, the source electrode potential changes corresponding to the potential change of the common electrode signal line. No fluctuations in the optimal common potential or thresholds occur. In particular, if the timing at which the potential of the common electrode signal line starts to change is set to approximately the center of the range and delayed within the above range, the margin will be maximized both during writing and holding, so the source potential such as timing deviation will be reduced. No fluctuations in the optimal common potential or thresholds due to modulation occur. In addition, within the range, in particular, the timing at which the potential of the common electrode signal line starts to change is determined by the scanning signal of the potential of the video signal line from one scanning signal line selection time to the timing at which the potential of the video signal line starts to change. If a high voltage is applied to the liquid crystal by delaying it by a time approximately equal to the time delay for the potential of the line and the maximum delay time of the common electrode signal line (black display in normally white mode, normally black display The potential difference between the source and drain electrodes when holding the white display) is reduced, and
Since the potential difference between the common electrode signal line and the source or drain electrode is reduced, the leakage current between the source and drain electrodes of the TPT and the leakage current due to the common electrode signal line parasitic MO5 are reduced, and the retention characteristics are improved. Furthermore, if the pulse width of the common electrode signal line (172 of one cycle) is made n times the one scanning signal line selection time, the frequency of the AC signal of the common electrode signal line becomes 17n, so the current consumption of the drive circuit is small. Become. Furthermore, even if the common electrode signal line has a period n times, the pulse width of the video signal line (172 of one period) is the same as one scanning signal line selection time, but the polarity becomes positive and negative for every n. The signal on the video signal line often has a small gradation difference between adjacent pixels due to frame thinning, etc., and if the cycle is set to n times, the polarity of adjacent pixels will often be the same, so the frequency will essentially become low. , the current consumption of the video signal line drive circuit is also reduced.

Also, if the vertical width of the common electrode signal line is the dimension obtained by dividing the area of the complete storage capacitor element by the horizontal width of the transparent pixel electrode, then the scanning signal line and the common electrode in the same plane Since the signal line spacing is at its maximum value, short circuits between wiring lines are less likely to occur. Furthermore, if the connection part between the full retention capacitors of the common electrode signal line is placed approximately in the vertical center of the left and right ends of the full retention capacitor, the length of the valley due to the step of the common electrode signal line will be short. Liquids used in the manufacturing process, such as etching liquid, are less likely to stagnate, so defects such as water marks are less likely to occur.

Furthermore, the width of the portion of the thin film transistor section through which light does not pass and which does not become a display section and the width of the portion of the complete storage capacitor section where no light passes through and does not become a display section are almost the same, so discontinuity in the display section is noticeable. It becomes difficult.

In addition, if the thin film transistor part that does not become a display part and the complete storage capacitor part are separated and arranged at approximately uniform intervals, the width of the part that does not become a display part becomes smaller on average, which reduces the discontinuity of the display part. becomes less noticeable.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the following description, first, the planar structure, cross-sectional structure, manufacturing method, etc. of the liquid crystal display section of the active matrix liquid crystal display device to which the present invention is applied will be explained, and then the particularly detailed contents of the present invention will be explained. An example of the configuration and a driving method of a complete storage capacitor element that provides the following will be described, and finally, an example of the overall configuration of a liquid crystal display device will be described.

FIG. 2 shows one pixel of a liquid crystal display section of an active matrix type liquid crystal display device according to an embodiment of the present invention, and FIG. 3 shows a main part of a liquid crystal display section in which a plurality of pixels are arranged. Further, FIG. 6B shows a cross section of the liquid crystal display device taken along the line VIB--VIB in FIG. 2.

As shown in FIG. 6B, in the liquid crystal display device of this embodiment, a pixel having a TFT 304 and a transparent pixel electrode 309 is formed on the inner surface (liquid crystal side) of the lower transparent glass substrate 400. or.

A color filter 451 is provided on the inner surface (liquid crystal side) of the upper transparent glass substrate 403. A liquid crystal 450 is sealed between these upper and lower transparent glass substrates.

The thickness of the lower and upper transparent glass substrates 400 and 403 is:
For example, it is about 1.1 (mm).

2 and 3 are both plan views of the lower transparent glass substrate 400 seen from the inside (liquid crystal side), and only the patterns on the lower transparent glass substrate 400 are shown. Each pixel is located at an intersection area (4 (in the area surrounded by and on the signal lines). The scanning signal lines 301 extend in the row direction, and a plurality of scanning signal lines 301 are arranged in the column direction. The video signal lines 302 extend in the column direction, and a plurality of video signal lines 302 are arranged in the row direction. Further, a common electrode signal line 303 is provided between each scanning signal line 301.
01 in the row direction, and a plurality of them are arranged in the column direction.

Note that these signal lines are respectively connected to drive circuits around the liquid crystal display section. That is, each scanning signal line 30
1 is connected to the terminal portion on the transparent glass substrate at the tip extending in the row direction, for example, the left end, and each terminal is connected to the terminal portion on the transparent glass substrate.
It is connected to each output section of the scanning signal drive circuit in the semiconductor substrate on the TAB. Each video signal line 302 is drawn out alternately at the ends extending in the column direction, that is, the upper end and the lower end, and is connected to a terminal section, respectively.Furthermore, each terminal is connected to the TAB, and is connected to the TAB. It is connected to each output section of the video signal drive circuit within the semiconductor substrate. Further, the common electrode signal line 303 is connected to a common electrode at its end extending in the row direction, for example, at the right end, and this common electrode is connected to a terminal section, and furthermore, this terminal section is connected to a flexible printed circuit (FPC). ) and to the output of the common electrode drive circuit.

As shown in FIG. 2, one TFT 304 is arranged for each pixel. Since the TFT 304 mainly forms part of the gate electrode 301 (scanning signal line 301),
), insulating film, amorphous Si semiconductor 30
6. Consists of a pair of source electrode 307 and drain electrode 308 6. Note that the source and drain are originally determined by the bias polarity between them, and in this display device, the polarity is reversed during operation, so the source and drain are I would like it to be understood that they will be replaced. However, in the following explanation, for convenience, one side is fixedly expressed as a source and the other side is fixedly expressed as a drain.

As shown in FIG. 2, in the pixel of the present invention, the TFT 304
is arranged on the scanning signal line 301 below the pixel, and this scanning signal line 301 serves as the gate electrode of the TFT 304. Furthermore, the channel direction of the TFT 304 (the direction in which current flows between the source and drain) is arranged parallel to the direction of the video signal line 302. Source electrode 30
7 is arranged above the TFT 304 in the drawing, and its end is connected to the transparent pixel electrode 309. drain electrode 3
08 is arranged below the TFT 304 in the drawing and is connected to the video signal line 302 on the left side of the pixel. That is, in this embodiment, the pixels are controlled by the lower scanning signal line 301 and the left video signal line 302. The ratio of the channel length L (distance between the source and drain electrodes) and the channel width W of the TFT 304, that is, the mutual conductance gm
The factor W/L for determining is set to approximately 3 in this embodiment. This value is the frame frequency, the number of scanning signal lines, T
It is set in consideration of PT mobility, liquid crystal capacitance value, complete retention capacitance value, etc., as well as dimensional shift during processing.

The common electrode signal lR303 is arranged between the scanning signal lines 301. Common electrode signal line 303 and scanning signal line 301
The distance between them is almost uniform.

Two adjacent scanning signal lines 301 and two adjacent video signals #! A rectangular transparent pixel electrode 309 is arranged in the area surrounded by 302, and a complete storage capacitor 310 is formed at the intersection of the common electrode signal line 303 and the transparent pixel electrode 309. W/L of TFT 304, source electrode 307
The capacitance value of the complete storage capacitive element 310 required per pixel is determined by the overlap capacitance (Cgs) of the scanning signal line 3°1, etc., and the area of the complete storage capacitive element 310 is determined from the capacitance value per unit area of the insulating film. It is determined. In this embodiment, the complete storage capacitor 310 has a rectangular shape, and the left-right direction (
The width of the transparent pixel electrode 309 in the left and right direction in the figure (same below) is the width of the transparent pixel electrode 309.
The width in the vertical direction (vertical direction in the figure, the same applies hereinafter) is determined from this width.

A crossing electrode 323 is provided on the transparent pixel 309. The crossing electrode 323 is, for example.

The transparent pixel electrode 309 is formed of the same layer as the source/drain electrode, and electrically connects the transparent pixel electrode 309 in a portion overlapping with the common electrode signal 4!303 and a portion not overlapping with the common electrode signal 4!303. This prevents display defects due to disconnection of the transparent pixel electrode 309 at the stepped portion of the common electrode signal line 303. A portion of the transparent pixel electrode 309 that does not intersect with the common electrode signal line 303 forms a liquid crystal capacitive element.

The amorphous Si semiconductor 30 of the TFT 304 is placed at the intersection of the scanning signal line 301 and the common electrode signal line 303 with the video signal line 302 in order to reduce short circuits between these signal lines.
Amorphous Si semiconductors 305, 311 consisting of the same layer as 6
is provided.

The transparent pixel electrode 309 is connected to the video signal line 302. Amorphous Si
The area is set to be as large as possible without shorting with the semiconductors 305, 311, the drain electrode 308, etc. A light shielding layer 3 is provided at the end of the transparent pixel electrode 309 on the video signal line 302 side.
12,313° and 314.315° are provided to partially prevent light leakage from the periphery of the transparent pixel electrode 309.

The transparent pixel electrode 309 has the same potential as the source electrode 307, and the potential of the video signal line 302 is written to the transparent pixel electrode 309 and the potential of the transparent pixel electrode 309 is held when the TFT 304 is turned on.

It is controlled by OFF.

The pixels having the configuration shown in FIG. 2 are arranged in the row direction and the column direction with a repeating pitch of the horizontal dimension 316 and the vertical dimension 317 of the pixels, as shown in FIG. 3. Opposing the lower transparent glass substrate formed in this way,
A top transparent glass substrate is provided.

FIG. 4 shows a color filter pattern of a transparent glass substrate that is a main part of a liquid crystal display section in which a plurality of pixels are arranged. In FIG. 4, in order to clarify the positional relationship between the pixel pattern on the lower transparent glass substrate and the color filter pattern, the frames of the horizontal dimension 316 and vertical dimension 317 of the pixel are shown with broken lines. The color filter pattern in FIG. 4 is a plan view of the upper transparent glass substrate viewed from the back side (opposite side of the liquid crystal). As is clear from FIG. 4, the color filter is arranged for each pixel at a position facing the pixel and is dyed differently.

That is, the color filter 451, like the pixel,
It is formed in an intersection area between two adjacent scanning signal lines and two adjacent video signal lines.

On the inner surface (liquid crystal side) of the upper transparent glass substrate, patterns of a light shielding layer 318, a red filter layer (R) 319, a green filter layer (G) 320, and a blue filter layer (B) 321 are formed. A common transparent electrode 453 is provided over the entire surface of the liquid crystal display section. Red filter layer (
The patterns of R) 319, green filter layer (G) 320, and blue filter layer (B) 321 extend in the column direction, and are arranged in the order of R2O and B in the row direction. That is, the color of the filter is a single color in the column direction.

In this way, the color filter has a vertical stripe arrangement structure.

FIG. 5 shows the pixel pattern on the lower transparent glass substrate and the color filter pattern on the upper transparent glass substrate at the same time. In the liquid crystal display device of the present invention,
A multicolor display is performed by mixing the colors of the R, G, and B pixels arranged side by side. In other words, three pixels arranged horizontally make up one display unit (one dot).
322 is configured. The horizontal and vertical dimensions of one dot 322 are set to be approximately the same. Therefore, the horizontal dimension 316 of one pixel is set to approximately one third of the vertical dimension 317.

A desired number of dots having the structure described above are arranged to form a liquid crystal display section. There is a light source (backlight) on the back of the lower transparent glass substrate of the liquid crystal display (opposite the liquid crystal).
is installed. The voltage (effective value of AC voltage) between the transparent pixel electrode 309 of the pixel on the lower transparent glass substrate and the common transparent electrode 453 on the upper transparent glass substrate is applied to the liquid crystal 450 between the upper and lower glass substrates. Display is performed by changing the alignment state of the liquid crystal and changing the light transmittance of the backlight. In order to increase the definition of a liquid crystal display device, the size of one dot is set small.

For example, high definition can be achieved by setting the size of one side of one dot to about 0.3 am.

Next, the cross-sectional structure and manufacturing method of the liquid crystal display device of the present invention will be explained.

As shown in the cross-sectional structure of FIG. 6B, each pixel (7
) The TFT 304 mainly includes a gate electrode 301, a gate insulator 412, and an i-type (intrinsic).

It is composed of an amorphous 81 semiconductor layer 306 (not doped with conductive type impurities), a pair of source electrodes 307 and a drain electrode 308.

The gate electrode 301 is made of an aluminum film with a thickness of 1100
It is formed with a film thickness of about n. This gate electrode 301 is S
so as to completely cover the i-semiconductor layer 306 (as seen from below)
It is formed with a larger grain. Therefore, when a backlight such as a fluorescent lamp is attached below the lower transparent glass substrate 400, the opaque gate electrode 301 forms a shadow and the Si semiconductor layer 306 is not illuminated by the backlight.

A conductive phenomenon, that is, deterioration of the off-characteristics of the TFT 304 due to light irradiation is less likely to occur. Considering only the function of gate and light shielding, the gate electrode 301 and its wiring may be integrally formed in a single layer, and in this case, the opaque conductive material is A1 containing Si or pure Al. , and AI containing pd can be selected.

The gate insulating film 412 of the TFT 304 is connected to the gate electrode 30.
1 and the scanning signal line 301. The gate insulating film 412 is formed using, for example, a silicon nitride film formed by plasma CVD, and has a thickness of about 300 nm. Further, the gate insulating film has a so-called two-layer gate insulating film structure in which the gate electrode, for example, an aluminum film is partially turned into alumina by anodization and used as an alumina gate insulating film 416. This alumina gate insulating film 416 is formed between the gate electrode 301 and upper layer wiring portions, such as the video signal line and the drain and source electrodes 308.
, 307 also serves to prevent short circuits with the metal films used for the metal films. A plan view of the manufacturing process described above is shown in FIG.

The Si half-I1 body layer 306 is formed of an amorphous silicon film or a polycrystalline silicon film, and is formed to have a thickness of about 180 nm. This Si semiconductor layer 306 is formed continuously with the formation of the silicon nitride gate insulating film 412 by changing the components of the supplied gas in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Further, a phosphorus-doped N layer 413a for ohmic contact is also continuously formed to a thickness of about 40 nm.

Thereafter, the lower transparent glass substrate 400 is taken out of the CVD apparatus, and the Si semiconductor layer 306 is patterned into an island shape using photolithography. A plan view of the manufacturing process described above is shown in FIG.

The transparent pixel electrode 309 uses a transparent conductive film (IT○: Nesa film) formed by sputtering, and has a thickness of 120 nm to 2
It is formed with a film thickness of 00 nm.

Thereafter, each pixel is patterned using photolithography technology. A plan view of the manufacturing process described above is shown in FIG.

The source electrode 307 and the drain electrode 308 are each formed by overlapping a first conductive film A and a second conductive film B from the bottom in contact with the N-thin conductor layer 413a. The first conductive film A and the second conductive film B of the source electrode 307 and the drain electrode 308 are each manufactured in the same process. A chromium film formed by sputtering was used as the first conductive film A, and was formed with a thickness of 50 nm to 1100 nm. If the chromium film is made thicker than necessary, stress will increase, so
The film is formed to a thickness not exceeding 0 nm.

The chromium film has good contact with the N-sensitivity conductor layer 413a. The chromium film prevents aluminum of the second conductive film B, which will be described later, from diffusing into the N-sensitivity conductor layer 413a.
This forms a so-called barrier layer. As the first conductive film A, in addition to chromium, a high melting point metal film (Mo, Ti, Ta, W) is used.
, high melting point metal silicide film (MoSi2.TiSi2.
It may also be formed of TaSi2°WSi2).

The second conductive film B is formed to have a thickness of 300 nm to 400 nm by aluminum sputtering. The aluminum film has less stress than the chromium film, so it can be formed thickly, and the source electrode 307
, the resistance value of the drain electrode 3.8 and the video signal line 302 is reduced. The second conductive film B is TF
It is configured to increase the operating speed of T304 and the signal transmission speed of the video signal line. In other words, the second conductive film B can improve the writing characteristics of pixels. . In addition to the aluminum film, the second conductive film B may be formed of an aluminum film containing silicon (Si) or copper (CU) as an additive. The source electrode 307 and the drain electrode 308, which are composed of the first conductive film A and the second conductive film B, are each patterned by photolithography. At this time, the Nthousand conductor layer 4
13a is partially removed using the photolithographic mask, the first conductive film A, and the second conductive film B as masks.

That is, the portions of the N+ semiconductor layer 413A remaining on the Si semiconductor layer 306 other than the first conductive film A and the second conductive film B are removed by the thickness thereof in a self-aligned manner.

Thereafter, silicon nitride is formed to a thickness of 1 μm on the surface of the lower transparent glass substrate 400 by plasma CVD, terminals and the like are exposed by photolithography, and the entire surface of the pixel is protected with a silicon nitride protective film 417. A plan view of the manufacturing process described above is shown in FIG.

The liquid crystal 450 includes a lower alignment film 418 and an upper alignment film 41 that set the orientation of liquid crystal molecules in a space formed between the lower transparent glass substrate 400 and the upper transparent glass substrate 403.
9 and is enclosed. The lower alignment film 418 is
It is formed on the silicon nitride protective film 417 on the lower transparent glass substrate 400 side.

On the inner surface (liquid crystal side) of the upper glass substrate 403, a color filter 451, an organic protective film 452, a common transparent pixel electrode 453, and the upper alignment film 419 are sequentially laminated. The common transparent pixel electrode 453 is integrally formed with the upper transparent glass substrate 403, facing the transparent pixel electrode 309 provided for each pixel on the lower transparent glass substrate 4°O side. This common transparent pixel electrode 453 is configured to be applied with a common voltage V com.

The color filter 451 is configured by coloring a dyed base material made of a resin material such as acrylic resin with a dye.

The color filter 451 is arranged for each pixel at a position facing the pixel, and is colored differently. color filter 4
51 is formed in a stripe shape between each pixel between two adjacent video signal lines 302. The color filter 451 is formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate 403, and the dyed base material other than the red filter formation area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and a fixing treatment is performed to form the dyed base material. After that, a green filter and a blue filter are sequentially formed.

The organic protective film 452 is provided to prevent the dyes used to dye the color filters 451 into different colors from leaking into the liquid crystal. The organic protective film 452 is made of, for example, a transparent resin material such as acrylic resin or epoxy resin.

This liquid crystal display device is assembled by separately forming the layers on the lower transparent glass substrate 400 and upper transparent glass substrate 403 sides, and then overlapping the upper and lower transparent glass substrates 400 and 403 and sealing liquid crystal between them. It will be done.

Although FIG. 6B shows the cross section of one pixel, FIG.
The figure shows a cross section of the left edge portion of the transparent glass substrates 400 and 403 where external lead wiring is present. 6th
Figure C shows a cross section of the right edge portion of the transparent glass substrates 400 and 403 where no lead wiring is present.

The sealing material 460 shown in each of FIGS. 6A and 6C is configured to encapsulate the liquid crystal 450, and covers the entire periphery of the transparent glass substrates 400 and 403 except for the liquid crystal injection opening (not shown). It is formed along. The sealing material 460 is made of, for example, epoxy resin.

Common transparent pixel electrode 4 on the upper transparent glass substrate 403 side
53 is silver paste 430 in at least one location.
It is connected to an external lead wiring formed on the lower transparent glass substrate 400 side. This external lead wiring is formed in the same process as each of the gate electrode 301, source electrode 307, and drain electrode 308.

The alignment films 418 and 419, the transparent pixel electrode 309, the common transparent pixel electrode 453, etc. are formed inside the sealant 460. Polarizing plates 431A and 431B are formed on the outer surfaces of lower transparent glass substrate 400 and upper transparent glass substrate 403, respectively.

Next, the structure, driving method, etc. of the complete storage capacitor element, which provides particularly detailed content in the present invention, will be explained.

First, some examples of the structure of a perfect storage capacitor element suitable for reducing in-plane variations in the optimum common potential will be shown.

FIG. 1 shows an embodiment for explaining the present invention. An intersection 503 between a first electrode 501, which is a common electrode signal line, and a second electrode 502, which is a transparent pixel electrode and which faces the first electrode 501 via an insulating layer, forms a complete storage capacitor. ing. In the diagram of the complete storage capacitive element, both the upper end 506 and the lower end 507 are terminated at the end of the first electrode 501, and the left end 504 and the right end 505 are both terminated at the end of the second electrode 502.

L<1.33 S/D (
1) Equation (1) characterizes the configuration of the complete storage capacitor element of the present invention. Here, L is the periphery 504. of the capacitive part.
Total length of 505, 506, 507 (unit: μm), S
is the area of the intersection 503, that is, the area of the capacitive element (unit: μm)
”), D indicates the diagonal length (in inches) of the area where pixels of the display section of the thin film transistor driven liquid crystal display device are arranged.

The amount of variation in area of the capacitor section when the element dimensions vary within the display plane is represented by LΔX. Here, △X is the deviation from the average dimension after element processing, that is, the variation (unit: μm)
It shows. Although ΔX depends on the processing technology, it is normally proportional and is expressed as ΔX=aD. According to experiments conducted by the inventors, the proportionality constant a is approximately 0.15.

△X=O, 15D ・・・・・・
(2) Therefore, in a 10-inch display device often used in terminals for office automation equipment, △X is 1.5 μm.
That's about it. When dimensions vary within a plane, the ratio of variation in the area of the capacitor to the area of the capacitive element, that is, the ratio of variation in capacitance value is expressed as LΔX/S. FIG. 12 shows the relationship between the capacitance value of the complete storage capacitor element and the optimum common potential. This curve shows almost the same tendency for commonly used pixel structures including those of the present invention. Jump voltage Vp
is expressed as (3) where the complete storage capacitance Cstg, the parasitic capacitance Cgs between the TFT gate and the source, the liquid crystal capacitance C1c, and the potential difference VgHL between when the scanning signal line (gate) is turned on and when it is turned off. If the capacitance value Cs t g of the perfect storage capacitor element is small, the jump voltage Vp will increase according to the above equation, and the optimal common potential will decrease. Based on the dependence of the optimal common potential on the capacitance value of this complete storage capacitor element, it was discovered that if the rate of capacitance fluctuation is approximately 20% or less, the variation in the optimal common potential can be suppressed to 200 mV or less regardless of the capacitance value. This has been clarified through studies by researchers and others. Therefore, if LΔX/S<0.2 (4), defects such as afterimages and deterioration of the liquid crystal will not occur.

Equation (1) is obtained from Equation (2) and Equation (4).

FIG. 13 shows the relationship between the capacitive part area S and the capacitive part peripheral length. A curve 522 indicates the case where the capacitor is circular, that is, the circumferential length of the capacitor is the minimum, and the circumferential length of the capacitor is a region above this curve.

A straight line 521 shows a case where the inequality sign in equation (1) is replaced with an equality sign, and equation (1) shows a range where the capacitance peripheral length is below the straight line 521. Namely.

The shaded area surrounded by the curve 522 and the straight line 521 is the area of the capacitive part peripheral length where the variation in the optimum common potential can be suppressed to 200 mV or less. As is clear from equation (1), the longer the diagonal length of the display section, the smaller the slope of the straight line 521.
This shaded area becomes narrower. Further, as can be seen from FIG. 13, if the area of the capacitive part is small, this area becomes narrow. In other words, the larger the screen of the liquid crystal display device becomes, and the smaller the size of one pixel due to the higher definition of the liquid crystal display device, the smaller the area of the capacitor part, the smaller the permissible area of the peripheral length of the capacitor part becomes The shape and dimensions of the capacitive element become important. In particular, the diagonal length of the display section of the liquid crystal display device is 9 inches or more, or the diagonal length of one dot (one display position consisting of three RGB pixels) is 400 μm or less, or the area of one pixel is 30,000 μm. The present invention is important in the following cases.

According to the curve in Fig. 12, if the capacitance value of the perfect storage capacitor element is increased, the variation in the optimum common potential becomes smaller when the capacitance value fluctuates, and even if the rate of capacitance variation is about 20% or more, the optimum common potential becomes smaller. It seems that the variation in potential can be suppressed to 200 mV or less. However, here, it is necessary to consider that the optimum common potential varies depending on the signal potential of the video signal line. That is, if the capacitance value of the complete storage capacitor element is too small, the difference in jump voltage depending on the potential of the video signal wiring becomes significant, so that the optimum common potential varies greatly depending on the signal potential. For example, when the voltage applied to the liquid crystal capacitance is small, the jump voltage is larger and the optimum common potential is smaller than when it is large. Therefore, at other in-plane positions to which a signal potential different from the in-plane position where the optimum common potential is appropriately set, a DC voltage is applied, causing defects such as afterimages and deterioration of the liquid crystal. Furthermore, if the capacitance value of the complete storage capacitor element is too large, the degree of writing depending on the potential of the video signal line will change significantly. For example, contrary to the above, when the voltage applied to the liquid crystal capacitor is large, the writing rate is lower on the positive electrode side and the common potential is smaller than when it is small.

This causes fluctuations in the optimum common potential similar to those described above, causing defects such as afterimages and deterioration of the liquid crystal. Therefore, the capacitance value of the complete storage capacitor element needs to be set to an appropriate value. For example, it is effective to set the capacitance value of the complete storage capacitance element to about 3 to 7 times the liquid crystal capacitance value.

FIG. 2 shows an embodiment of the structure of the complete storage capacitor element of the present invention, including other parts of the pixel.

In FIG. 2, one electrode (common electrode signal line) 303 and the other electrode (transparent pixel electrode) 309 of a complete storage capacitor element 310.
are almost orthogonal, and the perfect storage capacitor is almost rectangular. One electrode 303 of the complete storage capacitor 310 is made of a low-resistance metal such as 8β, and constitutes a common electrode portion corresponding to the electrode 516 in FIG. arranged in parallel. Further, the transparent pixel electrode 309 of the complete storage capacitor element 310 is a pixel electrode made of a transparent conductive film such as indium tin oxide (ITQ), and is laminated on the common electrode signal line 303 via an insulating film. Common electrode signal 1I1
Transparent pixel electrode 30 formed in a portion other than above 303
The region 9 is a region through which light passes, and is a portion that becomes an opening. An insulating film made of, for example, a silicon nitride film or a composite film of a silicon nitride film and an AQ203 film obtained by anodizing AΩ is laminated between the common electrode signal line 303 and the transparent pixel electrode 309. Such a membrane structure may be considered to be the same in other embodiments. Transparent pixel electrode 309
The width in the horizontal direction is designed to be the maximum width within a range that does not short-circuit with the adjacent video signal line 302. For this reason, since the complete storage capacitor element is rectangular, the common electrode signal line 3
The vertical width at the complete storage capacitor position 03 is the minimum width with respect to the set area of the complete storage capacitor. Intersection 5 between common electrode signal line 303 and video signal line 302
23, a short circuit between the two is likely to occur, so the crossing area is designed to be as small as possible.

For this reason, the line width of the common electrode signal line 303 at the intersection 523 is usually designed to be thinner than the line width at the capacitor section 310. For example, an amorphous Si layer 311 is formed at the intersection 523 to reduce the probability of short circuit between the common electrode signal line 303 and the video signal line 30.
It is placed between 2.

Further, the crossing electrode 323 is provided for the purpose of connecting the transparent pixel electrodes 309 above and below the step at the intersection in order to avoid disconnection of the transparent pixel electrode 309 due to the step at the end of the common electrode signal line 3°3. Complete storage capacitor element 310 of this embodiment
The relationship between the area and the peripheral length satisfies the relationship of equation (1). Therefore, variations in capacitance values due to variations in element dimensions are slight, and defects such as afterimages and deterioration of the liquid crystal do not occur. Further, since the vertical width of the complete storage capacitor element portion of the common electrode signal line 303 is the minimum width, the distance from the scanning signal line 301 forming the parallel gate electrode can be sufficiently long, and the scanning signal line 301 and The probability that the common electrode signal line 303 will be shorted is tJs. Also, the second @
In the shape of the complete retention capacitor shown in , the upper and lower ends are terminated with one electrode of the complete retention capacitor, and the left and right ends are terminated with the other electrode of the complete retention capacitor. Furthermore, the widths of both electrodes do not change within at least the distance of misalignment of the two electrodes from the end of the intersection of the two electrodes. Therefore, even if there is misalignment, the area of the intersection, that is, the capacitive portion does not change. Therefore, there is no variation in the capacitance value of the perfect storage capacitor due to misalignment, so an excessive DC voltage is not applied locally to the liquid crystal within the display surface.
It does not cause defects such as afterimages or liquid crystal deterioration.

FIG. 14 shows another embodiment of the invention.

Here, only the common electrode signal line 526 and the transparent pixel electrode 527 that constitute the complete storage capacitor element 525 are shown. In this embodiment as well, the relationship between the area and the peripheral length of the complete storage capacitor element 525 satisfies the relationship of equation (1). Furthermore, the widths of these electrodes do not change within a distance of at least the misalignment between the two layers from the intersection of the common electrode signal line 526 and the transparent pixel electrode 527. Therefore, variations in capacitance value due to dimensional variations are slight, and variations in capacitance value of the perfect retention capacitor element due to misalignment do not occur, so defects such as afterimages and deterioration of the liquid crystal do not occur. Further, in this embodiment, the upper and lower ends of the common electrode signal line 526 are not straight lines, and the end faces of the upper and lower ends face in at least three directions.

Therefore, even if the transparent pixel electrode 527 layered thereon is laminated using a method such as sputtering that does not adhere well to the thickness of the stepped portion of the surface to be laminated, the stepped portion of the common electrode signal line 526 will face at least three directions. Therefore, the transparent pixel electrode is sufficiently adhered to the thickness surface at the stepped portion in any of the three directions, making it difficult to break the wire. Concave portion 5 of complete storage capacitor element 525 of this embodiment
28, 529, etc. may be convex portions, and there are no restrictions on their position, size, or shape.As mentioned above, the relationship between the area and the peripheral length satisfies the relationship of the formula in Figure 1, and the upper and lower It goes without saying that the effectiveness is the same as in this embodiment as long as the ends extend in at least three directions.

FIG. 15 shows another embodiment of the invention.

In this embodiment, the upper end 531 and left and right ends 532 and 533 of the complete storage capacitor element 530 are terminated with a transparent pixel electrode 534, and only the lower end 535 is terminated with a common electrode signal line 536. In this embodiment as well, the relationship between the area and the peripheral length of the complete storage capacitor element 530 satisfies the relationship expressed by the formula shown in FIG. Therefore, variations in capacitance value due to dimensional variations are slight, and defects such as afterimages and liquid crystal deterioration do not occur. Further, in this embodiment, since the transparent pixel electrode 534 also terminates at the upper end 531, the display portion is completely formed under the storage capacitor element 530. Therefore, since the complete storage capacitor element 530 does not divide the display section, a decrease in resolution can be avoided. Further, since the portion where the transparent pixel electrode 534 crosses the step of the common electrode signal line 536 is only at one end, disconnection of the transparent pixel electrode 534 is less likely to occur. The configuration of this embodiment is effective not only when the capacitive element is a complete storage capacitive element having the circuit configuration shown in FIG. It is.

Reduction of afterimages and liquid crystal deterioration by the method clarified in the above embodiments can also be achieved by other methods. That is, the parasitic capacitance Cgs between the gate and the source is set to 5% or less of the sum of the complete storage capacitance Cstg and the liquid crystal capacitance C1c. With this setting, the jump voltage is reduced and the dependence of the optimum common potential on the capacitance value of the perfect storage capacitor element is reduced, so it is not necessary to impose restrictions on the shape of the perfect storage capacitor element as shown in FIG.

Next, an embodiment of a method for driving a perfect storage capacitor element suitable for reducing fluctuations in the optimum common potential and fluctuations in the threshold value will be described.

FIG. 16 shows drive waveforms in one embodiment of the present invention. Waveform (a) in Figure 16 is the gate electrode (scanning signal line)
Waveform (b) is the voltage waveform of the drain electrode (video signal line), waveform (c) is the voltage waveform of the common electrode signal line, and waveform (d) is the waveform of the voltage applied to these electrodes. In addition to the dotted line, the waveform of the source electrode voltage is also added as a solid line to show the relative relationship between these waveforms. At time t1, the gate electrode changes from OFF voltage VGL to ○N voltage V
It begins to rise to GH and writing begins. Therefore, the potential of the source electrode also begins to change toward the potential of the drain electrode. The gate electrode reaches VGH at time t2.

At time t2, the drain electrode begins to shift to the desired voltage VDH, and reaches VDH after a certain delay time.

At time t3, the common electrode starts to shift from voltage VC) to voltage VCL, and after delay time tCD of the common electrode, it reaches VCL at time t4.
Reach CL. Writing continues until the potential of the gate electrode begins to shift from the ON voltage VGH to the OFF voltage VGL at time t5, and during this time the potential of the source electrode reaches the desired voltage V.
Reach DH.

From time t4 to time t5 when writing is completed, the source electrode (~drain electrode) has a higher potential than the common electrode, so the drive waveform of this embodiment shows the positive polarity side. At time t5, the desired voltage VDH is applied to the liquid crystal capacitor and the complete storage capacitor.
-VCL is added. The pulse width (172 of one cycle) of the drain electrode voltage and the common electrode voltage is the same as the write time tW (one scanning signal line selection time t5-tl). Time t5
The gate electrode begins to fall from the ○N voltage VGH, and returns to the OFF voltage VGL at time t6 after the gate delay time tGD. During this time, the source electrode drops by the jump voltage Vp due to electrostatic induction. At time t6, the gate electrode becomes OFF, and when the jump is completed, the drain electrode begins to change. At time t7, which is a certain period of time tA after time t6, the common electrode begins to shift from voltage VCL to voltage VCH. At this time, the source electrode also begins to change due to electrostatic induction.

Since the source electrode changes after a predetermined time tA has elapsed after the jump, even if a timing shift occurs in the drive waveform of the common electrode, the waveform of the source electrode is not affected. FIG. 17 shows conventional drive waveforms for reference. The waveforms of the drain electrode and the common electrode are synchronized and start changing at the same time. For this reason, for example, at time t6, at the same time as the jump ends and the source potential finishes falling, the common electrode changes and the source potential begins to rise.

Therefore, the source potential is easily affected by modulation of the drive waveform. The delay time tA of the potential of the common electrode with respect to the potential of the drain electrode is greater than zero (conventional method),
Delay time tG from one scanning signal line selection time tW to the scanning signal line (gate electrode) of the video signal line (drain electrode)
D and the maximum delay time tCD of the common electrode. Note that the potential of the common electrode is actually made slightly lower in order to compensate for the jump voltage and remove the DC component from the voltage applied to the liquid crystal, and is adjusted to the optimum common potential.

FIG. 18 shows an embodiment of the present invention, in particular, when the delay time tA of the potential of the common electrode with respect to the potential of the drain electrode is maximum, that is, the scanning of the video signal line (drain electrode) starts from the one scanning signal line selection time tW. The waveform is shown when the delay time t GD with respect to the signal line (gate electrode) and the maximum delay time t CD of the common electrode are subtracted. In this case, the potential of the common electrode Vc reaches the desired potential at time t5 when writing ends. In this case as well, the source electrode changes after a predetermined time tA has elapsed after the jump, so even if a timing shift occurs in the drive waveform of the common electrode, the waveform of the source electrode is not affected. In addition, in this embodiment, when the positive electrode is held (after writing is completed), the potential difference between the common electrode, drain electrode, and source electrode becomes small, so the parasitic MO5 of the thin film transistor whose gate is the common electrode on the glass substrate on the color filter side Movement is difficult to occur. Therefore, the retention characteristics become stable.

The potential of the drain electrode determines the potential of the source electrode, that is, the transparent pixel electrode of each pixel, and in the case of multicolor display, this potential is divided into several gradations. This grayscale voltage is determined by the dependence of the light transmittance of the liquid crystal on the voltage applied to the liquid crystal. The voltage applied to the liquid crystal is determined by the potential difference between the video signal line and the common electrode signal line, and since the common electrode signal line is common to all pixels, the gray levels can be divided by changing the potential of the video signal line. FIG. 19 is an example of this, in which the potential difference between the video signal line and the common electrode signal line is divided into eight gradations. The potential setting of the video signal line is determined by the voltage of the common electrode signal line. In particular, in FIG. 19, the fourth gray level and below are in phase with the common electrode signal line. In this way, by setting the potential of at least one gradation or more to the same phase as the common electrode signal line, the difference between the gate ON voltage and the writing voltage becomes the same regardless of the gradation, and the video signal potential of the jump voltage dependence on is reduced.

FIG. 20 illustrates drive waveforms in another embodiment of the present invention. In FIG. 20, waveform (a) is the voltage waveform of the gate electrode, waveforms (b), (c), and (d) are waveforms obtained by the conventional driving method, and (b) is the voltage waveform of the drain electrode when the entire brightness is the same. (c) is a common electrode waveform, and (d) is a drain electrode waveform when the luminance differs within the plane. Also,(
e), (f), and (g) are waveforms obtained by the driving method of the present invention, where (e) is the drain electrode waveform when the entire brightness is the same, (f) is the common electrode waveform, and (g) is the in-plane waveform. This is the drain electrode waveform when the brightness is different. In this embodiment, the pulse width of the common electrode is twice the waveform pulse width (one scanning signal line selection time) of the gate electrode. In other words, whereas conventionally, writing was performed in the order of positive polarity, negative polarity, positive polarity, and negative polarity for each scanning signal line, in this embodiment, writing was performed for each scanning signal line in the order of positive polarity, positive polarity, negative polarity, and negative polarity. Write in this order. In this case, the drive frequency is halved, making it possible to reduce the power consumption of the open circuit.

As shown in (e), when the drain electrode has the same brightness over the entire surface, the driving frequency is halved, but since the brightness usually differs within the plane, the driving frequency is the same as the conventional one.

However, especially in the case of high-definition liquid crystal display devices, it is rare for adjacent pixels to have a large difference in gradation, so as shown in the example in (g), the driving frequency is essentially halved, so the driving circuit This enables lower power consumption. In this embodiment, the pulse width of the common electrode is twice the waveform pulse width of the gate electrode (one scanning signal line selection time), but it may be any other value as long as it is a divisor n of the total number of scanning signal lines. Note that the method of this embodiment may be combined with the aforementioned desynchronization of the potential of the common electrode.

Next, an example of the structure of a complete storage capacitor element suitable for reducing short-circuits and water marks between wiring lines and improving yield will be described.

FIG. 21 shows an embodiment of the present invention.

Complete storage capacitor elements 540 and 541 are repeatedly arranged at a pixel pitch in the horizontal direction. The common electrode signal line 542 extends in the horizontal direction and serves as one electrode of the complete storage capacitor element of each pixel. The connection portion 543 between the pixels of the common electrode signal line 542 is thinner than the portion serving as the electrode of the complete storage capacitor element, and is connected to the vertical center position of the left and right ends of the complete storage capacitor element. In addition, the common electrode signal line 54
2 and the scanning signal line electrodes are alternately arranged at substantially the same intervals. Since the connection portion 543 of the common electrode signal line 542 and the like are arranged at the vertical center of the left and right ends of the complete storage capacitor, the valley 5 due to the step of the common electrode signal line 542
The average length of 44,545 is short. Therefore, there is a low probability that liquid for cleaning or etching in the TPT manufacturing process will stay in the recess, and defects due to this are less likely to occur. in this way.

According to the method of arranging a complete storage capacitor element of the present invention, short circuits between wiring lines and water marks are reduced, and yield is improved.

FIG. 22 shows another embodiment of the invention.

The complete storage capacitor elements 546 and 547 are arranged in adjacent pixels so as to be staggered above and below the pixels.

The upper and lower ends of the connection portion 549 of the common electrode signal line 548 are the upper ends of the complete retention capacitor element 546 and the upper end of the complete retention capacitor element 5.
It coincides with the lower end of 47. Therefore, since there is no valley in the connection part 549 due to the step of the common electrode 548,
Retention of etching solution during the TPT process is less likely to occur, and defects due to this are less likely to occur. As described above, according to the method of arranging a complete storage capacitor element of the present invention, watermarks are reduced and yield is improved.

Furthermore, in this embodiment, since the complete storage capacitor elements are arranged vertically and staggered, the aperture is difficult to see divided by the complete storage capacitor elements, and a decrease in resolution can therefore be avoided.

Next, an example of the structure of a perfect storage capacitor element suitable for avoiding discontinuity in the display section and deterioration of resolution will be shown.

FIG. 23 provides a detailed explanation of the invention. In each pixel indicated by the broken line, there is an aperture (portion through which light passes) 5
Only 50, 551, etc. are shown. The aperture is 2 for each pixel.
There are several locations, and these locations, including adjacent pixels, are arranged at approximately equal intervals. In other words, the widths of the thin film transistor section serving as the light shielding section and the complete storage capacitor section are approximately the same.

Therefore, the width of the portion where the display is divided is narrow and the resolution is less likely to deteriorate.

In the above embodiments, the insulating film of the storage capacitor element is a silicon nitride film, or an An20. Although it is a composite membrane with A
AQ20.Q, O, film, silicon oxide film, anodized silicon oxide film and AQ. Any type of composite film, such as a composite film with a Ta anodic oxide film, a composite film of a silicon nitride film and a Ta anodic oxide film, a composite film of a silicon oxide film and a Ta anodic oxide film, or a composite film of three or more layers. The effectiveness of the present invention does not change even with membranes. In addition to AQ, the common electrode signal line is Ta.
, Cr, ITO, or a composite film consisting of at least two layers of these. In particular, ITO
A composite film of ITO and other metals has the advantage that the aperture ratio is improved because ITO is a transparent electrode. However, if a driving method is used in which the potential of the common electrode signal line is varied at the same frequency as the signal potential, the resistance value of the common electrode signal line should be 2Ω or less per pixel to prevent uneven display due to signal delay within the substrate. It is desirable to do so. Therefore, when designing a storage capacitor element, the dimensions of the connection part of the common electrode signal line should be set appropriately taking into account the sheet resistance of the common electrode signal line, so that the resistance value is 1.
Care must be taken to ensure that the resistance is 2Ω or less per pixel.

Furthermore, as the size of one pixel decreases due to higher definition, the aperture, that is, the display area through which light passes, becomes smaller, so care must be taken regarding its shape. Generally, when rubbing an alignment film, uneven rubbing tends to occur near the step portion, which tends to cause alignment abnormalities (domains) of the liquid crystal. For this reason, when the opening becomes small, there is a possibility that a domain may be generated over the entire small display section due to the step difference in the wiring section. Therefore, the complete storage capacitor element is arranged such that the minimum width of the opening of the pixel is 25 μm or more. The minimum width of the pixel opening is 25μ
If the thickness is more than m, most of the openings will be formed at positions sufficiently far away from the stepped portions of wiring, etc., and uneven rubbing will hardly occur, and alignment abnormalities such as domains will not occur.

Furthermore, since the common electrode signal line is common to all pixels in the display panel, care must be taken so that the lead-out portion at the end of the display panel does not distort the signal waveform of the common electrode signal line. That is, the minimum width of the lead-out portion of the common electrode signal line is made larger than the minimum width within the display panel. If the minimum width of the common electrode signal line lead-out part is larger than the minimum width within the display panel, the signal delay due to wiring resistance at the lead-out part will be small.
Less likely to cause signal waveform distortion.

Next, the overall configuration of a liquid crystal display device in which the complete storage capacitor element of the present invention is mounted will be described.

FIG. 24 shows an example of the configuration of a liquid crystal display system according to the present invention. The system includes an information processing system 220 such as a workstation, personal computer, word processor, etc., and a display system 200.

The display system 200 includes a liquid crystal display panel 202, a light source 201, a light source adjustment circuit 203, an image data generation circuit 204A, and a timing signal generation circuit 204B.
A control circuit 204 consisting of a control circuit 204, the brightness of the liquid crystal,
It is composed of a contrast adjustment circuit 240, a storage capacitor drive voltage generation circuit 205, and a common electrode drive voltage generation circuit 206.

The liquid crystal display panel 202 includes a liquid crystal panel 217,
It is composed of a signal circuit 207 and a scanning circuit 208 that generate signal voltages and scanning voltages.

The liquid crystal panel 217 includes a TFT 211 composed of A-5i, P-5i, etc., a complete storage capacitor 212, a liquid crystal capacitor 214, and a video signal line 210 for driving the TPT.
and a scanning signal line 209. One electrode of the complete storage capacitor 212 and the liquid crystal capacitor 214 is a TFT.
211, and the other electrode of the complete storage capacitor element 212 is connected to the storage capacitor common line 21.
5. The other electrode of the liquid crystal capacitor 214 is connected to the common electrode terminal 213.

The Vstg voltage generated by the storage capacitor drive voltage generation circuit 205 and the Vco generated by the common electrode voltage generation circuit 206
The m voltage is applied to the storage capacitor common line 215 and the common electrode terminal 2.
13, but these may have the same voltage level and phase and are not particularly limited. TFT
The other of the drain/source electrodes 211 is connected to the video signal line 2
10.

In addition, the complete storage capacitor element 212 and the storage capacitor common line 21
5 may be the connection example shown in FIG. 25, and is not particularly limited. Furthermore, the video signal 49 (2
10 and the signal circuit 207, as in the connection example shown in FIG. 26, the video signal lines are pulled out alternately in the vertical direction and each video signal line is connected to the signal circuit 207A and the signal circuit 207B. However, there are no particular limitations. Although not shown in FIG. 24, the method of connecting the scanning signal line 209 and the scanning circuit 208 is not particularly limited.

In FIG. 24, a signal circuit 207 and a scanning circuit 208
By integrating some or all of the circuits with the liquid crystal panel, the device can be simplified, the reliability of connections, etc. can be improved, and it is advantageous to lower costs. At this time, the means for configuring the signal circuit and the scanning circuit are as follows: (1) The circuit is placed on the liquid crystal panel 217 in an a-8i format.

(2) means for attaching the single crystal Si substrate on which the circuit is formed to the liquid crystal panel 217; and (3) means for combining the above two means. However, there is no particular limitation.

FIG. 27 shows one embodiment of a liquid crystal display panel 202. The liquid crystal display panel 202 includes a liquid crystal panel 218, signal circuit boards 227 to 234, and a scanning circuit board 2.
22 to 224, common electrode voltage Vcow and full holding capacitance voltage Vstg extraction substrates 225, 226, 235, 2
36. It is composed of a signal supply board 220.

Image data signals, power supply voltage, etc. are supplied to the signal supply board 220 via a signal cable 221.

Signal circuit boards 227 to 234 and scanning circuit board 222
An example of 224 is shown in FIG.

The circuit board is a circuit board in which an integrated circuit 237A having a signal circuit or a scanning circuit formed thereon is attached to an organic film or the like with patterned wiring. The pattern wiring 237B is a scanning voltage or signal voltage output terminal, and the pattern wiring 237C is
an image data signal for operating the integrated circuit 237A;
and a power supply voltage input terminal.

The common electrode voltage Vcom is applied to the common electrode terminal 238, and the storage capacitor voltage Vstg is applied to the storage capacitor common 12.
Added to 15.

Note that it is convenient for mounting if the drawer substrates 225, 226, 235, and 236 are made of elastic substrates such as organic films.

FIGS. 29A and 29B show an example of a system to which the liquid crystal display according to the present invention is applied.

FIG. 29A shows an example in which a liquid crystal display is applied to a display section of a desktop computer, which is composed of a computer main body 1, a keyboard 2, and a liquid crystal display 3. Compared to displays using conventional cathode ray tubes (hereinafter abbreviated as CRT), they are lighter and can be installed in a smaller area.

In particular, its features can be applied to systems that allow multiple operators to work simultaneously on a single computer 1 using multiple keyboards 2 and liquid crystal displays 3, as well as knee-rest type computers that require further weight reduction. is fully demonstrated.

Therefore, by using a liquid crystal display in the display section of a computer, it is possible to realize a lightweight, space-saving personal computer such as a notebook type computer.

FIG. 29B shows another application example of a liquid crystal display, in which a liquid crystal display is used as a part of the light shutter of a projection type display. The system consists of a projection section 4 including a liquid crystal display and an optical system. It consists of a screen 5 and a video signal processing section (not shown). The video signal input from the outside is converted by the video signal processing section into a signal format necessary for display on the liquid crystal display, such as a non-interlaced RGB digital signal, and an image is displayed on the liquid crystal display. This display image is formed on a screen through an optical system. Of these components,
The optical shutter part is the main factor that determines the dimensions of the optical system, and by using a liquid crystal display that can fit many pixels into a small panel, the optical shutter part can be made smaller, and the entire optical system can also be made smaller. Can be made smaller.

In addition, by using the small size and lightweight characteristics of liquid crystal displays, small color monitors and large wall-mounted televisions can be realized.

〔Effect of the invention〕

As described above, according to the present invention, in-plane variations in the optimal common potential are reduced, and fluctuations in the optimal common potential and threshold values are reduced. Further, short circuits between wiring lines and water marks are reduced, and yield is improved. Furthermore, discontinuity in the display section is avoided, and resolution deterioration is avoided.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a configuration example of a complete storage capacitor according to the present invention, FIG. 2 is a plan view of one pixel as an embodiment of the present invention, and FIG. 3 is a plan view of a pixel as an embodiment of the present invention. FIG. 4 is a plan view showing a main part of a liquid crystal display section in which a plurality of pixels are arranged according to an embodiment of the present invention; FIG.
FIG. 5 is a plan view 6A showing simultaneously the pixel pattern on the lower transparent glass substrate and the color filter pattern on the upper transparent glass substrate according to the embodiment of the present invention. FIG. 60 is a cross-sectional view of an end portion of a liquid crystal display device according to the present invention.
Figure B is a sectional view taken along the line VIB-VIB in Figure 2, No. 7.8
, 9.10 is a plan view of an intermediate step in the pixel formation process, the first
Figure 1 is an equivalent circuit diagram of one pixel, Figure 12 is a conceptual diagram showing the relationship between the capacitance value of a complete storage capacitor element and the optimal common potential, and Figure 13.
The figure is a conceptual diagram showing the relationship between the area of the capacitive part and the peripheral length of the capacitive part. Fig. 14.15.21.22 is a plan view showing another example of the structure of a complete storage capacitive element. Fig. 16.18.20. 17 is a waveform diagram showing the driving waveform of the complete storage capacitor element according to the embodiment of the present invention, FIG. 17 is a waveform diagram of the driving waveform according to the prior art, and FIG. 19 is the video signal line divided into eight gradations and the common electrode signal. FIG. 23 is a waveform diagram showing a line driving waveform, and FIG. 23 is a plan view showing an example of arrangement of a complete storage capacitor element according to the present invention, and FIG. 24.25.2
6 is a plan view showing a configuration example of a liquid crystal display system according to an embodiment of the present invention, FIG. 27 is a plan view showing an example of a liquid crystal display panel according to the present invention, and FIG. 28 is a plan view showing a signal circuit board and a scanning circuit board. Plan view showing an example of a circuit board, No. 29A,
FIG. 29B is a perspective view showing an example of a system to which the liquid crystal display according to the present invention is applied. 211... TPT, 212... Complete storage capacitor element. 214...Liquid crystal capacitor, 301...Scanning signal line, 30
2... Video signal line, 303... Common electrode signal 1IX
(3rd degree fourth electrode), 304... Thin film transistor (TPT), 307, 308... Drain/source electrode, 309... Transparent pixel electrode (liquid crystal capacitive element), 31
0... Complete storage capacitor element, 526... Common electrode signal line, 527... Transparent pixel electrode, 528, 529...
Recessed portion, 530... Complete storage capacitor element, 534... Transparent image electrode, 536... Common electrode signal line, 540,
541゜546.547... Complete storage capacitor element, 54
8,549...Common electrode signal line connection part.

Claims (1)

[Scope of Claims] 1. A first wiring forming a scanning signal line, a thin film transistor having a gate electrode connected to the first wiring, and a video signal line connected to one of the drain/source electrodes of the thin film transistor. a complete storage capacitor element having one electrode connected to the other of the drain/source electrodes of the thin film transistor, and a liquid crystal having one electrode connected to the other of the drain/source electrodes of the thin film transistor. a third electrode connected to the other electrode of the full retention capacitive element; and a fourth electrode connected to the other electrode of the liquid crystal capacitive element and substantially connected to the third electrode. In a thin film transistor driven liquid crystal display device in which a plurality of pixels including electrodes are arranged, the peripheral length μm of the capacitive part of each complete storage capacitive element is the area μm^2 of the capacitive part according to the thin film transistor driving method. The third and fourth electrodes are connected to a common electrode signal line, and the third and fourth electrodes are connected to a common electrode signal line. A thin film transistor driven liquid crystal display device characterized by: 2. The thin film transistor driven liquid crystal display device according to claim 1, wherein the capacitive portion of the complete storage capacitive element is formed by overlapping portions of electrodes that face each other and have different widths and lengths. 3. The video signal lines are arranged parallel to each other in the vertical direction at substantially equal intervals, the scanning signal lines are arranged parallel to each other at substantially equal intervals in the horizontal direction substantially perpendicular to the video signal lines, and the common electrode signal lines are 3. The thin film transistor driven liquid crystal display device according to claim 1, wherein the thin film transistor driven liquid crystal display device is arranged substantially parallel to the scanning signal lines and alternately with the scanning signal lines. 4. The capacitive part of the complete storage capacitive element is formed by the overlapping part of the common electrode signal line between the video signal lines and the transparent pixel electrode that is also arranged between the video signal lines, and The vertical width of the overlapping portion of the electrode signal line is a value obtained by dividing the area of the capacitive part of the complete storage capacitor element by the horizontal width of the transparent pixel electrode, and the width of the common electrode signal line is 4. The thin film transistor driven liquid crystal display device according to claim 3, wherein the connection portion between the complete retention capacitor elements is arranged approximately at the vertical center of the lateral end portion of the complete retention capacitor element. 5. The vertical row width of the part of the thin film transistor part through which light does not pass and which does not become a display part is almost the same as the vertical row width of the part of the complete storage capacitor element part through which light does not pass and does not become a display part. 5. The thin film transistor section, which does not become a display section, is separated from the complete storage capacitor section, and the intervals therebetween are substantially the same for each pixel. Thin film transistor driven liquid crystal display device. 6. The mutually opposing vertical ends of the common electrode signal lines forming one electrode of the complete storage capacitor element form parallel lines, and the mutually opposing ends of the transparent pixel electrodes forming the other electrode of the complete storage capacitor element. 6. The thin film transistor driven liquid crystal display device according to claim 1, wherein the lateral ends also form parallel lines. 7. At least one of the vertical ends of the common electrode signal line forming one electrode of the complete storage capacitor element is covered with a film laminated on the common electrode signal line. 7. The thin film transistor driven liquid crystal display device according to claim 6, further comprising a recessed portion having a width smaller in a direction than other portions. 8. The thin film transistor driven liquid crystal display device according to claim 1, wherein the complete storage capacitor element is arranged approximately at the center of the pixel. 9. It has at least 3 million pixels, and the diagonal length of the area in which the pixels are arranged is at least 25.4 cm.
The thin film transistor driven liquid crystal display device according to any one of claims 1 to 8. 10. The timing at which the potential of the common electrode signal line starts to change is the delay time of the potential of the video signal line relative to the potential of the scanning signal line from one scanning signal line selection time with respect to the timing at which the potential of the video signal line starts to change; 3. The method of driving a thin film transistor driven liquid crystal display device according to claim 1, further comprising delaying the potential of the common electrode signal line by a time equal to or less than a maximum delay time and greater than zero. 11. The thin film transistor driven liquid crystal display device according to claim 1 or 2, wherein the pulse width (1/2 of one period) of the common electrode signal line is n times the one scanning signal line selection time. Driving method.