JPH039565A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To make it possible to obtain an image signal having a good S/N even if the illuminance for the title device is low by a method wherein a negative potential is set in a potential setting gate conductor and a potential setting signal conductor and an n-type impurity semiconductor region, which is used as an avalanche region, and an n<-> impurity semiconductor region are all depleted. CONSTITUTION:Such a proper negative potential as an n-type impurity semiconductor region 2 and an n<-> impurity semiconductor region 4 are all depleted is set in a potential setting signal conductor 9 for setting the potential of a P<+> impurity semiconductor region 1 of an avalanche photo diode of a level of 0 on a p-type well 11 and such a positive potential as the well 11 under the photodiode is depleted is set in an n-type substrate 12. Moreover, by applying a positive voltage to a potential setting gate conductor 6 for setting the potential of an n<-> impurity semiconductor region of the avalanche diode, a high electric field is applied to the region 2 and is brought into an avalanche state. Thereby, even if the illuminance of a solid-state image sensing device is low, an image having a good S/N is obtained.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a solid-state imaging device.

(Conventional technology) Solid-state imaging devices are small, lightweight, maintenance-free,
It has advantages such as no image distortion.

Ever since practical devices appeared in the late 1970s, performance improvements have continued at a remarkable pace, and consumer video cameras have
It surpassed the performance of MKS tubes and has almost completely replaced image pickup tubes. Among them, COD and MOS type image pickup devices are comprehensively superior and have become the -L style.

But 1. For the era of HDTV (handy TV),
Solid-state imaging devices are being forced to increasingly reduce their pixel dimensions, and it is expected that their sensitivity and dynamic range will decrease.

FIG. 4 is a pixel structure diagram of a conventional MOS type image sensor. The pixel section consists of a photodiode and a vertical switch MOS transistor. The photodiode is P-well 11
, an n-type substrate 12 to which a positive bias is applied. and an n0 impurity semiconductor region which absorbs photoelectrically converted signal charges. Vertical switch M
The OS transistor part has a drain 5 and a vertical gate line 7.
, and vertical signal lines 8. Note that 10 is a channel stop region.

FIG. 5 is a basic circuit diagram of a MOS type image sensor.
In FIG. 5, 30 is a horizontal scanning circuit, 31 is a vertical scanning circuit, and 32 is a horizontal readout switch.

7 is a vertical gate line, 8 is a vertical signal line, and 33 is a photodiode section.

The operation of the MOS type image sensor configured as above will be described below.

The signal charges photoelectrically converted for a certain period in the photodiode section are accumulated in the n'' impurity semiconductor region 13, which is a signal charge accumulation section.Next, during the horizontal blanking period, a pulse is sent to the vertical gate line 7 from the vertical scanning circuit 31. is applied, and the signal charges accumulated in the n0 impurity semiconductor region 13 are converted to vertical signal 1.
iI8. After this.

During the horizontal scanning period, a horizontal scanning pulse is applied from the horizontal scanning circuit 30, the horizontal readout switch 32 is turned on, and signal charges are sequentially output.

(Problems to be Solved by the Invention) However, in the solid-state imaging device configured as described above, since the capacitance of the vertical signal line is large, so-called KTC noise, which has high thermal noise, cannot be reduced. M in Figure 6
The relationship between the number of noise electrons per pixel of the image sensor and the signal charge is shown for the OS type.

As is clear from FIG. 6, there was a problem in that the KTC noise became dominant over almost the entire illuminance.

The present invention is intended to solve the above problems.
It is an object of the present invention to provide a solid-state imaging device that is not affected by KTC noise as much as possible and has good S/H even in low illuminance.

(Means for Solving the Problems) In order to achieve the above object, the solid-state imaging device of the present invention has the following features:
- an avalanche photodiode on a conductive semiconductor substrate, and a storage photodiode that amplifies and stores signal charges photoelectrically converted by the avalanche photodiode;
An n-type impurity semiconductor region that becomes an avalanche region and an n-type impurity semiconductor region
``It is composed of a potential setting gate line and a potential setting signal line that set a negative potential at which all the impurity semiconductor regions are depleted, and an M○S transistor that reads out the signal charge from the storage photodiode.

(Function) According to the present invention, a negative potential is set on the potential setting gate line and the potential setting signal line, so that the n-type impurity semiconductor region and the n- impurity semiconductor region that become the avalanche region are all depleted. Therefore, it is possible to relatively reduce KTC noise, and it is possible to obtain an image signal with a good S/N ratio even at low illuminance.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional structural diagram of a pixel portion of a solid-state imaging device according to an embodiment of the present invention.

In FIG. 1, 1 is a p00 impurity semiconductor region of an avalanche photodiode, 2 is an n-type impurity semiconductor region that becomes an avalanche region that amplifies signal charges, 3 is a storage photodiode that accumulates amplified signal charges, and 4 is an n-type impurity semiconductor region. An n-impurity semiconductor region for guiding the signal charge amplified in the type impurity semiconductor region 2 to the storage photodiode 3, 5 a drain for reading out the signal charge, and 6 an n-impurity semiconductor region 4.
Potential setting gate line 7 for setting the potential of storage photodiode 3 7! A vertical gate line 8 provides a pulse for reading out the signal charge accumulated in the storage photodiode 3; a vertical signal line 8 reads out the signal charge accumulated in the storage photodiode 3 using a pulse from the vertical gate line 7; 9 a p+ impurity semiconductor of the avalanche photodiode. A potential setting signal line for setting the potential of region 1; 10 is a channel stop region; 11 is a p-well; 12 is an n-type substrate.

The operation of the solid-state imaging device configured as follows will be explained.

The p-well 11 has Ov, and the potential setting signal line 9 that sets the potential of the p+ impurity half-quad region 1 of the avalanche photodiode has the n-type impurity semiconductor region 2 and the n- impurity semiconductor region 4 all depleted. At a suitable negative potential such as
A positive potential is set so that each is depleted. Further, by applying a positive voltage to the potential setting gate line 6, a high electric field is applied to the n-type impurity semiconductor region 2, and the n-type impurity semiconductor region 2 is kept in an avalanche state.

FIG. 2 shows the potential shape of the photodiode section when it is set in this way.

The circuit configuration of this embodiment is exactly the same as the circuit configuration diagram shown in FIG.

Light incident on the p1 impurity semiconductor region 1 of the avalanche photodiode is photoelectrically converted, and the holes reach the p+ impurity semiconductor region and are absorbed. Electrons are amplified in the n-type impurity semiconductor region 2, which is an avalanche region, and become n-
The impurity semiconductor region 4 is reached. n- impurity semiconductor region 4
The electrons that have reached this point are stored in the storage photodiode 3.

To read out the charge thereafter, a pulse is applied to the vertical gate line 7 from the vertical scanning circuit 31 during the horizontal blanking period, and the charge is read out from the storage photodiode 3 to the vertical signal line 8, as in the conventional example. After this, a horizontal scanning pulse is applied from the horizontal scanning circuit 30 during the horizontal scanning period.

The horizontal readout switch 32 is turned on to output sequentially.

FIG. 3 shows the photoelectric conversion performance of the solid-state imaging device of the present invention constructed as described above. In the embodiment of the present invention, the voltage is set so that the gain of the avalanche photodiode is 10 times. As can be seen from FIG. 3, the KTC noise component is relatively reduced.

(Effects of the Invention) According to the present invention, the KTC noise component is relatively reduced by setting a negative potential such that the n-impurity semiconductor region and the n-type impurity semiconductor region are all depleted. It is now possible to obtain images with good S/N even in low illumination, and the dynamic range has also been improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of a pixel portion of a solid-state imaging device in an embodiment of the present invention, and FIG. 2 is a diagram showing a potential shape of an avalanche photodiode in an embodiment of the present invention.
Fig. 3 is a photoelectric conversion and noise characteristic diagram in an embodiment of the present invention, Fig. 4 is a cross-sectional structural diagram of a pixel section of a conventional solid-state imaging device, and Fig. 5 is a circuit configuration diagram of a conventional solid-state imaging device and an embodiment. , FIG. 6 is a diagram showing photoelectric conversion and noise characteristics of a conventional solid-state imaging device. 1.2.4...Pan type, n-impurity semiconductor region constituting an avalanche photodiode, 3...
Storage photodiode. 5...Drain, 6...Potential setting gate line for setting the potential of the n- impurity semiconductor region of the avalanche photodiode, 7...Vertical gate line for reading signal charges. 8... Vertical signal line, 9... Potential setting signal line for setting the potential of the p3 impurity semiconductor region of the avalanche photodiode, 10... Channel stop region, 11... P well, 12...・N-type substrate.

Claims (1)

[Claims] an avalanche photodiode on a one-conductivity semiconductor substrate; a storage photodiode that amplifies and stores signal charges photoelectrically converted by the avalanche photodiode;
An n-type impurity semiconductor region that becomes an avalanche region and an n-type impurity semiconductor region
^-A potential setting gate line and a potential setting signal line that set a negative potential at which all the impurity semiconductor regions are depleted, and a MOS that reads out the signal charge from the storage photodiode.
A solid-state imaging device comprising a transistor.