JPH0379434U - - Google Patents
Info
- Publication number
- JPH0379434U JPH0379434U JP14094989U JP14094989U JPH0379434U JP H0379434 U JPH0379434 U JP H0379434U JP 14094989 U JP14094989 U JP 14094989U JP 14094989 U JP14094989 U JP 14094989U JP H0379434 U JPH0379434 U JP H0379434U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- block
- semiconductor device
- source pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14094989U JPH0379434U (US07122603-20061017-C00045.png) | 1989-12-04 | 1989-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14094989U JPH0379434U (US07122603-20061017-C00045.png) | 1989-12-04 | 1989-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0379434U true JPH0379434U (US07122603-20061017-C00045.png) | 1991-08-13 |
Family
ID=31687884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14094989U Pending JPH0379434U (US07122603-20061017-C00045.png) | 1989-12-04 | 1989-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0379434U (US07122603-20061017-C00045.png) |
-
1989
- 1989-12-04 JP JP14094989U patent/JPH0379434U/ja active Pending
