JPH0363822B2 - - Google Patents
Info
- Publication number
- JPH0363822B2 JPH0363822B2 JP60134658A JP13465885A JPH0363822B2 JP H0363822 B2 JPH0363822 B2 JP H0363822B2 JP 60134658 A JP60134658 A JP 60134658A JP 13465885 A JP13465885 A JP 13465885A JP H0363822 B2 JPH0363822 B2 JP H0363822B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- heat sink
- mold layer
- resin mold
- bed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920005989 resin Polymers 0.000 claims description 65
- 239000011347 resin Substances 0.000 claims description 65
- 239000004065 semiconductor Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000009413 insulation Methods 0.000 description 9
- 238000001721 transfer moulding Methods 0.000 description 9
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 229910002026 crystalline silica Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は樹脂封止型半導体装置に関し、特に、
半導体チツプに対して絶縁されたヒートシンクを
有する樹脂封止型半導体装置の改良に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-encapsulated semiconductor device, and in particular,
The present invention relates to an improvement of a resin-sealed semiconductor device having a heat sink insulated from a semiconductor chip.
例えばパワートランジスタアレイのような電力
用半導体装置では、一つのヒートシンク上に複数
の半導体チツプをマウントして組立て、これを単
一の樹脂モールド層で封止した形態のものが知ら
れている。このような半導体装置では、当然なが
ら個々の半導体チツプとヒートシンクとは絶縁さ
れていなければならない。このため、当初はセラ
ミツク基板が用いられていたが、コストが高いこ
とや加工性に問題があることから、種々の代替が
提案されている。
For example, a power semiconductor device such as a power transistor array is known in which a plurality of semiconductor chips are mounted and assembled on one heat sink, and this is sealed with a single resin mold layer. Naturally, in such a semiconductor device, each semiconductor chip and a heat sink must be insulated. For this reason, ceramic substrates were initially used, but because of their high cost and problems with workability, various alternatives have been proposed.
出願人もセラミツク基板を用いず、通常の金属
製ヒートシンクのみを用いて半導体チツプ相互間
の絶縁を達成し得る樹脂封止型半導体装置の構造
を先に提案した。以下に第２図〜第５図を参照
し、この出願人の提案になる構造を説明する。 The applicant has also previously proposed the structure of a resin-sealed semiconductor device that can achieve insulation between semiconductor chips by using only an ordinary metal heat sink without using a ceramic substrate. The structure proposed by this applicant will be explained below with reference to FIGS. 2 to 5.
第２図はアルミニウム板等の熱伝導性の高い金
属板からなるヒートシンク１の平面図である。該
ヒートシンク１には放熱板に固着するためのビス
止め孔１１が形成されている。また、第３図は銅
系あるいは鉄系合金等の導電性金属薄板をパター
ンニングしたリードフレーム２の平面図である。
図示のように、リードフレーム２には独立した四
つのベツド部２１及びリードパターン２２が形成
され、これらはフレーム２３に連結して支持され
ている。 FIG. 2 is a plan view of the heat sink 1 made of a metal plate with high thermal conductivity such as an aluminum plate. The heat sink 1 is formed with screw holes 11 for fixing it to a heat sink. Further, FIG. 3 is a plan view of a lead frame 2 formed by patterning a conductive metal thin plate such as a copper-based or iron-based alloy.
As shown in the figure, four independent bed portions 21 and lead patterns 22 are formed on the lead frame 2, and these are connected to and supported by a frame 23.
出願人が先に提案した構造を得るには、リード
フレーム２のベツド部２１上に夫々半導体チツプ
をダイボンデイングし且つ所要のワイヤボンデイ
ングを施した後、これをヒートシンク１と共に金
型内にセツトしてトランスフアーモールドを行な
う。その際、リードフレームはヒートシンク１の
上に所定の間隙を置いて設置し、この間隙をモー
ルド樹脂が埋めるようにする。第４図は、こうし
て樹脂封止した後にリードフオーミングを行なつ
た状態を示す平面図であり、図中３は樹脂モール
ド層である。 In order to obtain the structure proposed earlier by the applicant, semiconductor chips are die-bonded on the bed portion 21 of the lead frame 2 and the required wire bonding is performed, and then these chips are set in a mold together with the heat sink 1. Perform transfer molding. At this time, the lead frame is placed on the heat sink 1 with a predetermined gap, and the mold resin fills this gap. FIG. 4 is a plan view showing a state in which lead forming is performed after resin sealing, and 3 in the figure is a resin mold layer.
第５図は第４図−線に沿う断面図で、図中
４は半田層５を介してベツド部２１上にダイボン
デイングされた半導体チツプ、６はボンデイング
ワイヤである。図示のように、この構造ではリー
ドフレーム２（特にベツド部２１）とヒートシン
ク１との間の間隙に樹脂モールド層３が介在し、
これによつて両者間の絶縁が達成されている。 FIG. 5 is a cross-sectional view taken along the line in FIG. 4, in which 4 is a semiconductor chip die-bonded onto the bed portion 21 via a solder layer 5, and 6 is a bonding wire. As shown in the figure, in this structure, a resin mold layer 3 is interposed in the gap between the lead frame 2 (particularly the bed portion 21) and the heat sink 1.
This achieves insulation between the two.
なお、上記の構造における放熱性はベツド部２
１とヒートシンク１との間に介在するモールド樹
脂の熱伝導率に依存する。そこで、樹脂モールド
層３として結晶性シリカ粉末を混合して熱伝導率
を向上させたエポキシ樹脂（λ＝60×10-4cal／
cm・sec・℃）が用いられている。 Note that the heat dissipation in the above structure is limited to the bed portion 2.
It depends on the thermal conductivity of the mold resin interposed between 1 and the heat sink 1. Therefore, as the resin mold layer 3, epoxy resin (λ = 60 × 10 -4 cal /
cm・sec・℃) is used.
上記従来の樹脂封止型半導体装置に用いられて
いる高熱伝導性樹脂は、結晶性シリカが多く混入
されているために粘度が高くならざるを得ない。
このため、トランスフアーモールドで樹脂モール
ド層３を形成する際にベツド部２１とヒートシン
クの間を埋める樹脂層にボイドが発生し易く、こ
のボイド発生は絶縁耐圧を低下させる。この傾向
は樹脂液の粘度に比例し、且つベツド部とヒート
シンク間の距離に反比例するから、シリカ含有率
を高めて放熱特性を向上しようとするとボイド発
生が顕著になつて絶縁性が低下してしまう問題が
あつた。また、樹脂液の粘度が高くなると、トラ
ンスフアーモールドの際の樹脂液の流れ抵抗が大
きくなり、ボンデイングワイヤ６の切断等、所謂
ボンデイングオープン不良を起こし易いという問
題が生じる。
The highly thermally conductive resin used in the conventional resin-sealed semiconductor device has a high viscosity because it contains a large amount of crystalline silica.
For this reason, when the resin mold layer 3 is formed by transfer molding, voids are likely to occur in the resin layer filling the space between the bed portion 21 and the heat sink, and this void generation lowers the dielectric strength voltage. This tendency is proportional to the viscosity of the resin liquid and inversely proportional to the distance between the bed and the heat sink, so if you try to improve the heat dissipation characteristics by increasing the silica content, the occurrence of voids will become noticeable and the insulation will deteriorate. I had a problem. Furthermore, when the viscosity of the resin liquid increases, the flow resistance of the resin liquid during transfer molding increases, causing a problem that so-called bonding open failures such as breakage of the bonding wire 6 are likely to occur.
一方、シリカ含有量を増大し且つボイド発生を
抑制しようとすればベツド部／ヒートシンク間の
距離を大きくせざるを得ず、樹脂層による熱抵抗
が増大して放熱特性向上の効果が得られなくなつ
てしまう。因みに、ベツド部２１の寸法が８mm×
８mm、モールド樹脂としてλ＝60×10-4cal／
cm・sec・℃の結晶性シリカ含有エポキシ樹脂を
用いた場合、ボイド発生の関係からベツド部／ヒ
ートシンク間距離を0.5mm以下にすることはでき
なかつた。 On the other hand, if you try to increase the silica content and suppress the generation of voids, you have to increase the distance between the bed part and the heat sink, which increases the thermal resistance of the resin layer and makes it impossible to improve heat dissipation characteristics. I get used to it. By the way, the dimensions of the bed part 21 are 8 mm x
8mm, as mold resin λ=60×10 -4 cal/
When using an epoxy resin containing crystalline silica of cm·sec·°C, it was not possible to reduce the distance between the bed portion and the heat sink to 0.5 mm or less due to the generation of voids.
本発明は上記従来の樹脂封止型半導体装置にお
ける問題を改善するためになされたもので、ベツ
ド部とヒートシンク間の距離を短縮すると共に、
ボイドの発生を防止し且つ両者間に介在するモー
ルド樹脂層の結晶性シリカ含有率を増大し、絶縁
性を維持しつつ放熱特性を向上することができる
樹脂封止型半導体装置の構造を提供しようとする
ものである。
The present invention was made in order to improve the above-mentioned problems in the conventional resin-sealed semiconductor device, and in addition to shortening the distance between the bed portion and the heat sink,
It is an object of the present invention to provide a structure of a resin-sealed semiconductor device that can prevent the generation of voids, increase the crystalline silica content of a mold resin layer interposed between the two, and improve heat dissipation characteristics while maintaining insulation properties. That is.
本発明による樹脂封止型半導体装置は、金属製
のベツド部表面にマウントされた半導体チツプ
と、前記ベツド部及び前記半導体チツプを前記ベ
ツド部の裏面が露出するように封止する第一の樹
脂モールド層と、前記ベツド部の露出した裏面下
に所定の距離を置いて配置された金属製のヒート
シンクと、該ヒートシンクおよび前記第一の樹脂
モールド層の外側を覆い、且つ前記ベツド部の露
出面と前記ヒートシンクとの間の間〓に充填して
形成された、前記第一の樹脂モールド層の樹脂よ
りも高熱伝導率の樹脂からなる第二の樹脂モール
ド層と、前記第二樹脂モールド層を貫通してその
先端部が前記第一の樹脂モールド層内に配置さ
れ、且つ前記半導体チツプ表面の内部端子に電気
的に接続されたリードとを具備したことを特徴と
するものである。
A resin-sealed semiconductor device according to the present invention includes a semiconductor chip mounted on the surface of a metal bed, and a first resin that seals the bed and the semiconductor chip so that the back surface of the bed is exposed. a mold layer; a metal heat sink disposed at a predetermined distance below the exposed back surface of the bed portion; and a metal heat sink that covers the outside of the heat sink and the first resin mold layer and that exposes the exposed surface of the bed portion. a second resin mold layer made of a resin having a higher thermal conductivity than the resin of the first resin mold layer, the second resin mold layer being filled in the space between the first resin mold layer and the heat sink; The device is characterized in that it includes a lead that penetrates through the semiconductor chip and has a leading end disposed within the first resin mold layer and electrically connected to an internal terminal on the surface of the semiconductor chip.
上記のように、本発明は樹脂モールド層を二層
に分けたことを要点とするもので、第一の樹脂モ
ールド層を形成した後、第二の樹脂モールド層を
トランスフアーモールドして製造することにな
る。この場合、一段階のトランスフアーモールド
による従来の場合とは樹脂液の流れが異なるた
め、最終的に空気が溜り易い部分はベツド部／ヒ
ートシンク間の間隙ではなく、第一の樹脂モール
ド層の外側部分になる。その結果、第二の樹脂モ
ールド層として粘度の高い樹脂を用い且つベツド
部／ヒートシンク間の間隙を狭くした場合にも、
この間隙内を充填する樹脂層にボイドが形成され
るのを防止できる。従つて、第二の樹脂モールド
層としてシリカ含有量の多い高熱伝導率の樹脂を
用い、絶縁性を維持しつつ放熱特性を向上するこ
とが可能となる。 As mentioned above, the main point of the present invention is that the resin mold layer is divided into two layers, and after forming the first resin mold layer, the second resin mold layer is manufactured by transfer molding. It turns out. In this case, the flow of the resin liquid is different from the conventional case of one-stage transfer molding, so the area where air tends to accumulate is not the gap between the bed section and the heat sink, but the outside of the first resin mold layer. Become a part. As a result, even when a high viscosity resin is used as the second resin mold layer and the gap between the bed section and the heat sink is narrowed,
It is possible to prevent voids from being formed in the resin layer filling this gap. Therefore, by using a high thermal conductivity resin with a high silica content as the second resin mold layer, it is possible to improve heat dissipation characteristics while maintaining insulation properties.
また、第二の樹脂モールド層を形成する際には
既に第一の樹脂モールド層が形成されているか
ら、高粘性の樹脂液によるトランスフアーモール
ドに際してもボンデイングオープン等の問題は発
生しない。 Further, since the first resin mold layer has already been formed when forming the second resin mold layer, problems such as bonding open do not occur even when transfer molding is performed using a highly viscous resin liquid.
なお、半導体チツプとヒートシンクとの間の絶
縁は、第２図〜第５図のように複数個の半導体チ
ツプを単一のパツケージ内に封止する場合に限ら
ず、１個の半導体チツプを封止した半導体装置に
おいても必要とされるものである。即ち、複数の
半導体装置の夫々をそのヒートシンクを同一の放
熱板上に固定して設置する場合には、当然に同様
の絶縁が要求される。従つて、本発明は第２図〜
第５図に説明した半導体装置のみならず、１個の
半導体チツプを封止した樹脂封止型半導体装置に
適用した場合にもその特有の効果を奏するもので
ある。 Note that insulation between a semiconductor chip and a heat sink is not limited to the case where multiple semiconductor chips are sealed in a single package as shown in Figs. 2 to 5, but also when a single semiconductor chip is sealed. It is also needed in semiconductor devices that have stopped. That is, when a plurality of semiconductor devices are installed with their respective heat sinks fixed on the same heat sink, similar insulation is naturally required. Therefore, the present invention is based on FIGS.
This unique effect is achieved not only when applied to the semiconductor device illustrated in FIG. 5, but also when applied to a resin-sealed semiconductor device in which a single semiconductor chip is sealed.
第１図は本発明の一実施例になる樹脂封止型半
導体装置を示す断面図である。同図において、第
２図〜第５図と同じ部分には同一の参照番号を付
してある。即ち、１はヒートシンク、２はリード
フレーム、２１はベツド部、４は半導体チツプ、
５は半田合金等のマウント剤層、６はAu、Al等
の金属細線からなるボンデイングワイヤである。
この実施例においては、樹脂モールド層が第一の
樹脂モールド層３1、第二の樹脂モールド層３2の
二層構造になつており、何れも結晶性シリカを含
む高熱伝導性エポキシ樹脂からなつている。但
し、第一の樹脂モールド層３1にはλ＝60×
10-4cal／cm・sec・℃のものを用い、第二の樹脂
モールド層３2には更に熱伝導率の高いλ＝80〜
90-4cal／cm・sec・℃のものを用いている。ま
た、ベツド部２１の寸法は10mm×10mm、ベツド
部／ヒートシンク間の距離は0.3mmである。
FIG. 1 is a sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention. In this figure, the same parts as in FIGS. 2 to 5 are given the same reference numerals. That is, 1 is a heat sink, 2 is a lead frame, 21 is a bed part, 4 is a semiconductor chip,
5 is a mounting agent layer such as a solder alloy, and 6 is a bonding wire made of a thin metal wire such as Au or Al.
In this embodiment, the resin mold layer has a two-layer structure of a first resin mold layer 3 1 and a second resin mold layer 3 2 , both of which are made of highly thermally conductive epoxy resin containing crystalline silica. ing. However, for the first resin mold layer 31 , λ=60×
10 -4 cal/cm・sec・℃ is used, and the second resin mold layer 32 is made of λ=80~ with even higher thermal conductivity.
90 -4 cal/cm・sec・℃ is used. Further, the dimensions of the bed section 21 are 10 mm x 10 mm, and the distance between the bed section and the heat sink is 0.3 mm.
上記実施例になる樹脂封止型半導体装置の製造
に際しては、従来と同様にリードフレーム３上で
半導体チツプ４のダイボンデイング及びワイヤボ
ンデイングを行なつた後、トランスフアーモール
ドにより第一の樹脂モールド層３1を形成して樹
脂封止を行なう。次に、ヒートシンク１をトラン
スフアーモルド金型内に設置し、更に該ヒートシ
ンク上に所定の間隔を置いて前記第一の樹脂モー
ルド層を形成したリードフレームを設置した後、
トランスフアーモールドを行なつて第二の樹脂モ
ールド層３2を形成する。この二回目のトランス
フアーモールドにおいて、樹脂液は先ずヒートシ
ンク１と第一の樹脂モールド層との間を流れてか
ら第一の樹脂モールドの外側に流れ込む。従つ
て、この場合の空気の逃げ場は従来のようにベツ
ド部／ヒートシンク間の間隙ではなく、第二の樹
脂モールド層３2成形空間となり、問題の間隙部
分には何等ボイドを生じることなく高熱伝導率の
樹脂を充填することができた。 In manufacturing the resin-sealed semiconductor device of the above embodiment, after performing die bonding and wire bonding of the semiconductor chip 4 on the lead frame 3 as in the conventional method, a first resin mold layer is formed by transfer molding. 3 1 is formed and resin-sealed. Next, the heat sink 1 is installed in a transfer mold mold, and the lead frame on which the first resin mold layer is formed is placed on the heat sink at a predetermined interval.
A second resin mold layer 32 is formed by transfer molding. In this second transfer molding, the resin liquid first flows between the heat sink 1 and the first resin mold layer, and then flows to the outside of the first resin mold. Therefore, the place for air to escape in this case is not the gap between the bed section and the heat sink as in the conventional case, but the molding space of the second resin mold layer 32 , and the gap area in question has high thermal conductivity without any voids. It was possible to fill the resin with a certain amount of resin.
上記実施例になる樹脂封止型半導体装置では、
ベツド部／ヒートシンク間の距離を0.3mmと従来
の1/2に短縮し、且つこの間隙内を従来よりも熱
伝導率の高い樹脂で充填したため、この間隙内の
樹脂層による熱抵抗は従来の3.4℃／Ｗから1.8
℃／Ｗと約47％改善することができた。また、こ
の間隙内の樹脂層におけるボイドの発生を略完全
に防止できたため、絶縁性の低下といつた問題は
生じなかつた。 In the resin-sealed semiconductor device of the above embodiment,
The distance between the bed part and the heat sink has been shortened to 0.3 mm, which is half of the conventional one, and this gap has been filled with resin that has higher thermal conductivity than the conventional one, so the thermal resistance due to the resin layer in this gap is lower than that of the conventional one. 3.4℃/W to 1.8
We were able to improve the temperature by approximately 47% (°C/W). Furthermore, since the generation of voids in the resin layer within this gap could be almost completely prevented, problems such as deterioration of insulation did not occur.
なお、本発明を効果的に適用できる具体的なデ
バイスとしては、トランジスタ、トランジスタア
レイの他、ダイオードアレイやソリツドステート
リレー、フオトカプラ等が挙げられる。 Note that specific devices to which the present invention can be effectively applied include transistors, transistor arrays, diode arrays, solid state relays, photocouplers, and the like.
以上詳述したように、本発明によればベツド部
とヒートシンク間に外囲器樹脂を介在させて両者
間を絶縁した樹脂封止型半導体装置において、ベ
ツド部とヒートシンク間の距離を短縮すると共
に、ボイドの発生を防止し且つ両者間に介在する
モールド樹脂層の結晶性シリカ含有率を増大し、
絶縁性を維持しつつ放熱特性を向上することがで
きる等、顕著な効果が得られるものである。
As detailed above, according to the present invention, in a resin-sealed semiconductor device in which an envelope resin is interposed between a bed part and a heat sink to insulate them, the distance between the bed part and the heat sink can be shortened, and the distance between the bed part and the heat sink can be shortened. , preventing the generation of voids and increasing the crystalline silica content of the mold resin layer interposed between the two,
Remarkable effects can be obtained, such as being able to improve heat dissipation characteristics while maintaining insulation properties.
第１図は本発明の一実施例になる樹脂封止型半
導体装置の断面図、第２図〜第５図は従来の樹脂
封止型半導体装置の一例を説明するための図であ
る。
１……ヒートシンク、２……リードフレーム、
２１……ベツド部、３，３1，３2……樹脂モール
ド層、４……半導体チツプ、５……マウント剤、
６……ボンデイングワイヤ。
FIG. 1 is a sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 5 are diagrams for explaining an example of a conventional resin-sealed semiconductor device. 1...Heat sink, 2...Lead frame,
21...Bed part, 3,31,32 ...Resin mold layer, 4 ...Semiconductor chip, 5...Mounting agent,
6...Bonding wire.
Claims (1)
体チツプと、前記ベツド部及び前記半導体チツプ
を前記ベツド部の裏面が露出するように封止する
第一の樹脂モールド層と、前記ベツド部の露出し
た裏面下に所定の距離をおいて配置された金属製
のヒートシンクと、前記ヒートシンク及び前記第
一の樹脂モールド層の外側を覆い、且つ前記ベツ
ド部の露出面と前記ヒートシンクとの間の間〓に
充填して形成された、前記第一の樹脂モールド層
の樹脂よりも高熱伝導率の樹脂からなる第二の樹
脂モールド層と、前記第二の樹脂モールド層を貫
通してその先端部が前記第一の樹脂モールド層内
に配置され、且つ前記半導体チツプ表面の内部端
子に電気的に接続されたリードとを具備したこと
を特徴とする樹脂封止型半導体装置。1. A semiconductor chip mounted on the surface of a metal bed part, a first resin mold layer that seals the bed part and the semiconductor chip so that the back surface of the bed part is exposed, and A metal heat sink disposed at a predetermined distance below the back surface, and a metal heat sink that covers the outside of the heat sink and the first resin mold layer, and is located between the exposed surface of the bed portion and the heat sink. a second resin mold layer formed by filling and made of a resin having higher thermal conductivity than the resin of the first resin mold layer; 1. A resin-sealed semiconductor device comprising a lead disposed within one resin mold layer and electrically connected to an internal terminal on the surface of the semiconductor chip.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60134658A JPS61292346A (en) | 1985-06-20 | 1985-06-20 | Resin-sealed semiconductor device |
| KR1019860004702A KR900001833B1 (en) | 1985-06-20 | 1986-06-13 | Packaged semiconductor device |
| DE8686304725T DE3684184D1 (en) | 1985-06-20 | 1986-06-19 | ENCLOSED SEMICONDUCTOR ARRANGEMENT. |
| EP86304725A EP0206771B1 (en) | 1985-06-20 | 1986-06-19 | Packaged semiconductor device |
| US07/334,771 US4924351A (en) | 1985-06-20 | 1989-04-10 | Recessed thermally conductive packaged semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60134658A JPS61292346A (en) | 1985-06-20 | 1985-06-20 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61292346A JPS61292346A (en) | 1986-12-23 |
| JPH0363822B2 true JPH0363822B2 (en) | 1991-10-02 |
Family
ID=15133527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60134658A Granted JPS61292346A (en) | 1985-06-20 | 1985-06-20 | Resin-sealed semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS61292346A (en) |
| KR (1) | KR900001833B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2503029B2 (en) * | 1987-10-06 | 1996-06-05 | 沖電気工業株式会社 | Method for manufacturing thin semiconductor device |
| US5172213A (en) * | 1991-05-23 | 1992-12-15 | At&T Bell Laboratories | Molded circuit package having heat dissipating post |
-
1985
- 1985-06-20 JP JP60134658A patent/JPS61292346A/en active Granted
-
1986
- 1986-06-13 KR KR1019860004702A patent/KR900001833B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61292346A (en) | 1986-12-23 |
| KR900001833B1 (en) | 1990-03-24 |
| KR870000753A (en) | 1987-02-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |