JPH0363263B2 - - Google Patents

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Publication number
JPH0363263B2
JPH0363263B2 JP57148424A JP14842482A JPH0363263B2 JP H0363263 B2 JPH0363263 B2 JP H0363263B2 JP 57148424 A JP57148424 A JP 57148424A JP 14842482 A JP14842482 A JP 14842482A JP H0363263 B2 JPH0363263 B2 JP H0363263B2
Authority
JP
Japan
Prior art keywords
phase
phase difference
circuit
sample
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57148424A
Other languages
Japanese (ja)
Other versions
JPS5937757A (en
Inventor
Junji Namiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57148424A priority Critical patent/JPS5937757A/en
Publication of JPS5937757A publication Critical patent/JPS5937757A/en
Publication of JPH0363263B2 publication Critical patent/JPH0363263B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/233Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2332Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は位相変調信号の復調器に関る。 位相変調信号の復調には特性の優れた同期検波
が専ら用いられているが、検波の際、送信搬送波
と同一の参照搬送波が必要である。この為、同参
照搬送波が受信側で再生される様に、情報を送信
する前に送信側から送信搬送波だけを一定期間送
信するのが普通である。そして、その後、受信側
で参照搬送波が準備された後、はじめて位相変調
信号が送信されることになる。送信側が送信搬送
波を送出する時間は全く情報伝送から見れば無駄
時間であるので、これは短かい程良いと言うこと
になる。そこで受信側の参照搬送波発生器(搬送
波再生回路)はかなり広い帯域の同期系を用意
し、比較的短いアクジシヨン時間で、搬送波同期
を完了させることになる。帯域の広さは情報受信
時には入力雑音の影響を受ける結果を招き、サイ
クル・スリツプの多発に見まわれることになる。 本発明の目的は、無駄情報と言うべき送信側か
らの搬送波信号を受けることなしに、しかも入力
雑音の影響も受けにくい狭帯域の位相同期系を用
いて位相変調信号を復調しようとするものであ
る。 この発明はK相位相変調された入力信号に対
し、該入力信号キヤリアと固定発振器出力との位
相差を検出する位相差検出器と、該位相差検出器
出力をシンボル・レートでサンプルしP1からPN
までN個のサンプル値を得るサンプル回路と、Pi
とPi-1(2≦i≦N)との位相変化Diを法(モジ
ヨロー)2π/Kで求め、これを順次P1に加え累積
値Ai=P1ij=2 Djを得る位相変動検出器と、前記
累積値Aiから、サンプル値系列Piの初期位相差θ0
と、位相差増加速度Δωとを算出する位相差推定
回路と、該位相差推定回路出力と入力系列Piとか
ら搬送波位相同期のとれた復調信号を得る位相差
吸収回路とを、備えたことを特徴とする位相変調
復調器である。 次に本発明に付いて図面を参照して詳細に説明
する。 第1図1〜6は0−π位相の2相変調波を送信
搬送波とΔωrad/s異る受信側参照搬送波に対
して位相差検出を複素数表示で行つた時の復調出
力を示している。同参照搬送波は送信搬送波とθ0
なる初期位相差が存在するものとする。この2相
変調波を正しく復調する為には、Δωとθ0とを正
確に推定し、図に示された復調信号に対し−
(Δωt+θ0)なる位相補正を行う必要がある。第
1図の1から6はシンボル送信周期T(秒)間隔
で復調信号をサンプルしたものであるので、第1
図1と2との位相差θDがそのままΔωTとなつて
いる。従つてΔωはθD/Tとして求められる。2
と3との位相差も0−π変調が掛つていない場合
にはθDと等しくなる所であるが、この場合には
(θD+π)となつている。同様に3と4,4と5,
5と6も変調による位相変化が重畳されている。
各サンプル間の変調による位相変化は必ず正確に
±πである。そこで連続するサンプル間の位相変
化の内、±πの変化は変調によるものとして、減
じて考えることによつて本来のΔωTが観測でき
る。一般にK位相変調信号に対しては、変調によ
る位相変化は2π/K(rad)であるので、送受信相
互の搬送波周波数差による本来の位相変化は連続
するサンプル間の位相変化を2π/Kラジアンの法
(モジユロー演算;位相変化を2π/Kラジアンで割
つた余り)をとることにより求めることができ
る。この位相変化をDとする。 今、N個の複素表示位相誤差値のサンプル値を
Xiで表わしXiとXi-1とのモジユロー2π/Kの位相
差の角位相表示をDi、同じくX1のモジユロー2π/
Kの角位相表示をD1とすると Aiij=2 Dj+X1 ……(1) は搬送波周波数ずれにより、受信側で観測された
受信信号Xiの位相変化を示していることになる。
第2図は第1図に示した6つのXiから求めたAi
プロツトしたものを示している。第2図が与えら
れると、θ0は直線2000が縦軸を横切る値、また
Δωは直線2000の傾斜であることが分る。 無線通信に於いては、入力雑音を零と考えるこ
とはできないので、各サンプル値Xiも入力雑音の
外乱を受けている。従つてAiも第2図に示す様に
きれいな直線上に並ぶことは期待できない。第3
図はこの様子を示している。この図は(A1,t1)、
(A2,t2)、…(Ai,ti)…(A11,t11)までの11
点より成つている。これらの点をもとにΔωとθ0
を推定することになる。これは全11点に対し、自
乗誤差最少となる直線3000を求る問題になる。同
問題に付いては以下の様な解が知られている。 イントロダクシヨン トウ ニユーメリカル
メソツド アンド フオートラン プログ
ラミング“Introduction to Numerical
Methods and FORTRAN Programming” トーマス リチヤード マツカーラ
Thomas Richard McCalla著 1967年 John Wiley & Sens,Inc。 直線3000を(θ^0+Δ^ωt)と表わすとすると、 なる式でθ^0とΔ^ωの推定値θ^0,Δ^ωが求められる

ここで上式を行列式〓=〓−1・〓と記すとQ−
1は各Xiは等間隔サンプリングを行つているの
で、θ0とΔωを推定するサンプル数Nを固定すれ
ば定数行列になる。従つて行列Rのみを求めれば
良いことが分る。ここでRは非常に単純な形をし
ていてAiとAi・tiの累積値を求めることだけが要
求される。 よつて上式よりθ^0とΔ^ωとが求まれば、各サン
プル値Xiは Xi・ej(-〓^0-〓^〓(tit-t1) ……(3) とすることにより、位相誤差が吸収されたことに
なる。 第4図は以上の原理を具体化した本発明の一実
施例を示すブロツク図である。図中1は位相検波
器で、送信搬送波にかなり近く設定されe-j0t
出力する固定発振器10、複素掛算器11、複素
低減波器12より成つていて複素表示(eje
位相差を検出する。2は位相差検出器の複素出力
のデータのアイ(目)が最も良く開いたタイミン
グで同出力をシンボル・レートでサンプルしX1
からXNまでのサンプル値を時間t1からtNまでの間
で得るサンプル回路、3はサンプル値XiとXi-1
の位相変化の法(モジユロー)2π/Kの角位相表
示Diを求め、これを順次X1の位相角D1に加え累
積値Ai=D1ij=2 Djを得る位相変動検出器、4はij=2 Aiを得る加算器、5は同じくij=2 ti・Aiを得る積
和回路で50の掛算器と51の加算器とから成つてい
る。6は先の第(2)式のQ−1・Rを演算してθ^0
Δ^ωを導出する位相差推定回路で具体的には2行
2列の行列演算回路である。7は第(3)式に示した
搬送波位置誤差を修正する為に位相回転を行なわ
せる位相差吸収回路で、e-j(〓〓(tit-t1)+0)を出力

る演算回路71と同回路出力とXiとの複素積をと
る掛算器70から成つている。8は遅延回路でθ^0
とΔ^ωとがNサンプルからかかつて推定される時
間差を調整する為のものでサンプル値XiをNサン
プル時間遅延させる為のものである。 なお、本実施例では、θ0とΔωの推定だけを行
つたがNが大きくなるに従つて2乗の項、すなわ
ちej〓〓at2の項も影響してくる。この場合には第4
図の実施例の5の積分回路を第5図の様にij=2
Ai・ti 2をも求められる様に変更し、さらに6の位
相差推定回路の演算を
The present invention relates to a demodulator for phase modulated signals. Although synchronous detection with excellent characteristics is exclusively used for demodulating phase modulated signals, a reference carrier that is the same as the transmission carrier is required during detection. For this reason, it is common for the transmitting side to transmit only the transmission carrier wave for a certain period of time before transmitting information so that the same reference carrier wave can be reproduced on the receiving side. Then, after a reference carrier wave is prepared on the receiving side, the phase modulation signal is transmitted for the first time. Since the time it takes for the transmitting side to send out a transmission carrier wave is completely wasted time from the perspective of information transmission, so the shorter it is, the better. Therefore, the reference carrier generator (carrier regeneration circuit) on the receiving side prepares a synchronization system with a fairly wide band, and completes carrier synchronization in a relatively short acquisition time. The wide bandwidth results in the reception of information being affected by input noise, resulting in frequent cycle slips. An object of the present invention is to demodulate a phase modulated signal using a narrowband phase synchronization system that is not susceptible to input noise and without receiving a carrier wave signal from the transmitting side, which can be called useless information. be. This invention includes a phase difference detector that detects a phase difference between the input signal carrier and a fixed oscillator output for a K-phase phase modulated input signal, and a phase difference detector that samples the output of the phase difference detector at a symbol rate . from P N
A sample circuit that obtains N sample values up to P i
Find the phase change D i between and P i-1 (2≦i≦N) using the modulus 2π/K, and add this sequentially to P 1 to get the cumulative value A i = P 1 + ij=2 D j , and from the cumulative value A i , the initial phase difference θ 0 of the sample value series P i
and a phase difference estimating circuit that calculates a phase difference increasing rate Δω, and a phase difference absorbing circuit that obtains a demodulated signal with carrier phase synchronization from the output of the phase difference estimating circuit and the input sequence P i . This is a phase modulation demodulator characterized by: Next, the present invention will be explained in detail with reference to the drawings. 1 to 6 show demodulated outputs when phase difference detection is performed in complex numbers for a two-phase modulated wave of 0-π phase with respect to a receiving side reference carrier that is different from the transmitting carrier by Δω rad/s. The same reference carrier wave is the transmission carrier wave and θ 0
It is assumed that there exists an initial phase difference such that In order to correctly demodulate this two-phase modulated wave, it is necessary to accurately estimate Δω and θ 0 , and to calculate −
It is necessary to perform phase correction of (Δωt+θ 0 ). 1 to 6 in FIG. 1 are demodulated signals sampled at symbol transmission intervals T (seconds), so the first
The phase difference θ D between FIGS. 1 and 2 is unchanged as ΔωT. Therefore, Δω is obtained as θ D /T. 2
The phase difference between Similarly, 3 and 4, 4 and 5,
Phase changes due to modulation are also superimposed on signals 5 and 6.
The phase change due to modulation between each sample is always exactly ±π. Therefore, among the phase changes between successive samples, the change of ±π is considered to be due to modulation, and by subtracting it, the original ΔωT can be observed. Generally, for a K-phase modulated signal, the phase change due to modulation is 2π/K (rad), so the original phase change due to the carrier frequency difference between the transmitter and the receiver is the phase change between successive samples of 2π/K radian. It can be obtained by taking the modulus (modulo operation; the remainder when the phase change is divided by 2π/K radians). Let this phase change be D. Now, the sample values of N complex display phase error values are
Expressed by X i, the angular phase representation of the phase difference modulo 2π/K between X i and X i-1 is D i , and the modulo 2π/ K of X i
If the angular phase representation of K is D 1 , A i = ij=2 D j + X 1 ...(1) indicates the phase change of the received signal X i observed on the receiving side due to carrier frequency shift It turns out.
FIG. 2 shows a plot of A i determined from the six X i shown in FIG. Given FIG. 2, it can be seen that θ 0 is the value at which straight line 2000 intersects the vertical axis, and Δω is the slope of straight line 2000. In wireless communication, input noise cannot be considered to be zero, so each sample value X i is also subject to input noise disturbance. Therefore, A i cannot be expected to line up on a clean straight line as shown in Figure 2. Third
The figure shows this situation. This figure shows (A 1 , t 1 ),
11 up to (A 2 , t 2 ), ... (A i , t i ) ... (A 11 , t 11 )
It is made up of points. Based on these points, Δω and θ 0
will be estimated. This is a problem of finding the straight line 3000 that minimizes the squared error for all 11 points. The following solutions to this problem are known. Introduction to Numerical Method and Fortran Programming “Introduction to Numerical”
Methods and FORTRAN Programming” Thomas Richard Matsukala
Written by Thomas Richard McCalla 1967 John Wiley & Sens, Inc. If the straight line 3000 is expressed as (θ^ 0 + Δ^ωt), then Estimated values θ^ 0 and Δ^ω of θ^ 0 and Δ^ω can be obtained using the following equations.
Here, if we write the above equation as the determinant 〓=〓-1・〓, then Q-
1 performs sampling at equal intervals for each X i , so if the number N of samples for estimating θ 0 and Δω is fixed, it becomes a constant matrix. Therefore, it can be seen that only the matrix R needs to be determined. Here, R has a very simple form, and only the cumulative value of A i and A i ·t i is required. Therefore, if θ^ 0 and Δ^ω are found from the above formula, each sample value X i is set as X i・e j(- 〓^ 0- 〓^〓 (tit-t1) ……(3) This means that the phase error has been absorbed. Figure 4 is a block diagram showing an embodiment of the present invention embodying the above principle. In the figure, 1 is a phase detector, which It consists of a fixed oscillator 10 that is set close to e -j 〓 and outputs 0t , a complex multiplier 11, and a complex wave reducer 12, and a complex display (e je detects the phase difference. 2 is a phase difference detector Sample the complex output at the symbol rate at the timing when the eye of the data of the complex output is most open .
A sample circuit obtains sample values from t to Phase variation detector which calculates i and sequentially adds this to the phase angle D 1 of X 1 to obtain the cumulative value A i = D 1 + ij=2 D j , 4 is addition to obtain ij=2 A i The unit 5 is a product-sum circuit that similarly obtains ij=2 t i ·A i , and it consists of 50 multipliers and 51 adders. 6 calculates Q-1・R in equation (2) above and calculates θ^ 0 ,
The phase difference estimating circuit that derives Δ^ω is specifically a matrix calculation circuit with 2 rows and 2 columns. 7 is a phase difference absorption circuit that performs phase rotation to correct the carrier wave position error shown in equation (3), and an arithmetic circuit 71 that outputs e -j( 〓〓 (tit-t1)+0). It consists of a multiplier 70 that takes the complex product of the circuit output and X i . 8 is a delay circuit and θ^ 0
and Δ^ω are used to adjust the time difference previously estimated from N samples, and are used to delay the sample value X i by N sample time. In this embodiment, only θ 0 and Δω are estimated, but as N becomes larger, the square term, that is, the term e j 〓〓 at2 also becomes influential. In this case, the fourth
The integration circuit of Example 5 in the figure is as shown in Figure 5 ij=2
Change A i・t i 2 so that it can also be calculated, and further calculate the phase difference estimation circuit in step 6.

【表】 〓 〓 〓 〓〓 〓
の様に変更するだけでよい。この場合も、もちろ
ん行列Q−1は定数行列である。この時、演算回
路71の出力もe-j(〓〓2(ti-t1)2+〓〓(ti-t1)+0)
変更され
ることは言うまでもない。 また1の位相検波器も複素表示(eje)での出
力に代つて0〜2πまでの角位相表示の出力のも
のを採用すれば、複素表示から角位相表示への変
換が不用になり利点も多い。
[Table] 〓 〓 〓 〓〓 〓
Just change it like this. In this case as well, the matrix Q-1 is of course a constant matrix. At this time, it goes without saying that the output of the arithmetic circuit 71 is also changed to e -j( 〓〓 2(ti-t1)2+ 〓〓 (ti-t1)+0) . In addition, if the phase detector in step 1 uses an output with an angular phase representation from 0 to 2π instead of an output with a complex representation (e je ), there will be no need to convert from a complex representation to an angular phase representation. There are many advantages as well.

【図面の簡単な説明】[Brief explanation of drawings]

第1図1〜6は2相PSKの送受搬送波の周波
数ずれによる位相回転の様子を説明する為の図。
第2図、第3図は同周波数ずれによる位相変化を
時間を横縦に示した図であり、第3図は第2図に
対して入力雑音を考慮した時の図、第4図は本発
明の一実施例のブロツク図を示す図である。 図中、1……位相差検出器、2……サンプル回
路、3……位相変動検出器、4……加算器、5…
…積和回路、6……位相差推定回路、7……位相
差吸収回路を各々示す。また第5図はΔω2・t2
項による誤差をも検出する為に、前記5の積和回
路を変更したもの。
FIGS. 1 to 6 are diagrams for explaining the state of phase rotation due to frequency deviation of transmitting and receiving carrier waves in two-phase PSK.
Figures 2 and 3 are diagrams showing phase changes due to the same frequency shift horizontally and vertically, Figure 3 is a diagram when input noise is considered compared to Figure 2, and Figure 4 is a diagram of the main 1 is a diagram showing a block diagram of an embodiment of the invention. FIG. In the figure, 1... Phase difference detector, 2... Sample circuit, 3... Phase fluctuation detector, 4... Adder, 5...
. . . product-sum circuit, 6 . . . phase difference estimation circuit, 7 . . . phase difference absorption circuit, respectively. In addition, Fig. 5 shows a modification of the product-sum circuit in 5 above in order to detect errors due to the term Δω 2 ·t 2 as well.

Claims (1)

【特許請求の範囲】 1 K相位相変調された入力信号に対し、該入力
信号キヤリアと固定発振器出力との位相差を検出
する位相差検出器と、該位相差検出器出力をシン
ボル・レートでサンプルしP1からPNまでN個の
サンプル値を得るサンプル回路と、PiとPi-1(2
≦i≦N)との位相変化Diを法(モジヨロー)2
π/Kで求め、これを順次P1に加え累積値Ai=P1
ij=2 Djを得る位相変動検出器と、前記累積値Ai
ら、サンプル値系列Piの初期位相差θ0と、位相差
増加速度Δωとを算出する位相差推定回路と、該
位相差推定回路出力と入力系列Piとから搬送波位
相同期のとれた復調信号を得る位相差吸収回路と
を、備えたことを特徴とする位相変調復調器。
[Claims] 1. A phase difference detector for detecting a phase difference between the input signal carrier and a fixed oscillator output for a K-phase phase modulated input signal; A sample circuit that samples and obtains N sample values from P 1 to P N , and P i and P i-1 (2
≦i≦N) and the phase change D i is modulo 2
Find it as π/K and add it to P 1 in order to get the cumulative value A i = P 1 +
a phase variation detector that obtains ij=2 D j ; a phase difference estimation circuit that calculates an initial phase difference θ 0 and a phase difference increasing rate Δω of the sample value series P i from the cumulative value A i ; A phase modulation demodulator comprising: a phase difference absorption circuit that obtains a demodulated signal in carrier phase synchronization from the output of the phase difference estimation circuit and the input sequence P i .
JP57148424A 1982-08-26 1982-08-26 Phase modulating and demodulating device Granted JPS5937757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57148424A JPS5937757A (en) 1982-08-26 1982-08-26 Phase modulating and demodulating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57148424A JPS5937757A (en) 1982-08-26 1982-08-26 Phase modulating and demodulating device

Publications (2)

Publication Number Publication Date
JPS5937757A JPS5937757A (en) 1984-03-01
JPH0363263B2 true JPH0363263B2 (en) 1991-09-30

Family

ID=15452481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57148424A Granted JPS5937757A (en) 1982-08-26 1982-08-26 Phase modulating and demodulating device

Country Status (1)

Country Link
JP (1) JPS5937757A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0773289B2 (en) * 1984-08-09 1995-08-02 日本電気株式会社 Phase demodulator
JPS63252014A (en) * 1987-04-08 1988-10-19 Kokusai Denshin Denwa Co Ltd <Kdd> Phase locked loop system
JP3348661B2 (en) * 1998-10-09 2002-11-20 双葉電子工業株式会社 Carrier phase tracking device and frequency hopping receiver

Also Published As

Publication number Publication date
JPS5937757A (en) 1984-03-01

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