JPH0363109B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data flow rate control circuit that controls data exchange between at least two information processing devices.

Conventionally, when connecting several data flow processing devices, it has been done through a queue memory in order to provide sufficient margin for data exchange between them. However, since the amount of data processed by each data flow processing device is different, it is necessary to focus on the data flow processing device with the largest amount of processing and use software to control the performance of other data flow processing devices. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that can automatically transfer data between data flow processing devices without the aid of software control in accordance with the data flow processing device that has the largest processing capacity.

For example, when calculating equation (1) with ui = xi + yi × zi vi = xi − yi × zi ... (1) (where i = 1, ... n), information processing device A calculates xi, yi, zi. The data are sequentially sent to the information processing device B, and the information processing device B shows the calculation results ui and vi to the data flow processing device A. At this time, three data sets are transferred as a unit from information processing device A to B n times, and two data sets are transferred as a unit from information processing device B to A n times. In the data flow rate control circuit of the present invention, we focus on one element of a data set as a unit, for example, zi and vi, and zi is from information processing device A to B.
By constantly monitoring the absolute value of the difference between the number of times vi has been sent to A and the number of times vi has been sent from information processing device B to A, and ensuring that the absolute value of the difference does not exceed a certain number, Prevent data inflow that exceeds processing capacity. Also, the three types of data xi, yi, and zi have different identifiers such as '0', '1', and '2'.
Different identifiers such as '0' and '1' values are given to the two types of data, ui and vi. As a result, in the above example, among the data transferred from information processing device A to B,
It is sufficient to count the number of transfers of data having an identifier having a value of 2' and the number of transfers of data having an identifier having a value of ``1'' among the data transferred from information processing device B to A.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. From information processing device 1 to information processing device 2
When there is data to be given to the queue memory 100 with FIFO function (for example, MMI
C67401) has a data storage area, and if a data acceptance signal is output to the signal line 102, the information processing device 1 outputs data consisting of a data identifier and a data value to the data line 101, and the queue memory 100 Save this data temporarily.
Data temporarily stored from the queue memory 100 is read out to the data line 103, and the data identifier is read out to the table memory 11 through the data line 104.
0 is accessed, the new data identifier is read out on the data line 106, and the increment monitoring bit is read out on the signal line 114. Both the data value applied to the data line 105 and the new data identifier applied to the data line 106 are applied to the information processing device 2 through the data line 107. Data input from the information processing device 2 through the data line 111 is provided as is to the information processing device 1 through the data line 118. Among the data on the data line 118, the data identifier is passed through the data line 112 to the memory 12.
0 is accessed and a decrement monitoring bit is output to the signal line 113. The counter 130 increases by 1 when the increase monitoring bit is output to the signal line 114, and the counter 130 increases by 1 when the increase monitoring bit is output to the signal line 114.
When the decrement monitoring bit is output to 3, it decreases by 1.
The absolute value of the counter 130 is output to the data line 115, and compared with the output of the register 150 by the comparator 140. When the value of the data line 115 is smaller than the value of the data line 116, '1' is sent to the signal line 117.
The value of is output. When the information processing device 2 is ready to receive data, a value of '1' is output to the signal line 108, and the output signal line 109 of the AND circuit 160, which outputs a value of '1' to the signal line 117, is '1'. Takes the value 1'. The queue memory 100 continues reading when a value of '1' is output to the signal line 109.
In this embodiment, the output section corresponds to the queue memory 100, and the output control section corresponds to block 3 indicated by a broken line.

FIG. 2 is a block diagram showing another embodiment of the present invention.

This embodiment shows an example in which two information processing apparatuses control mutual data exchange.

When there is data to be given from the information processing device 11 to the information processing device 10 and the flow rate control circuit 20-1 is outputting a data acceptance state to the data line 70-1, the information processing device 11 sends the data identifier and data. The data consisting of the value is output to the data line 50-2. Data identifiers are given to distinguish data, and the information processing device 10 performs different processing for each identifier. The data inputted from the data line 50-2 is added with an increment monitoring bit according to the identifier by the flow rate control circuit 20-2, and inputted to the flow rate control circuit 20-1 through the data line 30-1, where the data is temporarily stored. In the flow control circuit 20-1, the data input from the data line 30-1 and the data line 50
-1 to monitor the data input from the information processing device 1.
0 to the signal line 60-1, the temporarily stored data is provided to the information processing device 10 through the data line 40-1. A similar procedure is followed when data is provided from the information processing device 10 to the information processing device 11. The flow rate control circuits 20-1 and 20-2 are configured with the same circuit.

FIG. 3 is a block diagram specifically showing the flow rate control circuit 20-1.

When data is input from the data line 50-1,
The table memory 204 is accessed using the data identifier, and the decrease monitoring bit is sent to the signal line 256, the signal line 25
5 and outputs an increment monitoring bit to data line 50-1.
The input data and the increase monitoring bit on the signal line 255 are passed through the data line 3 to the flow rate control circuit 20 in FIG.
-Give to 2. When the decrement monitoring bit on the signal line 256 has a value of '1', the counter 202 is decremented by one. The increase monitoring bit and data from the flow rate control circuit 20-2 of FIG. 2 inputted to the data line 30-1 are temporarily stored in the queue memory 200. When data can be stored in the queue memory 200, a data acceptance state is output to the information processing device 11 in FIG. 2 through the signal line 70-1. The increase monitoring bit read from the queue memory 200 passes through the signal line 251 to increment the counter 202 by 1, and the data passes through the data line 40-1 to the information processing device 1 in FIG.
given to 0.

The absolute value of the counter 202 is output to the data line 257, and the comparison circuit 203 compares it with the value of the register 201. When the value on the data line 258 is greater than the value on the data line 257, a value of '1' is output to the signal line 259, and otherwise a value of '0' is output.

From the information processing device 10 in FIG. 2, the signal line 60-
A data input enable state is input through 1, and the value of the signal line 259 and the signal line 60 are input through the AND circuit 205.
The logical product with the value of is taken and outputted to the signal line 260. That is, the value of the register 201 is the value of the counter 202.
When the data input enable state is output to the signal line 60-1, the absolute value of ' is greater than the absolute value of '.
A value of 1' is output and data is read from the queue memory 200.

Note that the register 201 and table memory 204
Although initial data is set in advance in the register 201, it is also possible to use a read-only memory as a constant generator and table memory 204 instead of the register 201.

When data processing is performed by two or more information processing devices using the data flow rate control circuit of the present invention, the processing status of each information processing device is monitored,
The processes are synchronized with each other and freed from software control.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the data flow rate control circuit of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram of the flow rate control circuits 20 and 21 of FIG. It is a detailed view. In the figure, 1, 2, 10, 11 are information processing devices, 20, 21 are flow rate control circuits, 100, 200
1 is a queue memory, 110 and 204 are table memories, 120 is a memory, 130 and 202 are counters, 140 and 203 are comparators, 150 and 201 are registers, and 160 and 205 are AND circuits.

Claims (1)

[Claims] 1. In data exchange between at least two information processing devices A and B that handle data consisting of an identifier and a data value, data input from information processing device A is held, and the held data is output to information processing device B. an output unit including a FIFO to calculate the data given from the information processing device B to the information processing device A by focusing on the identifier of the data;
The data outputted from the output unit to the information processing device B is counted by focusing on the data identifier, and
1. A data flow rate control circuit comprising: an output control section that controls output from the output section so that a difference between different types of count values does not exceed a certain value.