JPH0359477A - Inspection device for integrated circuit - Google Patents

Abstract

PURPOSE:To inspect a function with simple constitution by providing a means for generating an inspection signal and a 1st reference signal corresponding to the inspection signal, a means for outputting a 2nd reference signal by inputting the 1st reference signal and a means for comparing both signals. CONSTITUTION:A device 1 is constituted of a test pattern generator 1a, the comparison means 1b and a decision means 1c and an integrated circuit element DUT 2 being an object to be inspected incorporates a 1st signal conversion means DAC 2a for converting the 1st kind of digital signal to the 2nd kind of analog signal. The inspection signal and the 1st reference signal which corresponds to the inspection signal and is more accurate are generated by the generator 1a, then the former is impressed on the DUT 2 from an input test pattern generator 3 and the latter is impressed on the means 1b from an expected value pattern signal generator 4 respectively. The means 1b compares the output signal from the DUT 2 with the latter and the means 1c decides the propriety of the situation of an action. Thus, the inspection is performed with high accuracy with the simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated circuit testing device. More specifically, the present invention relates to an integrated circuit testing device that includes a built-in digital and 'analog converter.

Conventional technology Recently, tl! Semiconductor users, such as equipment manufacturers, have their own 06
! By equipping our own products with dedicated integrated circuits with
In order to differentiate ourselves from other companies, pursue first-mover advantage, and overcome non-price competition such as ensuring high performance and confidentiality, the need for specialized integrated circuits that are compatible with systems, so-called custom ICs, is increasing.

On the other hand, with advances in process technology and design technology, semiconductor manufacturers are increasingly using digital circuits. /Achieved a dramatic increase in the scale of tATI, such as by incorporating analog circuits, to meet the demands of users. The increase in integrated M4JlX has recently led to the appearance of LSIs that house digital-to-analog converters (hereinafter referred to as DACs) in the same chip as other devices, and have become widely used. .

FIG. 4 is a block diagram showing an example of the internal configuration of an LSI including a DAC. LSIII is an arithmetic unit (A L
U>12a, control unit (CO) 12b,
Timing circuit 1 including register group 12C and oscillator
The central processing unit (CPtl12) formed by 2 (1, etc.) is the core, and the peripheral input/output data, internal data, instructions (
Instruction) code 1 stores memory (ROM > unit 13, synchronous serial I10 port (SIO) 14, liquid crystal driver 15 that drives a liquid crystal display array (not shown), input/output port 16, etc. Various circuits, a bus 18 formed by a plurality of signal lines, etc. are arranged, and a DAC 17 is arranged integrally with the above circuits, so that an LSIII is formed into one piece.

In the LSIII package, multiple input/output terminals (not shown) are arranged in bins, and the analog output terminal of the DAC 17 is also drawn out, but the operation of the DAC 17 itself is under the control of the CPU 12, and the conversion Digital data is given via register 12 () and DAC 17
The independent data input terminal is not drawn out to the outside of the luggage gauge.

Problems to be Solved by the Invention Up until now, LSIII has been classified into two categories: digital and analog, and the testing of the operating status of the a-product circuit (hereinafter referred to as functional testing) carried out by manufacturers has also been conducted in analog LSIs. For commercial and digital LSIs, testing equipment suitable for each field was used. A functional test is also called a function test, and is one of the important tests, as it checks whether the LSI to be tested satisfies the functions described in the specifications.

However, as mentioned above, the LSI with built-in AC17
Functional testing requires handling both digital and analog signals at the same time, so if you only have digital LSI testing equipment, for example, you need to set testing data such as input codes, and then use the DC level test function. Therefore, the processing time increases due to multi-point inspection and measurement, and the measurement accuracy of the DC level test function is not sufficiently high compared to the accuracy of the DAC being tested, resulting in a decrease in inspection accuracy. There were some problems.

However, a method has been proposed in which analog LSI testing equipment is used in conjunction with the test equipment, but there are problems with the installation space of the testing equipment, the cost is high, and analog testing equipment has problems such as insufficient number of bins depending on the LSI. Is it possible that the measurement status cannot be set? There is a point I'IM.

On the other hand, L that supports analog//digital mixed type
Although SI testing equipment is used, these four companies have had the undesirable problem that the testing equipment itself is expensive, increases equipment costs, and requires 100% replacement of the product LSI testing equipment.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide an integrated circuit testing device that can perform functional testing of an integrated circuit to be tested with a simple configuration.

Means for Solving the Problems The invention as set forth in claim 1 inspects the operating status of an integrated circuit provided with a first signal conversion means for converting an input first type of signal into a second type of signal. In an integrated circuit testing device, a test signal belonging to the first type given to the integrated circuit, and a test signal corresponding to the test signal and belonging to the first type with higher accuracy than the test signal, Signal generation means configured to form and derive a first reference signal having a predetermined reference (q difference amount); A second signal converting means outputs a second reference signal belonging to the second type '4-B.

Comparing means detects a deviation amount by comparing the first signal conversion manual output and a second reference signal, and the 4A product is calculated based on the deviation amount detected by the comparing means and the reference deviation amount. This is an integrated circuit testing device characterized by testing the accuracy of circuit operation.

The invention according to claim 2 provides a 4A integrated circuit testing device for testing the accuracy of operation of an integrated circuit, which includes a first signal conversion means for converting an input first type force signal into a second type signal. .

A first test signal belonging to the first type given to the 4A product circuit; a signal generating means for creating and deriving a reference signal having a predetermined standard (amount of deviation); and converting the output of the first signal converting means into a second test signal belonging to the first type with the same accuracy as the reference signal. an integrated circuit testing device, characterized in that: a reference signal and a second testing signal are input, and the integrated circuit J)'tl# is tested based on the magnitude relationship between the reference signal and the second testing signal. It is.

According to the invention set forth in claim 1, a test signal and a first reference signal are generated from the signal generating means and inputted to the t&product circuit to be tested and the second signal converting means, respectively. 1st
The reference signal is more accurate than the test signal and is generated as a signal having a reference width difference with respect to the test signal.

The test signal is converted from a first type signal to a second type force signal by a signal conversion means (2) in the integrated circuit. Also the first
The reference signal is output by the second signal converting means as a second reference signal which has higher accuracy than the output signal from the first signal converting means and also belongs to the second type.

The comparison means detects the amount of deviation between the first signal conversion means and the second reference signal. If this deviation amount is within the range of the reference deviation amount, the first signal '
It is determined that the exchange means is relatively accurate. Further, if the deviation amount is outside the deviation amount range, the first deviation amount is outside the deviation amount range.
It is determined that the signal conversion means has relatively low accuracy.

In this way, the integrated circuit J) dynamic f? The accuracy of is determined.

In this way, the first signal conversion means converts the first type of signal inputted by five people into the second type of signal by the integrated circuit testing device including the plurality of components described above in a single device. PJi'! The operating status of the integrated circuit provided. ! Inspection can be performed with a high precision with a simple configuration.

According to the second aspect of the invention, the signal generating means creates a first test signal and a reference signal and inputs them to the integrated circuit to be tested and the second signal converting means, respectively. The first test signal is converted into a second type of signal by a first signal conversion means in the integrated circuit, and this signal is input to the second signal conversion means to convert the first test signal to a second type of signal with higher precision than the first test signal. A second test signal belonging to the first type is output with the same accuracy as a reference signal having a predetermined standard (4 difference amounts) for the first test signal.

The reference signal and the second test signal are input to a comparison means,
The magnitude relationship between these is determined. Based on this l'1 constant result, when the second test signal is within the range of the standard deviation amount of the reference signal, it is determined that the integrated circuit to be tested has relatively high accuracy; Sometimes it is determined that the accuracy is relatively low.

By means of an integrated circuit testing apparatus integrally equipped with the above-described configuration, the operating status of an integrated circuit equipped with a first signal converting means for converting an inputted signal into a first type of signal can be easily and highly precisely configured. will be inspected.

Embodiment FIG. 1 is a block diagram showing the outline of an integrated circuit testing device (hereinafter referred to as the testing device) 1 according to the present invention. In FIG. The device has a built-in D A C 2a which is a first signal conversion means for converting a digital signal, which is a first type of signal, into an analog signal, which is a second type of signal.

The functional test is the test signal to be applied to the DOT2 and the expected output value of the DOT2 that corresponds to the test signal, has higher accuracy than the test signal, and is assumed to be obtained from the test signal, and is the first standard. An input test pattern signal S1 having a certain time series is sent as a test signal from an input test pattern signal generator 3 of a test pattern generator 1a as a signal generating means for creating and deriving an expected value pattern signal. The expected value pattern signal S2, which is more accurate than the input test pattern signal S1, is applied from the expected pattern signal generator 4 to one input terminal of the comparing means 1b. Comparison means 1 compares the output signal of DOT2 and the expected value pattern signal S2, and determines the operating status)
The quality is determined by the determining means 1 c-7. Test pattern generator 1a, comparison means 1b and determination means 1 (ζ1
An inspection device 1 according to the present invention is configured.

In the function test, test pattern generator 1a or 8 test mode signal S3 is given to DOT2 in advance, and DtJ
Interrupts are disabled in the CPU (central processing unit) 2b in T2, and the input test pattern S1 is set in the register 2c, read out sequentially by CP Ll 2 b and applied to D A C2;t.

FIG. 2 is a block diagram showing a specific example of the electrical configuration of the inspection apparatus 1g) according to an embodiment of the present invention. In Figure 2, the first
Inspection device 1, parts corresponding to the figures are given the same reference numerals.
is a test pattern generator 1a, a comparison circuit 1b which is a comparison means, a judgment circuit 1c which is a judgment means, a programmable power supply 1 (1 and a reference D which is a second signal conversion means).
Admonish from each block of AC1e.

The test pattern generator 1a is the DA C2 in the DOT2.
Multiple pins corresponding to the specifications of a) - <For example, 8 pins)
-) - pattern signal S1 and expected value pattern signal S2 are created, and lines 11 and 1 are created, respectively.
The number of bits forming the 1 expected value pattern signal S2, which is individually derived for each test pattern, is made up of 12 bits, which is 11 bits more than the number of bits of the input test pattern signal S1. That is, the reference DAC1e is DAC2ft
It is a D/'A converter with higher precision than that of the D/'A converter.

The reference DAC 1e converts the expected value pattern signal S2 into a second analog signal A2 and sends it to the comparison circuit 1 via a line 14.
input to one input terminal of b.

The comparator circuit 1b is realized by an operational amplifier or the like, and D A
A first analog signal A1 derived from C2El and a second analog signal A2 derived from said reference DAC1e.
The differential voltage is set to a predetermined amplification degree (for example, 100
line 15 as the comparison output A3.
is applied to the determination circuit 1c via.

The determination circuit 1c is realized by, for example, a lie/doe comparator circuit, and is a circuit that checks whether the comparison output A3 is within a predetermined range and determines whether the characteristics of D[IT2 are appropriate or not.

The programmable electric Jld has the rated power supply voltage of DOT2.
71 (for example, 5.00 V) and the power supply voltage ■2 required for the operation of each block forming the inspection device 1,
This is the power supply unit that supplies each block.

Next, power supply voltage V1=5. D
A functional test of AC2a will be explained based on FIG. Since the resolution is 8 bits), the least significant bit (LSB)
) is: ILSB = (5,00,'2”) = 19.6rn
V −= (1) and the tolerance is ±9.8 mV.

The input test pattern signal S1 inputted from the test pattern generator 1a to DOT2 is, for example, 40 in hexadecimal notation.
If set to H (01000000), this will be received [
) The output voltage of A C2El, that is, the output level of the first analog signal A1, is 19.6X2' = 1254
．． 4 mV ・(2>), that is, upper limit value 1264, 2 rn V, lower ra value 12 J J, 6 m V I>0 In this embodiment, this J ) to test the level range of the first analog signal A1.
l? , 2a is used as a reference D A C1e with a resolution of 12 bits, which is more accurate than that of 2a.

If the power supply voltage V1 of the reference DAC 1e is 5.00\r, which is the same as that of D LI T 2, the voltage level corresponding to the least significant bit (LSB) is: ILSB = <5.00/2") = 1.22 mV
−<3>However−), the input test pattern signal S
The first expected value pattern signal S2 corresponding to the upper limit value of 1264.2rnV is: 1264, J7'1.22 = 1036
...(4> That is, 40CH (010000001
100>, which similarly corresponds to the lower limit value 1244.6rrtV, is 12-IJ,
6/1.22 = 1020...(5>
In other words, 3 F CH (OO1111111100).These groups corresponding to the above upper and lower limit values) Expected value pattern signals S2a and S2b can be generated by the test pattern generator I by specifying the input test pattern signal S1 and the allowable error range. The program is created by CL,
2 to the reference DAC:1e.

Here, it is assumed that for an input of 40H, the first analog signal A1 derived from the DAC 2a is 1245, 4 mV, which is shifted by 9 mV from the center value. Standard DAC
The second analog signal A2 derived from 1e has a lower limit value of 1244.6rnV. However, the comparison circuit 1b
is the difference between the two, 1245.4-12J4.6 = 0.8rnV
...(6>) is detected and the comparison signal A3 a = 80 mV is amplified with an amplification degree of 100.
Derived as follows.

Since the comparison signal A 3 a is larger than Orn V, the determination circuit IC determines that the comparison signal A 3 a is below the lower limit value.

In this embodiment, the determination circuit 1 amplifies the comparison signal A3a for determination to a level that facilitates determination in this way.
C only needs to be able to determine whether the comparison signal A3 is lower or higher than Q m V, and even a circuit with relatively low sensitivity of about 10 m V can make a highly accurate determination.

As described in the conventional example, it is difficult to judge a low level signal of 0.9 mV as described above with high accuracy using the conventional technology.

Next, when data 40CH of the second expected value pattern signal S2 corresponding to the upper @ value is given to the reference DAC1e, the reference DAC
1e outputs 1264.4mV. Comparison circuit 1
b is the first analog signal A 1 (1245, 4rn
■) and the second analog signal A 2 < 1264,
4 mV) difference, 12=15.4-1264.4=
19rnV − (7) Therefore, comparison signal A
3-1.9V is output, and the judgment circuit IC
3 b <: Judged as Om V. In other words, real Mr.
94, the comparison signal A3b output from the comparison circuit 1b
For the upper limit value, 0', )A3a
・=(8) For the lower limit value, 05rA3b
・= (If 9>, it is judged as appropriate.The judgment result is given to the display means (I2I not shown) etc. via (>;8).

FIG. 2 is a block diagram showing the electrical configuration of the present invention J>Other embodiments J) Inspection device 11J). Figure 2 shows 1. .

The inspection apparatus 11 according to the actual example, in which parts corresponding to those in FIG.
The digital converter is hereinafter referred to as ADC>Ig, a comparison circuit 1b that compares the magnitude of individually input digital data, a judgment circuit 1j, and a programmable power supply 1d.
, 7) Each part is overpowered. What should be noted is that in the first embodiment described above, the expected value pattern signal S2 outputted from the test pattern generation circuit 1a is sent to the reference DAC 1e.
is converted into the second analog signal A2, and this and D A (:
In this example, the analog output A1, which is the first test signal of the D A C2a, is reconverted to the digital signal D3, which is the second test signal, by the ADC1g. , and this is compared with the expected value Petter> signal S2).

The turn generator 1a receives an input test pattern signal S1 to be applied to the DLI T2.
Expected value butter> signal S2 is derived to f>12.

The input test pattern signal S1 is formed with S bits, for example, in accordance with the specifications of D Ac1 Ei, and the expected value pattern signal S2 is formed with a bit number 1)5 smaller than that, for example, 12 bits. Ru. The input test pattern signal S1 given to DUT2 is i) A (:
l: The analog signal A is changed by 1 by 2, and the line>
It is input to ADC1g via Z3.

A D C1g divides the analog signal A in L into the same number of bits as the expected value pattern S2, for example, 12 bins)・)f)
It is converted into a digital signal D3 and inputted to one input terminal bO-b1l of the comparator circuit 1h. Comparison circuit 1h
The 12-bit 7-bit data of the expected value pattern signal S2 is input to the other input terminals aO to zt11.

The comparison circuit 1h is realized by a magnicade converter or the like, and compares the magnitude of the input digital signal D3 and the expected value signal S2, and when D3=D2, outputs the output terminal xO. High level I) 3,',::-
D 2 y), the output terminal Xi is set to the f level D
3 F) When 2, output terminal x2 is set to high level.

The determination circuit 1j is connected to the output terminals xO to x2 of the comparison circuit 1h.
By reading these levels derived from −),
Determine the suitability of D A C2a.

Same as the first embodiment, resolution is 8 pins ~, tolerance ±1
,,,,' 2 L S B , power supply voltage s, oov
It is assumed that the DAC 2a is tested at f%. Input test butter〉・When applying signal S 1 = , 40 H,
125-t.

1264, 2-124 J, centered on 4 mV,
A force output of 6 mV is within the compatible range. Test butter>
The generator 1a has an input test pattern signal 5t (40H).
When the allowable error (±1/2LSB) is set, the expected value pattern signal S2 of the upper limit value data 40CH and the lower limit value data 3FCH is automatically programmed.

Manual butter〉D A for signal S 1 = -10H
It is assumed that C2a outputs an analog signal A of 1254.4 mV, which is -9 mV shifted from the central value of 1254.4 mV. This analog signal A is input to ADClg and converted into a 12-bit digital signal D3, which is the same as the expected value pattern S2. The 12-bit data of the digital signal [)3 at this time is 125-1.4. '1.22 = 102
8...(10) That is, 404 H(0
10000000100) is input to the input terminals bO-b11 of the comparison circuit 1tt. The other input terminal aO~3111 of the comparison circuit 111 receives upper limit value data 40CH.
and lower limit value data 3FCH are input as the expected value pattern signal S2.

Comparison circuit 1 tt is data 40 of digital No. 58 D3
Compare ゜4H and the upper limit data 40CH, and find D2・
Since it is the second stage, the output terminal x1 is set to high level. Next, compare it with the lower limit data 3 F CH, D2・D
3, the output terminal x2 is set to high level. In this case, the data of the digital signal D3 exists between the upper limit value and the lower limit value of the expected value pattern S2, so it is determined that the data is compatible.

It is clear that hZ is disqualified if it is D3'·D2 when compared with the upper limit, or D 3 [:t 2 when compared with the lower limit. Also, when comparing the upper limit value)), when D 3 = D 2, the output terminal xO is
When compared with the lower limit value, the output terminal When comparing D3''D2, if the output terminal x2 becomes high level, both are determined to be 6 (3).

In the above embodiment, the expected value pattern signal S2 and the digital signal D3 are composed of 12 bits.
It goes without saying that the inspection accuracy can be further improved if a larger number of bits (for example, 16 bits) is used to correspond to the resolution of AC2;t.

Invention 1) More than Effect J) According to the invention of Claim 1 J), the amount of deviation between them is detected by the detection means, and if this amount of deviation is within the range of the standard deviation amount, the integrated circuit It is determined that the first bow converting means in the first bow conversion means has relatively high accuracy. Also mentioned above (
If the deviation amount is outside the range of 14 difference amounts, it is determined that the first signal conversion means has relatively low accuracy. In this way, the dynamic status of the integrated circuit 1) is determined.

In this way, the integrated circuit testing device including the Pi number of components described above in a single power device converts the input first type of signal into a second type of signal.
! The operational status of an integrated circuit equipped with r:1 negative means can be inspected with a simple configuration and with high accuracy.

According to the invention as claimed in claim 2 (1), the reference signal and the second test signal are manually input to the comparing means, and the magnitude relationship between them is determined. Based on this determination result, when the second test signal is within the range of the standard deviation amount of the reference signal, it is determined that the integrated circuit to be tested has relatively high precision, and when it is outside the range, it is determined that the integrated circuit has relatively high precision. It is judged to be a hit based on accuracy.

With the integrated circuit testing apparatus integrally equipped with the above-described configuration, the dynamic state of the integrated circuit, which includes the first signal converting means for converting the input signal into the first type of signal, can be checked with a simple configuration. It is often inspected with high precision.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of an IJ & integrated circuit testing device 1 according to the present invention, and FIG. 2 is a block diagram showing an outline of an integrated circuit testing device 1 according to an embodiment of the present invention. 2, FIG. 3 is a block diagram showing the electrical configuration of an inspection apparatus ii according to another embodiment of the present invention, and FIG. 11 is a block diagram showing the internal structure of an example of the device to be tested. , chiru. 1.11...Integrated circuit testing device, 1a-...Test pattern generator, 1b, 1h...Comparison circuit, l(,]j
---Judgment circuit, 1d...Programmable power supply, 1e
--Reference digital/analog converter, 2...Device to be tested, 2a...Digital, 'analog converter', A, At, A2...Analog signal, Sl...Input cover turn signal, S2...・・Expected value pattern signal, D3−
...Digital signal O2 Fig. 4

Claims (2)

[Claims] (1) In an integrated circuit testing device for testing the operating status of an integrated circuit, which includes a first signal converting means for converting an input first type of signal into a second type of signal, the above applied to the integrated circuit is provided. A test signal belonging to a first type and a first reference signal that corresponds to the test signal, belongs to the first type with higher precision than the test signal, and has a predetermined standard deviation amount with respect to the test signal are created. a second signal converting means receiving the first reference signal and outputting a second reference signal belonging to the second type with higher accuracy than the output signal from the first signal converting means; , said first
Comparing means for comparing the output of the signal converting means and a second reference signal to detect an amount of deviation, and determining the accuracy of the operation of the integrated circuit based on the amount of deviation detected by the comparing means and the reference deviation amount. An integrated circuit testing device characterized in that it is designed to perform testing. (2) In an integrated circuit testing device for testing the accuracy of the operation of an integrated circuit, which includes a first signal conversion means that converts an input first type of signal into a second type of signal, the integrated circuit is provided with: a first type belonging to the first type;
Creating a test signal and a reference signal that corresponds to the first test signal, has higher accuracy than the first test signal, belongs to the first type, and has a predetermined standard deviation amount with respect to the first test signal. a second signal converting means for converting the output of the first signal converting means into a second test signal belonging to the first type with the same precision as the reference signal; and a reference signal and a second test signal. An integrated circuit testing device characterized in that the accuracy of the integrated circuit is tested based on the magnitude relationships inputted.