JPH0357220A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To remove a difference in level between a protruding part of a substratum layer and the surface of a flattening layer by a method wherein a resist is formed on the flattening layer inside a recessed region at a difference in level of the substratum layer and the flattening layer is etched isotropically by making use of the resist as a mask. CONSTITUTION:After a field oxide film 20 has been formed on a substrate 1, polysilicon 3 is formed on the whole surface of the film 20 by a CVD method. Then, a resist 5 is formed by a spin coating operation; the resist 5 is left only at the inside of a slightly recessed region from a peak part of the film 20 by a photolithographic operation. Then, when the polysilicon 3 is etched isotropically by making use of the resist 5 as a mask, a difference in level between the polysilicon 3 and the film 20 is reduced. After that, the resist 5 is removed; an oxide film 4 is formed. Thereby, an angular edge of the polysilicon 3 is rounded; a difference in level on the surface is almost removed; it is possible to prevent a disconnection of an Al interconnection.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device for planarizing a base layer having a surface step. be.

[Conventional technology]

Basic in the manufacturing process of bibolar LSI! After forming the field oxide film 20 on the Ill, a step was formed on the surface as shown in FIG.

When an AI wiring is formed on the field oxide film 20, if the slope of the surface step is steep, the wiring may be disconnected. Further, on the field oxide film 20, A
When patterning AN wiring by placing a resist on two layers and using photolithography, the pattern dimensions may change due to reflection of light at the step, or the depth of focus may differ between deep and shallow steps, resulting in pattern dimensions. The disadvantage is that it varies. In order to eliminate this drawback, it is possible to apply SOG (M-shaped glass) to the surface of the field oxide film 20, or to apply PSG (S102 containing phosphorus) or BPS.
Conventionally, G (S i0 2 containing phosphorus and boron) is applied to the surface.

FIG. 5 is a cross-sectional view when SOG 30 is applied to the surface. SOG 30 is applied to a part of the surface of the field oxide film 20 to make the slope of the surface step gentle. In this way, A provided on the field oxide film 20
Although the number of disconnections in the I wiring is reduced, the step amount L1 is hardly improved.

Figure 6 shows that PSG40 is formed into field oxide film 2 by heat treatment.
0 is a cross-sectional view when the entire surface of 0 is coated. PSG4
0 is applied to the entire surface to make the slope of the surface level difference gentle and to reduce the amount of the level difference. However, since it requires heat treatment at high temperatures and for a long time, it has an impact on the denocent chair. In addition, the step amount L2 is SO
Although it is improved compared to when G30 is applied, it is not completely improved.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit device is configured as described above, and although the slope of the step has become gentle, the amount of the step has not been improved much. Therefore, when patterning the A2 wiring by photolithography, there is a problem that the pattern dimensions change or vary as described above.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device having no surface steps.

[Means to solve the problem]

A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device for planarizing a base layer having a step on the surface, the method comprising flattening the entire surface of the base layer having a step on the surface. , a step of forming a resist on the planarization layer corresponding to a region slightly narrower than the concave area of the step of the base layer, and a step of forming an isotropic layer on the planarization layer using the resist as a mask. The process includes an etching process and a resist removal process.

[Effect]

In this invention, a resist is formed on the flattening layer corresponding to an area slightly narrower than the concave area of the step of the base layer, and the flattening layer is isotropically etched using this resist as a mask. There is no difference in level between the convex portion and the surface of the flattened layer subjected to isotropic etching.

〔Example〕

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor integrated circuit device according to the present invention, and shows a cross-sectional view around an isolation region of a bibolar LSI. A field oxide film 20 is formed from S t 0 2 so as to cover the surface of the substrate 1 that covers the element formation region 2 . Field oxidation II! 20 has a step. In the recessed region A of the field oxide film 20, polysilicon 3 is formed which serves as a flattening layer to eliminate steps. A {V planarized oxide film 4 is formed on the polysilicon 3 and the field oxide film 20.

A method for manufacturing the conductor integrated circuit device shown in FIG. 1 will be explained using FIGS. 28 to 2E. A field oxide film 20 is formed by selectively oxidizing a predetermined region on the substrate 1 . At this time, the field oxide film 20 has a stepped shape (FIG. 2A). Next, polysilicon 3 is formed on the entire surface of field oxide film 20 by the CVD method (FIG. 2B). Next, a resist 5 is formed on the polysilicon 3 by spin coating, and then by photolithography so that the resist 5 remains on an area slightly narrower than the concave area A of the field oxide film 20 (FIG. 2C). That is, a mask used in photolithography whose end is slightly (1.0 μm or less) inside the concave area A from the peak part of the field oxide film 20 is used, and B shown in FIG. 2C is 1.
The resist 5 is shaped to have a thickness of 0 μm or less. This is to prevent a difference in level between the field oxide film 20 and the etched polysilicon 3 when the polysilicon 3 is subjected to isotropic etching, which will be described later.

Next, the resist 5 is patterned as shown in FIG. 2C.
Isotropically etching is performed on polysilicon 3 using as a mask. Then, there is almost no difference in level between the polysilicon 3 and the field oxide film 20 after isotropic etching (FIG. 2D). After that, the resist 5 is removed and the All wiring is formed, but since the polysilicon 3 is a conductor,
AI wiring cannot be formed directly on the polysilicon 3. Therefore, the surface is oxidized again to form an oxide film 4 on the surface of the polysilicon 3, which serves as an insulator.

By shaping the oxide film 4, the angular edges of the polysilicon 3 (FIG. 2D) are rounded, and the surface level difference is further reduced (FIG. 2E).

Since there are almost no surface steps as described above, even if the A1 wiring is formed on the oxide film 4, there will be no disconnection. In addition, when patterning AI wiring using photolithography, pattern dimensions do not change due to reflection of light at step portions, and pattern dimensions do not vary due to differences in sunspot depth between deep and shallow step portions. .

FIG. 3 is a sectional view showing another embodiment of the invention. In this example, when a plurality of flat wirings are provided as lower layer wirings and upper layer wirings are provided on top of them (when performing double layer wiring), the surface level difference caused by providing the lower layer wirings is Similar to the embodiment, polysilicon 3 is used to eliminate this. A2 wirings 51a and 5lb are formed on the oxide film 50 in a parallel positional relationship to each other. AI wiring 51
An oxide film 52 is formed on the oxide film 50 and the oxide film 50. In this case, AI wiring 51a, 51 . rr of b: Due to the presence of the oxide film 52, the oxide film 52 has a stepped shape. Oxide film 52
Polysilicon 3 is formed in the concave area A so as to fill the concave area A and eliminate the step. An oxide film 54 is formed to cover the oxide film 52 and the borin silicon 53. The surface of the oxide film 54 is flat because the polysilicon 3 is provided thereon. In this embodiment as well, the polysilicon 3 is used to eliminate surface steps, so that when an AN wiring is formed on the oxide film 54, the same effect as in the above embodiment can be obtained. Note that the manufacturing process of providing polysilicon 3 in the concave region A of oxide film 52 and then forming oxide film 54 is as follows:
The steps are similar to those shown in FIGS. 2B to 2E.

In the above embodiments, improvement of the step difference on the field oxide film 20 and the step difference that occurs during two-layer wiring has been described, but the present invention is not limited to these cases, but can be applied to all locations where the step difference occurs.

Further, in the above embodiment, a case was explained in which polysilicon 3 was used as a flattening layer for surface flattening, but other materials may be used.

Further, when the planarization layer is a non-conductor, it is not necessary to provide the oxide films 4 and 54 shown in FIGS. 2E and 3.

〔Effect of the invention〕

As described above, according to the present invention, a resist is formed on the planarization layer corresponding to an area slightly narrower than the recessed area of the step of the base layer, and isotropic etching is performed on the planarization layer using this resist as a mask. Therefore, there is no difference in level between the convex portion of the base layer and the surface of the flattening layer subjected to isotropic etching. Therefore, even if wiring is provided on the surface, there is no risk of disconnection. Further, even if patterning of the wiring is performed by photolithography, there is an effect that the pattern dimensions do not change or vary.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the semiconductor integrated circuit device according to the present invention, FIGS. 28 to 2E are views showing the manufacturing process of the semiconductor integrated circuit device according to the present invention, and FIG. FIGS. 4 to 6 are cross-sectional views showing other embodiments of the semiconductor integrated circuit device according to the invention, and FIGS. 4 to 6 are cross-sectional views showing conventional semiconductor integrated circuit devices. In the figure, 1 is a substrate, 3 is polysilicon, 5 is a resist, and 20 is a field oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor integrated circuit device for planarizing a base layer having a step on the surface, the step of forming a flattening layer for surface flattening over the entire surface of the base layer having a step on the surface. a step of forming a resist on the planarization layer corresponding to a region slightly narrower than a concave region of the step of the base layer; a step of isotropically etching the planarization layer using the resist as a mask; A method of manufacturing a semiconductor integrated circuit device, comprising the step of removing the resist.