JPH0353346A - Logic simulation system - Google Patents

Abstract

PURPOSE:To shorten the overall simulating time by preparing a board containing a corresponding real chip to each real chip type component element and actuating en bloc and at one time the real chips in a simulation process at occurrence of an event. CONSTITUTION:In a simulation process 101, an event E1 occurs in response to the rise of a clock. A board 104 containing plural real chips outputs the value of a prescribed address bus and the prescribed decoding result of an address decoder 403. These output results are sent to the process 101. In this process 101, the events E2 and E3 are produced in response to a valid address bus and an output enable state of the decoder 403. Then a real chip seimulating action is carried out to a relevant instruction fetch cycle in the same procedure. As a result, the simulating time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation method, and more particularly to a logic simulation method that performs logic simulation for a given logic circuit while operating an actual chip.

[Conventional technology]

Logical simulation (hereinafter abbreviated as simulation)
As the scale and complexity of logic circuits to be simulated has become larger and more complex, various new logic simulation methods have been developed. One conventional technique for this purpose is a logic simulation method that has a function of simulating while operating a real chip (hereinafter abbreviated as "actual chip simulation").

Real-chip simulation is effective in simulating logic circuits that include components that have already been made into actual chips, such as microcomputer systems.
No software functional description is performed for the above-mentioned constituent elements; in the simulation, only a model of the logical function of the above-mentioned constituent elements is used. This is done by actually operating the corresponding real chip.

FIG. 3 shows the logical block structure of the conventional logic simulation method when performing actual chip simulation. In Figure 3, 101 is the simulation
102 is a real chip control process, 103 is an input event storage means for the real chip, 304 is a real chip, and 105 is an output result sampling means from the real chip.

Of these, the simulation process 101 is software that performs a simulation by performing predetermined logical operations from a given logic circuit and input button, and all normal simulations that do not use a real chip can be performed only by this process. . In general, the simulation process 101 further includes a process that has an interface function with various input data to the simulation such as logic circuits and input patterns, a process that is in charge of logical operations, and various output data from the simulation such as trace display of output results. Although it is subdivided into processes having interface functions, it will be treated as one process in this specification.

In addition, the actual chip control process 102 is simulated and
This software has an interface function between the process 101 and the input event storage means 103 for a real chip, which is specific hardware, and the output result sampling means 105 from the real chip.

Hereinafter, y in the conventional real chip simulation will be explained. In the simulation process 101, when an event occurs for a structural element (hereinafter abbreviated as a real chip type component) in a logic circuit whose logical function is modeled by the real chip 304, the simulation process 101 causes the real chip 304 to The input data is transmitted to the actual chip control processor 102. Next, the real chip control process 102 stores this data in the input event storage means 103 for the real chip, and then
Enter 4.

The predetermined output from the real chip 304 for this is the real chip,
The actual chip control process 102 will transmit this detection result to the simulation process 101. The simulation process 101 is a real chip 304
If the output of has changed compared to before the event occurred,
We will continue the simulation by treating this as a new event. The operations of the input event storage means 103 for the real chip and the output result sampling means 105 from the real chip are all performed according to timings determined by the real chip control process 102. Next, we will explain the case where the operation of the conventional real chip simulation described above is applied to the simulation of a general microcomputer system. FIG. 4 shows an example of a newly designed microcomputer system, in which 401 is a CPU, 402 is a ROM, 403 is an address decoder for the ROM 402, and 404 is a newly designed part. In addition, CPU4 0 1,R
The address decoder 403 for the OM402 and ROM402 is a real chip type component, respectively.

FIG. 5 particularly shows the instruction fetch cycle among the operations in the microcomputer system shown in FIG. The instruction fetch cycle consists of four cycles TI, T
Consists of 2, T3, and T4. In Figure 5, El,
E2, . . . are events that occur in the simulation process 101.

The operation of conventional real chip simulation regarding this instruction fetch cycle will be explained below with reference to FIG. 6(a). (1) In the simulation process 101, an event }El corresponding to the falling edge of C and C occurs.

(2) For (1), the actual chip control process 102
A predetermined input button is applied to the real chip of the CPU 401 via the input event storage means 103 for the real chip.

(3) In response to (2), the real chip of the CPU 4 0 1 outputs the value of a predetermined address bus, and this output result is simulated via the output result sampling means 105 from the real chip and the real chip control process 102.・
It is communicated to process 101.

(4) In response to (3), an event E2 corresponding to address valid occurs in the simulation process 101.

(5) For (4), the actual chip control process 102
A predetermined input button is applied to the real chip of the address decoder 403 via the input event storage means 103 for the real chip.

(6) In response to (5), the real chip of the address decoder 403 outputs a predetermined decoding result, and this output result is sent to the simulation process via the output result sampling means 105 from the real chip and the real chip control process 102. 101 will be notified.

(7) In response to (6), event }E3 corresponding to the address decoder output enable occurs in the simulation process 101. Thereafter, the actual chip simulation operation for this instruction fetch cycle is performed in the same manner. Figures 6(a) to (C) show a summary of these operations.
However, in FIGS. 6(a) to (C), each event occurs on the simulation process 101, and (1) to (7) correspond to those described above. In addition, in the simulation process 101, events other than those shown in FIG. 6, such as the rise of the clock at the beginning of clock cycle T2, etc. actually occur, but these events directly change the output signal of a specific actual Chisso. It is not intended to be used here, so it is omitted here. The occurrence of each event shown in FIGS. 6(a) to 6(c) and the access to each real chip in the simulation process 101 based on the event are all performed in chronological order. Furthermore, the proportion of instruction fetch cycles in the operation of a microcomputer system is extremely high, and proportionately to this, the proportion of the processing shown in FIG. 6 in the total simulation time is also very high. On the other hand, as shown in FIG. 4, in the design of a normal microcomputer system, the operation of the instruction fetch cycle is often not subject to verification. It is necessary to suppress the number of accesses (ie, the number of ↓ in FIG. 6) in order to shorten the simulation time.

[Problem to be solved by the invention]

In the conventional logic simulation method described above, when performing an actual chip simulation, the CPU 401, RO
The corresponding real chips are prepared for each of the real chip components such as the M402 and the address decoder 403, and the simulation process 101 operates each of the real chips individually and in chronological order when an event occurs. This has the drawback that the number of times the simulation process 101 accesses each actual chip regarding the occurrence of each event increases, leading to a significant increase in the overall simulation time.

[Means to solve the problem]

The logic simulation method of the present invention includes a plurality of physically connected real chips corresponding to a combination of a plurality of components already made into real chips in a logic circuit, and a plurality of physically connected components. It has means for simultaneously inputting arbitrary input events to a real chip at once, and means for owning outputs from the plurality of physically connected real chips in response to the input events as modeling data. ．． [Example] FIG.

In FIG. 1, 104 is a board on which a plurality of real chips are mounted. Note that the simulation process 10l, the actual chip control process 102, and the input event storage means 10
3. The output result sampling means 105 is the same as the conventional example shown in FIG.

FIG. 2 is a more specific hardware block diagram of the input event storage means 103, the board 104 on which a plurality of real chips are mounted, and the output result sampling means 105 shown in FIG. In Fig. 2, 201 is a connector, 2
02 is a board 203 on which the input event shown in FIG. 1, the storage means 103, and the output result sampling means 105 are mounted.
is a bus, 204 and 205 are real chips that are physically connected to each other, and 206 is a connector. The part surrounded by dotted lines in FIG. 2 is the same as the conventional one, and the input button to be applied to the real chip is finally generated by the input event storage means, and then sent to the plural real chips via the bus 203. Given to the mounted board.

The output result of the board 104 on which the actual chip is mounted is sent to the output result sampling means 1 via the bus 203.
Sampled at 05.

Next, the operation of this embodiment will be explained using the microcomputer system shown in FIG. 4 and the instruction fetch cycle shown in FIG. 5, as in the conventional example.

In this embodiment, CPU401, ROM402 in FIG.
, ROM address decoder 403, actual chips are mounted on one board 104, respectively.

The operation of this embodiment regarding the instruction fetch cycle will be described below with reference to FIGS. 7(a) to 7(c).

In the αD simulation process 101, an event }El corresponding to the falling edge of the clock occurs.

A predetermined input pattern is applied to the Q3 cD to the board 104 via the real chip control process 102 and the input event storage means 103 for the real chip.

031 a'b, the board 104 outputs a predetermined address bus value and a predetermined decoding result from the address decoder 403, and this output result is sent to the output result sampling means 105 from the real chip and the real chip control process 102. Simulation process 1 via
01 is reported to have an error.

0◆ (simulation process 1 for 131
At 01, event E2 corresponding to address bus valid and event }E3 corresponding to address decoder output enable occur. (However, these two output results are commonly treated as one event that occurs at the same time in the simulation process 101.) Hereinafter, the actual chip simulation operation for this instruction fetch cycle is performed in the same procedure. ．． Figures 7(a) to (c) show a summary of these operations.
However, as in FIG. 6, each event occurs on the simulation process 101, and αD~Q
4) corresponds to that described above.

In FIG. 7, compared to FIG. 6, the number of accesses to each real chip of the simulation process 101 regarding the occurrence of each event (i.e., the number of ↓ in FIG. 7) is 1.
The number has significantly decreased from 4 to 6. By suppressing the number of accesses to each actual chip by the simulation process 101 regarding the occurrence of each event in the instruction fetch cycle, it is possible to significantly shorten the overall simulation time.

Next, a second embodiment of the present invention will be described with reference to the drawings. The overall logical configuration of this embodiment is also as shown in FIG. 1, similar to the first embodiment.

FIG. 8 shows the input event storage means 103 in FIG.
, a board 104 on which a plurality of real chips are mounted, and an output result sampling means 1050. This is a more specific hardware configuration diagram in this embodiment. The difference between this embodiment and the first embodiment is shown in Figure 8. That is, in FIG. 1, the input event storage means 103, the output result sampling means 105, and the actual chips 204, 20-
5 are mounted on two boards, whereas in FIG. 8 these are mounted on one board, thereby reducing the size of the device as a whole.

Note that since the operation of this embodiment is the same as that of the first embodiment, the explanation thereof will be omitted.

〔Effect of the invention〕

As explained above, in performing an actual chip simulation, the present invention uses CPU401, ROM402
, address decoder 403, etc., and prepare a board on which corresponding real chips are mounted, and perform simulation process 1 in response to an event.
01 operates each of the actual chips in batches and at the same time, so the number of accesses to each actual chip in the simulation process 101 regarding the occurrence of each event can be suppressed, and the overall simulation time can be significantly reduced. effective.

[Brief explanation of drawings]

FIG. 1 is a logical block diagram of the first and second embodiments of the present invention, and FIG. 2 is a hardware diagram for the components 103, 104, and 105 in FIG. 1 in the first embodiment of the present invention. Block diagram, FIG. 3 is a logic block diagram of a conventional example, FIG. 4 is a circuit diagram of a conventional example, a microcomputer system for explaining the operation of an embodiment of the present invention, and FIG. 5 is a microcomputer system of M4 diagram. FIGS. 6(a) to 6(c) are diagrams for explaining the operation of the instruction fetch cycle in FIG. 5, and FIGS. Figures (a) to (
C) is a flowchart for explaining the operation of the embodiment of the present invention of real chip simulation for the instruction fetch cycle of FIG. 5, and FIG. 8 is the structural element of FIG. 1 in the second embodiment of the present invention. It is a hardware block diagram for 103, 104, and 105. 101...Simulation process, 10
2...Actual chip control process, l03...
... Input event storage means, 104 ... Board on which a plurality of real chips are mounted, 105 ... Output result sampling means, 201, 206 ... Connector, 202 ... ...Board, 203...
・Bus, 204, 205, 304...Real chip, 401...CPU, 402...RO
M, 403...Address decoder, 404...
...Parts to be newly designed.

Claims (1)

[Claims] A logic simulation method in which a real chip is prepared for a component in a logic circuit that has already been implemented as a chip, and modeling of a logical function in response to the occurrence of an input event for the component is performed by operating the real chip. , the plurality of real chips physically connected corresponding to the combination of the plurality of components already made into real chips in the logic circuit, and the plurality of physically connected real chips; A logical simulation characterized by having means for inputting arbitrary input events all at once and simultaneously, and means for possessing outputs from the plurality of physically connected real chips in response to the input events as modeling data. method.