JPH0347511B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to raster scanning (luster scanning).
In a cathode ray tube display device (hereinafter abbreviated as CRT) that uses the scanning method, one CRT
The present invention relates to an image display device that combines and displays two images on a display surface.

A conventional device of this type is shown in FIG. In FIG. 1, 101 is the first video
RAM, 102 is the second video RAM,
RAM is also called refresh memory.
2 is a serial-parallel conversion unit (hereinafter abbreviated as SP conversion unit), 3 is a parallel-serial conversion unit (hereinafter abbreviated as PS conversion unit), and 4 is a serial-parallel conversion unit (hereinafter abbreviated as PS conversion unit).
Address switching unit for switching addresses to RAM 101 and 102; 5 is a programmable CRT controller; 6
Reference numeral 7 indicates a timing generation section, 7 an address data setting section, and 8 a data input/output switching section.

Further, 9 to 22 each indicate a signal, 9 is an input image signal, 10 is a CRT separator video signal,
11 is a CRT synchronization signal, 12 is an output data signal,
13 is an input address signal, 14 is a data input/output switching signal, 15 and 17 are each an address signal, 1
6 is an address switching signal, 18 is a video RAM switching signal, 19 is a read-write switching signal, 20 is a dot clock signal, 21 is image data, and 22 is a basic clock signal.

The sweep of the CRT (not shown) is synchronized by a CRT synchronization signal 11 and the brightness of the CRT is modulated by a CRT separator video signal 10.
Images are displayed on the CRT display screen in the same way as in the case of a television receiver. The input image signal 9 is an image signal from a television camera (not shown), for example, an output signal from an ITV camera, a CCD camera, and a CRT.
This is a signal synchronized with the synchronization signal 11. Therefore, both signals 9 and 10 are bit series signals. On the other hand, video RAM101,10
2, consecutive 8 bits (1 byte) constitute one word, and one word is stored at one address. Therefore, signals 9, 10 and video RAM 1
An SP converter 2 and a PS converter 3 are provided for mutual conversion between the signal formats in 01 and 102.

In the device shown in FIG. 1, the CRT separator video signal 10 consists of image data 21 read from a first video RAM 101, and
RAM 102 is used to temporarily store the input image signal 9.

When reading the image data 21, the read/write switching signal 19 is used as read control, and the address switching signal 16 changes the address signal 15 to the address signal 17 according to the signal set in the address data setting section 7.
The video RAM switching signal 18 is output as
RAM101 is selected, and the data in RAM101 is read out for each address as image data 21.
The signal is input to the PS converter 3. The image data 21 input to the PS converter 3 in 8-bit 1 word (1 byte) units is outputted 1 bit by bit in response to the dot clock signal 20, resulting in a CRT separator video signal 10.
becomes.

When writing the input image signal 9 to the video RAM 102 as image data 21 via the SP conversion section 2, the read/write switching signal 19 is used as write control, and the address switching signal 16 is set according to the signal set in the address data setting section 7. address signal 15
is output as the address signal 17, and the video RAM
Switching signal 18 selects RAM102 and RAM1
Image data 21 is written to 02 in address order.

FIG. 2 is a diagram showing a map of the video RAM 102. A rectangle 103 indicated by a solid line in the figure represents the entire area of the memory, and this area corresponds to the image signal of one frame from an ITV camera, etc., which is the source of the input image signal 9. The area A of the shaded rectangle 104 corresponds to the video signal of only the area A in one frame of the image signal.
This means writing to the RAM 102. The center of area A is n bytes and N lines, and its width is
2m bytes, 2M lines, nm bytes N-M
Point P on the line becomes the writing start point. Therefore, writing the image signal of area A into the video RAM 102 requires one frame of scanning time regardless of the size of area A. Vertical synchronization frequency v=55Hz
Then, the scanning time for one frame is 1/v=
It is 18.18ms.

FIG. 3 is a diagram showing a map of the video RAM 101. In the video RAM 102, the area A located at the address position shown in FIG. This indicates that the address position (x=k bytes+α bits, y line is point R) should be overlapped.
Reading and writing to the video RAMs 101 and 102 are performed in word units (in the above example, 1 word = 1 byte), so in the special case of α=0 in FIG. 3, the area A of the video RAM 102 in FIG. Although it is relatively easy to read data from the video RAM 101 and write it to area A in FIG. 3 of the video RAM 101, since α≠0 generally, processing has conventionally been performed using the following procedure.

The data input/output switching signal 14 is output to control the image data 21 to be output as the output data signal 12. Further, the address switching signal 16 controls the address switching section 4 to output the input address signal 1.
3 is output as the address signal 17.

An electronic computer is installed for comprehensive control of the circuit shown in Figure 1, and its central processing unit (CPU)
It is abbreviated as Not shown in FIG. ) and a main memory unit (hereinafter abbreviated as MMU, not shown in FIG. 1), and an input address signal 13
is given from the CPU, and the output data signal 12 is
Stored in MMU. The signal stored in MMU is
After the fractional bit α is processed and the address is converted in software under program control by the CPU, and the signal in area A in Figure 2 becomes the signal in area A in Figure 3, the CPU control The data is thus read out and sent to the data input/output switching section 8 as an output data signal 12. At this time, the data input/output switching signal 14 controls the data input/output switching section 8, and the signal 12 is sent to the video RAM 10 as image data 21.
Connect so that it is input to 1. The address signal 17 at this time is the input address signal 13, and the read/write switching signal 19 is the video signal for writing.
Since it is given to RAM101, image data 21
is written to the location specified by the input address signal 13.

Since the conventional device operates as described above, the image data 21 read from the video RAM 102 is subjected to fractional bit processing and address conversion using software in a computer, and then written back to the video RAM 101 as image data 21. This may require a long time from hundreds of milliseconds to several seconds, and this is due to the ITV signal source of the input image signal 9.
This corresponds to several times the time of one frame of 18.18ms,
When the input image signal 9 from the ITV changes from frame to frame, the input image signal displayed on the CRT as the CRT separator video signal 10 becomes very difficult to see.

This invention was made to eliminate the above-mentioned drawbacks of conventional devices, and an object of the present invention is to provide an image display device that can quickly perform fractional bit processing and address conversion by adding a simple circuit. It is said that

Embodiments of the invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, 23 is a bit shifter, 24 is an address converter, 25 is written image data, and 26 is a read image. 27 is a shift number control signal, 28 is an address addition signal, 29 is a converted address signal, and 30 is an OR circuit. In addition, the address signal 1 in FIG.
5 is called a read address signal 15 to distinguish it from other address signals.

The bit shifter 23 is a circuit that shifts bits by the value indicated by the shift number control signal 27. FIG. 5 is an explanatory diagram for explaining the operation of the bit shifter 23 in FIG. 4.
The word address is ADV1, and the following addresses are
It is assumed that the change is from ADV1 to ADV2. Fifth
Figure a shows the contents of the image data 21 output from the converter 2. At time T ₁ , one word of the part corresponding to address ADV1 is written, and at time T ₂ , one word of the part corresponding to address ADV1 is
Indicates that one word of the portion corresponding to ADV2 is output. The bit shifter 23 for processing the fractional α bit in order to store such image data 21 in the position shown in FIG. , SR2, both SR1 and SR2 are reset to 0 at the beginning of each line, and at the time of _T1 , the output of the SP converter 2 is
It is written to SR2 and becomes as shown in FIG. 5b.
If the content shown in FIG. 5b is shifted to the left by (p-α) bits, the content shown in FIG. 5c will be obtained. Here p is
The number of bits in SR1 and SR2, that is, the number of bits in one word, is p=8 and α=5 in the embodiment shown in the figure. The content shown in Figure 5c is seen from SR1,
This is equivalent to shifting the contents of ADV1 to the right by α (α = 5) bits, so write this and create image data 2.
Output as 1 word of 5. Next, if the contents of FIG. 5c are shifted to the left by α bits, it becomes as shown in FIG. 5d, which is the same as shifting the contents of FIG. 5b by p bits to the left. When the output of the SP converter 2 is written to SR2 at time T ₂ , the state shown in Fig. 5e is obtained, and when this is shifted to the left (p-α) bits, Fig. 5f is obtained.
The content of SR1 at this time is output as the next word of the written image data 25. By repeating the above operations, the fraction α is processed. In this shift process, p is known, α is determined from the position of point R in FIG.
The signal is input to the bit shifter 23 as a shift number control signal 27.

In order to write the write image data 25 after rounding into the area A shown in FIG. 3 of the video RAM 102, N-M lines and nm bytes (FIG. 2) are required.
The address corresponding to y line, k byte (third
It is necessary to convert the address into an address corresponding to the address shown in FIG. That is, since the read address signal 15 indicates the address corresponding to FIG.
The difference between the address of the point obtained by removing the fractional α bit from the point and the address of point p in FIG.
When the converted address signal 29 is added to the address signal 29 and outputted as the converted address signal 29, and the image data 25 is written to the video RAM 102 as the address signal 17, the image data shown in area A in FIG. Now, area A in Figure 3
It is written to the location shown in .

In order to combine and display the image data stored in the video RAMs 101 and 102, the read address signal 15 is set as the address signal 17 and the RAM 1
01 and 102 are simultaneously read out using the same address signal, converted into bit series signals by the PS converter 3, and synthesized by the OR circuit 30.
It can be a CRT separator video signal 10.

As described above, according to the present invention, even in the maximum case, the generation time of a composite image is 2 frame time (18.18ms x 2 = 36.36ms in the above example).
Processing time can be significantly reduced.

[Brief explanation of drawings]

1 is a block diagram showing a conventional device, FIG. 2 is a diagram showing a map of the second video RAM in FIG. 1, FIG. 3 is a diagram showing a map of the first video RAM in FIG. 1, FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is an explanatory diagram illustrating the operation of the bit shifter shown in FIG. 4. 101...First video RAM, 102...Second video RAM, 2...SP conversion unit, 3...PS
Conversion unit, 23...Bit shifter, 24...Address conversion unit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In an image synthesis display device for synthesizing and displaying a first image and a second image on a cathode ray tube display device using a raster scanning method, a video signal of the first image; A first video RAM stores a predetermined number of successive bits (hereinafter referred to as p) as one word, and each word is stored at a respective address position, and a change in a read address signal for reading out this first video RAM. means for sweeping the cathode ray tube display device with a synchronized synchronization signal; and an input image signal in the form of a bit series, which is output in synchronization with the synchronization signal and represents the second image; A serial-to-parallel converter that outputs image data in the form of a signal, and α bits at the end of one word of the image data (α is an integer from 1 to p-1) and p-α at the front of the word connected to it. a bit shifter that connects the bits and outputs it as write image data of p bits 1 word; an address converter that adds a desired value to the read address signal and outputs it as a converted address signal; a second video RAM in which the write image data is written to a designated address position; and means for simultaneously reading video signals from the first and second video RAMs according to the read address signal to generate a composite signal. An image synthesis display device comprising: