JPH0344029A - Etching method of compound semiconductor - Google Patents

Abstract

PURPOSE:To form grooves whose width sizes are different and whose depths are uniform, by a method wherein, after a silicon oxide film is deposited on the surface of a compound semiconductor substrate by using high melting point metal as a mask, heat treatment is performed at a high temperature. CONSTITUTION:A tungsten silicide (WSi) layer 3 is formed on the surface of a gallium arsenide substrate 1 by sputtering deposition or the like. After a photoresist pattern mask is formed by photolithography technique, dry etching is performed by using a mixed gas of carbon tetrafluoride and oxygen, thereby forming a WSi mask 3a. After a silicon dioxide film 4 is deposited on the whole surface by plasma chemical vapor growth method, heat treatment is performed. Since the oxidative effect by the above heat treatment is progressed on the boundary between the WSi mask 3a and the SiO2 film 4, a groove 1a is formed in the manner in which the boundary serves as the center.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to etching of compound semiconductors, and in particular, to etching of compound semiconductors.
This invention relates to a compound semiconductor etching method for forming fine etching patterns that occur in the manufacturing process of six-speed 1-transistors and lasers.

(Prior Art) In the manufacturing process of each pressing device using a compound semiconductor, a method of scraping off a part of the surface of a substrate is often used. for example,
When forming a field effect transistor 1 to transistor using an n-conducting epitaxial layer plate of gallium arsenide, indium phosphide, etc., the separation between elements is achieved by setting the component ratio of sulfuric acid, hydrogen peroxide, and water to, for example, 5:1: Wet etching and silicon tetrachloride (S x CQ
4) and carbon tetrafluoride (hereinafter referred to as CF4), a part of the epitaxial layer is removed by dry etching using an etching gas having a component ratio of, for example, 30:5.

In the case of a recessed field effect transistor, the gate electrode portion is etched using a similar method to form a groove. Furthermore, in the formation of a semiconductor laser, the epitaxial growth layer that will become the laser oscillation section is etched into a striated plateau topography.

As described above, the substrate of a compound semiconductor device is often subjected to etching during its manufacturing process.

This conventional method of etching a compound semiconductor of rice will be explained with reference to FIGS. 3 and 4.

3 and 4 are enlarged cross-sectional views of essential parts of a compound semiconductor having a flat surface and a stepped surface, respectively.

In FIG. 3, a photoresist film 2 is formed on the surface of a gallium arsenide substrate 1, and a mask having openings 2a of various widths is formed by photolithography. next,
Etching is performed using, for example, a sulfuric acid-based etching solution and the photoresist film 2 described in "2" as a mask to form grooves 1a having various width dimensions on the surface of the gallium arsenide substrate 1.

The conventional example shown in FIG. 4 differs from the conventional example shown in FIG. 3 described above in that a step is provided on the gallium arsenide substrate l. Since the other features are the same, the same components are given the same reference numerals and a detailed explanation of the etching method will be omitted. Grooves 1a are formed in the upper and lower flat surfaces of the gallium arsenide substrate 1.

(Problem to be solved by the invention) However, in the above method, as shown in FIG.
When the width of the groove 1a is different, the way the etching solution enters and wraps around the groove differs depending on the opening width of the groove. +1jll
Due to the fact that the depth of a depends on the opening of the cap, there is a problem in that the groove 1a becomes shallower when the width of the opening 28 becomes narrower.

In addition, as shown in Figure 4, if there is a step difference, the pattern is formed using photolithography technology, so the step difference is
There was a problem in that a groove could not be formed on the side surface of b.

The present invention solves the above-mentioned problems and provides a method for etching a compound semiconductor to form grooves of each width dimension and grooves of stepped surfaces having the same depth.

(Means for Solving the Problems) In order to solve the above problems, the present invention deposits a silicon oxide film on the surface of a compound semiconductor substrate using a high melting point metal as a mask, and then heat-treats it at a high temperature. be.

(Function) With the above configuration, at high temperatures during heat treatment, oxygen contained in silicon oxide combines with lower group elements of the compound semiconductor substrate, forms an oxide, and evaporates together with the remaining higher group elements. The reaction occurs significantly at the interface between the refractory metal and the silicon oxide, resulting in the formation of concave grooves.

(Example) A first example of the present invention will be described with reference to FIGS. 1(a) to d).

Figures (a) to d) are enlarged cross-sectional views of main parts showing the etching method according to the present invention in order of steps, taking as an example the case of forming grooves having various width dimensions.

First, a tungsten silicide (hereinafter referred to as WSi) layer 3 having a thickness of 2000 A is formed on the surface of a gallium arsenide substrate 1 by sputter deposition or the like (FIG. 1(a)).

Next, after forming a photoresist pattern film (not shown) using photolithography technology, carbon tetrafluoride (CF
Dry etching is performed using a mixed gas of 4) and oxygen (02) to form a WSi mask film 3a (FIG. 1(b)).
. Next, a silicon dioxide (hereinafter referred to as SiO2) film 4 having a thickness of 1,000 layers is deposited on the entire surface by plasma chemical vapor deposition (CVD), and then heat treatment is performed in a furnace at a temperature of 850° C. for 15 minutes. Gallium (Ga), which is a low group element of the plate 1, combines with the oxygen contained in the SiO2 film 4 to form gallium oxide (Ga20a),
The remaining arsenic (As) is evaporated because its sublimation temperature is much lower than the heat treatment temperature, and gallium oxide is also removed at the same time. The above oxidation effect is caused by the WSi mask film 3a and SiO2
Since it is promoted at the boundary of the film 4, the groove 1a is formed around the boundary. When the width of the groove 1a is wide, the number of openings 3b in the WSi mask film 3a is set according to the width dimension (FIG. 1(C)). Finally, when the 5102 film 4 and the WSi mask film 3a are removed, the gallium arsenide substrate 1
Grooves 1a with various width dimensions and uniform depth are formed on the surface of the substrate (FIG. 1(d)).

Next, a second embodiment of the present invention will be described in FIGS. 2(a) to d.
).

FIGS. 2(a) to 2(d) are enlarged cross-sectional views of essential parts showing steps of an etching method exemplifying the case of forming grooves on a step surface according to the present invention. The second embodiment is different from the first embodiment shown in series in FIG. Groove from lower surface 1c of board 1 ↓
WSi with a thickness of 2000 people according to the distance to the center of a
The WSi mask film 3a was left only at the point where layer 3 was formed (Fig. 2(a)) and on the lower surface 1c (Fig. 2(a)).
b)) and the point where the thickness of the 5jO2 film 4 formed over the entire surface was set to 4,000 mm (FIG. 2(C)). The rest is the same as in the first embodiment, and the same components are given the same reference numerals.

In this example, heat treatment was performed at a temperature of 850'C for 15 minutes.
This embodiment is the same as the first embodiment except that a groove 1a is formed in the stepped surface where the boundary between the WSi mask film 3a and the 5in2 film 4 is in contact.

In addition, as shown in the first embodiment, the width dimension is 0.5/1
+n to 2.07 zm, there is a uniform groove 1a with a depth of 0.5 pm, and as shown in the second embodiment, a groove 1a with a width of 0.57 zm and a depth of 0.5 μm is formed on the stepped surface. obtained respectively.

(Effects of the Invention) As described above, according to the present invention, it is possible to form grooves of uniform depth and different groove widths on the surface of a compound semiconductor substrate. Furthermore, it becomes possible to form grooves on the side surfaces of steps, which was previously impossible.

[Brief explanation of drawings]

1(a) to (d) are enlarged cross-sectional views of main parts showing the process order of the compound semiconductor etching method of the first embodiment of the present invention, and FIGS. 2(a) to (d) are FIGS. 3 and 4 are enlarged sectional views of main parts showing the second embodiment in the order of steps, and FIGS. 3 and 4 are enlarged sectional views of main parts in the middle of the process for explaining the conventional etching method. 1... Gallium arsenide substrate, 1a... lecture, 1b...
...Step, lc...Lower stage surface, 2...Photo-diss 1~film, 2a...Groove opening, 3...Tungsten silicide (WSi) layer, 3a...Tungsten silicide ( WSi) mask film, 4...Silicon dioxide (Si
n2) Membrane.

Claims (2)

[Claims] (1) forming a patterned refractory metal thin film on the surface of the compound semiconductor substrate; forming a silicon oxide film on the entire surface of the compound semiconductor substrate including the refractory metal thin film; A method for etching compound semiconductors that includes a process of heat treatment at high temperatures. (2) Claim comprising the step of forming a high melting point metal thin film only on the lower surface of a compound semiconductor substrate having a step on the surface
1) The compound semiconductor etching method described above.