JPH0334725A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To evade a limit on an analog input voltage range and the manufacturing yield decrease by adopting the the converter constitution as such that a P-N junction of a charge balanced sampling comparator is not biased forward. CONSTITUTION:This circuit is provided with a sample and hold circuit S/H 11 sampling an analog input VIN, a DAC(D/A converter) 14 receiving a reference voltage VREF and a comparator circuit CM1 comparing an analog input sampled by the S/H 11 and an output VDAC DAC 13. The DAC 13 is constituted by outputting 3 kinds of voltages and provided with comparators CM2, CM3 receiving an output of the DAC 13 in addition to the comparator circuit CM1. The CM2 compates 3/4 of the reference voltage VREF outputted from the DAC 13 with an analog input voltage VIN and the CM3 compares 1/4 of the reference voltage VREF outputted from the DAC 13 with the analog input voltage VIN. A successive approximation control section 12 is controlled by the output of the comparators CM1, CM2 and CM3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to analog-to-digital conversion circuits, and in particular to C
The present invention relates to a new configuration of a successive approximation type analog-to-digital conversion circuit configured with an MO3 circuit.

2. Description of the Related Art With the recent progress in CMO3 technology, digital integrated circuits that even include analog circuits such as analog-to-digital converters (hereinafter referred to as ADCs) have become widespread.

FIG. 8 is a block diagram showing the basic configuration of an analog-to-digital conversion circuit used for the above-mentioned applications.

As shown in the figure, this analog-to-digital conversion circuit includes a sample-and-hold device (hereinafter referred to as S/H) 11 that samples the analog input VIN, and a reference voltage VIN.
Digital-to-analog converter with IIEF as input (
(hereinafter referred to as DAC) 13, the analog input sampled by S/H1l, and the output V of DAC13. It is equipped with a comparator CM1 for comparing the AC and AC. Here, comparator CM
The output of I is input to the successive approximation control section 12, and the successive approximation control section 12 gives a digital value to the DAC 13.

Generally, in a successive approximation type ADC, the DAC 13 has reference voltages V, I! The voltage of 1/2 of F is compared with the input terminal V whose value was first sampled, and V DAC is output, and the comparator CM
I is the input voltage VIN and VOa. Compare with. Here, if the comparison result is Vlll>V[lAC, the value of 3/4 of the reference voltage V□ is set to V. Output to AC. Also, the comparison result is V! 11 < VnAc, a value of 1/4 of the reference voltage VIEF is output to V□. Furthermore, VOa. The next comparison voltage is determined based on the comparison result. Note that such control is performed by the successive approximation control section 12.

FIG. 2 is a diagram showing a typical configuration of a comparator constituting the charge balance sampling comparator 14 used in the above-mentioned ADC, that is, the comparator CMI in the circuit shown in FIG. 8. .

As shown in FIG. 2, this circuit has an input terminal Vl at one end.
Switches S1 and S connected to ll and voAc
2, a capacitor C having one end commonly connected to the other ends of these switches S1 and S2, and the other end of the capacitor C and an output V. 8. switch S3 inserted in parallel between
and an inverter INV.

FIG. 4 is a graph showing the input/output characteristics of the inverter INV used in the circuit as described above.

In the comparator CMI, when the switches S2 and S3 are first closed to perform zero correction, the Vr point becomes V B 1. Here, the iE load Q of capacitor C is Q=C(VIN
V1) [However, ■□ is the bias voltage of INV].

Next, when S2 and S3 are opened and 31 is closed, the charge is conserved, so Q=C(VIN VBI) =C(VoAc Vx
), and the potential of Vx is Vx=V++++ (VDACVllll)ΔVOUa=
A (VDACVIN) [However, A is inverter I
V B (gain at NV) of NV.

Therefore, the inverter output V. L+, VIN>VDA
In the case of C, high level (hereinafter referred to as "l"), V
r, I<V. In the case of AC, the low level (hereinafter referred to as “0”)
It is written as〉. As described above, the comparator CMI
The comparison result is V in the output. Appears as LIT.

The eighth device is equipped with the comparator CMI configured as described above.
The operation of the conventional ADC shown in the figure will be described in detail below. For convenience of explanation, this ADC has a resolution of 3
Bit, reference voltage VIEF=5V1 Comparator bias voltage vs+=1.5 V, analog input voltage Vl)l"5
Let it be V.

FIG. 9 is a time chart explaining the operation of this ADC.

First, at timing TS, analog input VIM
is sampled and charged to capacitor C. Next, V
When applying 1/2 value (2.5V) of the reference voltage Vllll:F=5V to the DAC, the voltage Vx becomes Vx =1.5
v+ (2,5v-5v) =-1v [Here, “V
# represents the unit of voltage "V"'.

Problem to be Solved by the Invention Here, in the comparator of this ADC, curve 4 is shown in FIG.
If an inverter with input/output characteristics as shown in 1 is installed, the bias voltage VB□=3.5V, V*
*If p=5VSVIN=OV, the value of Vx is Vx =3.5 v+ (
2,5v+Ov) = +6V. Incidentally, FIG. 10 is a diagram showing the operation of the ADC in such a case.

As described above, in the conventional control method, due to variations in the input/output characteristics of the inverter, -1V below the ground potential (OV>) and +6V above the reference voltage are applied to the Vx point. In the case of the sampling comparator, the switch Sl-S3 is composed of a P-channel MOS transistor and an N-channel MO3) transistor, so there is always a P-N junction and an N-P junction. Therefore, as mentioned above, when a voltage exceeding the voltage range between the ground potential and the reference voltage is applied to the Vx point, the P-N junction is forward biased and a current flows, causing the analog input terminals Vf and I to flow into the capacitor C. The electric charge when applied is no longer conserved,
The conversion accuracy of the ADC will deteriorate significantly and it will no longer function as a comparator.

To solve this problem, either limit the analog input terminal VtN to about IV to 4V, or reduce manufacturing variations so that the bias point of the comparator inverter is about 2.5V±0.5V. It is necessary to suppress this as much as possible, conduct rigorous characteristic tests, and discard products that are outside the standard range.

However, if you limit the analog input terminal range, the AD
The application range of C will be significantly narrowed, and if the bias point of the inverter is restricted, the manufacturing yield will be extremely reduced, resulting in a significant increase in cost.

Therefore, the present invention solves the above-mentioned problems of the prior art and provides a new ADC circuit configuration that can realize an ADC circuit with a wide range of applications without reducing manufacturing yield or increasing costs. Its purpose is to.

Means for Solving the Problems, that is, according to the present invention, in a successive approximation type analog-to-digital converter, there is provided a sample and hold section that receives an analog input, a successive approximation control section, and a predetermined voltage lower than the input reference voltage. a digital-to-analog conversion section that generates a comparison voltage from the output of the successive approximation control section using the voltage as a reference voltage; and a first comparison that compares the output of the sample-and-hold section and the output of the digital-to-analog conversion section. a second comparator that compares an analog input voltage with a predetermined voltage that is equal to or higher than the reference voltage and that is lower than the reference voltage; and a third comparator that compares the analog input voltage with a predetermined voltage that is equal to or higher than a ground potential, and the successive approximation control section is configured to compare the first, second, and third comparisons. An analog-to-digital converter is provided, the analog-to-digital converter being configured to be controlled by the output of the converter.

Operation The ADC circuit according to the present invention has the following characteristics due to its characteristic configuration:
Since the P-N junction of the charge-balanced sampling comparator is not forward biased, it does not limit the analog input voltage range or reduce manufacturing yield. below,
The present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 is a block diagram showing an example of the configuration of an ADC circuit according to the present invention. Note that in the circuit shown in FIG.
Components that are the same as the conventional ADC circuit shown in the figure are given the same reference numerals.

As shown in the same figure, this circuit is connected to the ADC shown in FIG.
Similar to the circuit, an S/
A comparator CMl that compares the analog input sampled by the S/H1l with the output VDAC of the DAC 13 is provided. However, in this circuit, the DAC 13 is configured to output three types of voltages as described below.

In addition to the comparator CMI, this circuit also includes comparators CM2 and CM3 to which the output of the DAC13 is input.

Here, the CMI has the same configuration and operation as the comparator in the conventional ADC already described with reference to FIG.

That is, the output of the sample/hold section 11 and the DA converter 1
Compare the output VDAC of 3 and VIJl>VDA
It is configured to output "1" in the case of V DAC, and "0" in the case of V I N < V DAC. still,
In this embodiment, V DAC is ■. The voltage is 1/2 of .

Further, the comparator 0M2 is connected to the base 1 [t
Compare 3/4 value of Evapp and analog input voltage VIN, Vllll > 3/4 ・Vllll! F
It is configured to output "1" in case (7), and output "0" in case vyN<3/4·VREF.

Furthermore, the comparator CM3 compares the value of 1/4 of the reference voltage V REF outputted by the DAC 13 with the analog input voltage VIN, and sets "l" if VIN<1/4・V IEF, and sets VIJl>1. /4.VREP is configured to output "0".

FIG. 3 is a circuit diagram showing a specific configuration example of the successive approximation control section 12 used in the ADC shown in FIG.

As shown in the figure, this circuit consists of a set/reset flip-flop (hereinafter referred to as S-RF/F) 31
-a-c and D-type flip-flop below, D-F/F
) 32-a-d, AND game) 33-a,
b, and OR gates 34-a to 34-C. Here, TRG is a trigger signal for starting conversion of ADC,
VOUT is the output signal of the comparator shown in Figure 2, and C
M2 and CM3 are the comparator 0 shown in FIG.
These are the output signals of M2 and CM3. Also, the output DOO
~DO2 is a digital output, and output DO~D2 is an input signal of the DA converter 13 shown in FIG.

FIG. 5 is a time chart for explaining the operation of the ADC circuit configured as described above.

The operation of this ADC circuit will be described below with reference to the same figure. Note that here, as in the conventional example, the reference voltage Vmip=5V, and the bias voltage of the comparator V□=1.5.
V, analog input terminal Vl) l=5V.

First, when the trigger signal TRG shown in FIG. 3 becomes "1", all R-3F/F 3l-a-c are reset and TS becomes "1" with a delay of 1 bit. Therefore, the timing 1S , the switch S2 of the circuit shown in FIG.
and S3 are closed, analog input terminal Vl! 1 and V
Charge is stored in capacitor C by BI. At this time, comparator 0M2 is "1" and CM3 is "0".

Next, at timing 1 shown in FIG. 5, CM2 is “1”.
”, so S-RF/F31-a is set and OR
Output D2 of Age-34-a becomes “1”, AND game) 3
The output of 3-b becomes "1", and the output D2 of ○R Age-34-b also becomes "1". Therefore, the DA converter output VDA
The value of 3/4·V*ep is output to C. Here, the voltage at point Vx of the circuit shown in FIG. 2 is as follows: Vx = 1.5 v+ (3,75v-5v) = 0.
It becomes 25v.

At this time, the output V of the comparator CMI. U7 is ■.

〉Vx, so it is "1'. Also, 5-RF/F
The set side AND gate of 31-a becomes "1" and is set, but since the output DO2 is originally "l",
It does not change.

Next, in the timing period 2 shown in FIG. 5, the OR age-34-a shown in FIG. 3 is "1" because t2 is "1".
#, and OR Age-34-b becomes "l". The DA converter output VDAC has 3/3 as well as timing 1.
4・V 11! F (3,75V) is output, and the comparator CMI output V. , T becomes "1".

Therefore, FIG. 5-RF/F 31-b is set,
The output Dot becomes "l".

Next, during the period of timing t in FIG. 5, all of the circuits shown in FIG.
7/8'vm from A converter output VDAC! p(4,37
5v) is output. Comparator CM shown in Figure 2
The voltage at point Vx of I is: Vx = 1.5v+ (4,375v-5v) =0
．． 875 V, and since V□>V, the comparator output V. u7 is 1''. Therefore, R-3 shown in FIG.
F/F 31-c is set, and digital outputs of all 1'' from DOO to DO2 are obtained.

Next, the inverter INV of the comparator shown in FIG.
A case will be described in which the human output characteristic is shown as a curve 42 in the figure.

Regarding the conventional example, as already explained with reference to the figure, the reference voltage V*! r=5V, comparator bias voltage V B 2=3
．． 5 V, analog input terminal VIN=OV, when the trigger signal TRG in Figure 3 becomes "1", the S-RF/F
3l-a-c are all reset. After a delay of 1 bit, the trigger signal TRG becomes "0", and the D-F/F 32
-a output TS becomes "1" and sampling timing occurs.

FIG. 6 is a time chart showing the sequence in such a case.

As shown in the figure, at timing TS, the point Vx of the comparator CMI shown in FIG. 2 is Vx''Vl+2=3.
5 V, zero correction is performed, and the input voltage V
Charge is accumulated due to IM=OV.

Next, at timing 1, the output of comparator CM2 shown in FIG. 1 becomes "0" and the output of comparator CM3 becomes "1".
Therefore, the AND game shown in Figure 3) 33-a
is prohibited. Further, since the 5-RF/F 31-a is reset by the output of the comparator CM2, the outputs DO to D2 of the OR games 34-a and -c are all "0". Therefore, the output VOLIT of the DA converter 13 becomes OV. Here, the Vx point of the comparator CMI shown in FIG. 2 is vx = 3.5v+ (Ov-Ov) = 3.5v
Therefore, VB7 is at a level that cannot be determined as "0" or "■", but since the S-RF/F31-a shown in Fig. 3 has been reset by the comparator CM2, the conversion result will not be abnormal. do not have.

Next, in the timing period 2, ○R Age-3
4-b is set to "1", and OR gates 34-a and C are set to "1".
0'', and the output of the DA converter 13 is Vout=1
/ 4 ・V+u: Output p=1.25V. Here, the voltage at point Vx of the comparator in FIG. 2 is as follows: Vx = 3.5v+ (1,25v-OV) = 4.
75v, and since VX>V, 2, the comparator CMI
output V. 8. becomes “0”. Therefore, the R-3F/F 31-b shown in FIG. 3 remains in the reset state because the set condition is not satisfied.

Next, in the timing period 3, the OR gate 34-C shown in FIG. 3 becomes "1", the OR gates 34-a and 34-b become "0", and the output of the DA converter 13 is V.D.
AC=1/8・V+up,=0.625V
becomes. Here, the voltage at point Vx of comparator CMI in Fig. 2 is: Vx = 3.5V+ (0°625 v-OV) =
It becomes 4.125 y. Here, since VX > VB2, the output V of the comparator CMI. 8. becomes “0”. Therefore, the S-RF/F 31-c remains in the reset state, and a conversion result of all "0" is obtained for the S-RF/F 3l-a-c.

Embodiment 2 FIG. 7 is a block diagram showing another configuration example of the ADC according to the present invention. In FIG. 7, the same components as in FIG. 1 are given the same reference numbers as in FIG. 1.

The circuit shown in the same figure is the ADC according to the present invention shown in FIG.
A pair of D-type switches L1 and L2 are further added to the circuit. These D-type switches Ll and L2 are connected to a signal TS for sampling the analog input voltage VB.
latches the outputs of comparators CM2 and CM3, respectively. The other operations of this circuit are the same as in the first embodiment, so a detailed explanation will be omitted.

That is, in this embodiment, in the sampling period TS,
D-type switches L1 and L2 are comparators CM2 and CM3
The output is latched and held until the next AD conversion timing TS. Therefore, during AD conversion, the analog input terminal V1
This has the advantage of not malfunctioning even if N changes.

Effects of the Invention As detailed above, the ADC circuit according to the present invention has V
Analog input terminal V above a predetermined voltage higher than the DAC
It is equipped with a comparator that detects IN and a comparator that detects analog input voltage VTII that is less than a predetermined voltage lower than VDAC. Since the PN junction in the circuit is not forward biased no matter what analog input voltage V1N up to the reference potential VREF is input, the conversion accuracy of the ADC is always good.

Also, a pair of comparators used in the circuit as described above is
Since there is no problem in using a simple static comparator with a comparison accuracy of about ±0.25 V, the above-described configuration does not significantly increase the manufacturing cost of the ADC circuit.

As described above, the ADC circuit according to the present invention can be widely applied because there is no need to narrow the analog input voltage range, and can extremely limit manufacturing variations in the inverter of the charge balance sampling comparator. Since the yield is not deteriorated, it is possible to provide an ADC with high AD conversion accuracy at a low price.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of an ADC circuit according to the present invention, and FIG. 2 is a circuit diagram showing a detailed configuration of a comparator that can be used in the ADC circuits shown in FIGS. 1 and 8. 3 is a circuit diagram showing a specific configuration example of the successive approximation control section in the ADC circuit shown in FIG. 1, and FIG. 4 is a circuit diagram used in the circuit shown in FIG. 2. FIG. 5 and FIG. 6 are graphs showing the input/output characteristics of the inverter according to the present invention, and FIGS. 5 and 6 are time charts for the operation of the circuit shown in FIG. FIG. 8 is a block diagram showing a typical configuration of a conventional ADC circuit; FIG. 9 and FIG. 5 is a time chart for explaining the operation of the circuit. [Main reference numbers] 11... Sample/hold section, 12... Successive approximation control section, 13... DA conversion section, 14... Charge balance sampling comparator, CMI to CM3... Comparison 31-S3...Switch, INV...Inverter, 3l-a-c...Set/reset type flip-flop, 32-a-d...D type flip-flop, 33-a
, b ・ ・ ・AND gate, 34-a-c ・ ・
・OR gate, Ll, L2...D type latch

Claims (1)

[Claims] A successive approximation type analog-to-digital converter, comprising: a sample/hold unit that receives an analog input; a successive approximation control unit; a digital-to-analog conversion section that generates a comparison voltage from the output of the comparison control section; a first comparator that compares the output of the sample-and-hold section and the output of the digital-to-analog conversion section; and a first comparator that is equal to the reference voltage. a second comparator that compares the analog input voltage with a predetermined voltage that is equal to or higher than the reference voltage and that is lower than or equal to the reference voltage; a third comparator that compares a predetermined voltage higher than the analog input voltage, and the successive approximation control section is controlled by the outputs of the first, second, and third comparators. An analog-to-digital converter comprising: