JPH0330894B2 - - Google Patents
Info
- Publication number
- JPH0330894B2 JPH0330894B2 JP8659181A JP8659181A JPH0330894B2 JP H0330894 B2 JPH0330894 B2 JP H0330894B2 JP 8659181 A JP8659181 A JP 8659181A JP 8659181 A JP8659181 A JP 8659181A JP H0330894 B2 JPH0330894 B2 JP H0330894B2
- Authority
- JP
- Japan
- Prior art keywords
- virtual
- virtual machine
- computer
- control
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007796 conventional method Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
Description
【発明の詳細な説明】
この発明は制御プログラムとユーザプログラム
からなるシステムにおいて、システムのアクセス
しようとするハードウエア資源（例えば主記憶装
置、中央処理装置その他）のすべてのシステムに
よつて管理されている実計算機及びシステムのア
クセスしようとするハードウエア資源の一部ある
いは部が他のシステムの管理にゆだねられている
が他のシステムの存在をまつたく意識せずに記述
されている仮想計算機の上で仮想計算機を実現す
るための情報処理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION This invention provides a system consisting of a control program and a user program, in which all hardware resources (for example, main storage, central processing unit, etc.) that the system attempts to access are managed by the system. on a real computer, and on a virtual computer where part or part of the hardware resources that the system is trying to access is entrusted to the management of other systems, but is written without being aware of the existence of other systems. The present invention relates to an information processing device for realizing a virtual computer.
実計算機上に仮想計算機を実現する場合その実
計算機のことを制御用実計算機、その上に別の仮
想計算機を実現する仮想計算機を制御用仮想計算
機、その上には仮想計算機を実現しない（あるい
はできない）仮想計算機を一般仮想計算機とそれ
ぞれ呼ぶことにする。 When a virtual computer is realized on a real computer, the real computer is called the control real computer, the virtual computer on which another virtual computer is realized is the control virtual computer, and the virtual computer is not (or cannot) be realized on top of it. ) The virtual computers will be referred to as general virtual computers.
実計算機上および仮想計算機上で仮想計算機を
実現する従来の手法についてはR.P.ゴールドバー
グ（R.P.Gold berg）によるVirtnal Machines
Architecture（Haneywell Computer Journal誌
1973年、VOL.7，No.４）にくわしく述べてある。
この文献を用いて従来の手法について説明をす
る。第１図に仮想計算機間の関係の一例を示す。
Ｒは実計算機、V1c〜V1 For conventional methods of realizing virtual machines on real machines and virtual machines, see Virtual Machines by RPGold berg.
Architecture (Honeywell Computer Journal)
1973, VOL.7, No.4).
The conventional method will be explained using this document. FIG. 1 shows an example of the relationship between virtual computers.
R is the real computer, V 1c ~ V 1
Claims (1)
に実現する仮想計算機システムにおいて、仮想計
算機の構成要素である仮想主記憶を実主記憶上の
連続する領域に割り付け、１レベル下位に１つ以
上の仮想計算機を有しかつそれらの仮想計算機を
制御する制御用計算機の主記憶のあらかじめ定め
られた領域に上記仮想計算機ごとにその仮想計算
機を制御するための情報を保持する仮想計算機ブ
ロツクと、上記制御用計算機が現時点で制御をわ
たしている仮想計算機の仮想計算機制御ブロツク
のアドレスを得るための情報を保持する実行仮想
計算機制御ブロツクアドレス保持域とをもうけ、
上記仮想計算機制御ブロツクに、その仮想計算機
の主記憶の１つ上位の制御用計算機の主記憶上で
のアドレスとその仮想計算機が現時点でさらに下
位の仮想計算機に制御を渡しているかどうかを表
わす情報とを付加し、仮想計算機に制御を渡す際
にその仮想計算機を制御している制御用計算機上
の前記実行仮想計算機制御ブロツクアドレス保持
域の情報を得るための情報をそのトツプにつみ上
げ、仮想計算機から制御がもどつてくる時にその
トツプの値をおろし、トツプからボトムまでの任
意の位置にある値を参照することができるラス
ト・イン・フアースト・アウトスタツク（LIFO
STACK）機構を備えたことを特徴とする仮想計
算機方式。1. In a virtual computer system that implements one or more virtual computers hierarchically on a real computer, virtual main memory, which is a component of the virtual computer, is allocated to contiguous areas on the real main memory, and one level below a virtual computer block that holds information for controlling each virtual computer in a predetermined area of the main memory of a control computer that has the above virtual computers and controls the virtual computers; an execution virtual machine control block address holding area for holding information for obtaining the address of the virtual machine control block of the virtual machine to which the control computer is currently transferring control;
The above virtual machine control block contains the address on the main memory of the control computer one level above the main memory of the virtual machine and information indicating whether the virtual machine is currently passing control to a lower virtual machine. When passing control to a virtual machine, information for obtaining the information of the execution virtual machine control block address holding area on the control computer controlling the virtual machine is added to the top of the virtual machine, and the virtual machine is transferred to the virtual machine. Last-in-first-out stack (LIFO) allows you to drop the top value when control returns from the computer and refer to the value at any position from the top to the bottom.
A virtual computer method characterized by having a STACK) mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8659181A JPS57201951A (en) | 1981-06-05 | 1981-06-05 | Virtual computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8659181A JPS57201951A (en) | 1981-06-05 | 1981-06-05 | Virtual computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57201951A JPS57201951A (en) | 1982-12-10 |
| JPH0330894B2 true JPH0330894B2 (en) | 1991-05-01 |
Family
ID=13891245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8659181A Granted JPS57201951A (en) | 1981-06-05 | 1981-06-05 | Virtual computer system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57201951A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7257811B2 (en) * | 2004-05-11 | 2007-08-14 | International Business Machines Corporation | System, method and program to migrate a virtual machine |
| US9785485B2 (en) * | 2005-07-27 | 2017-10-10 | Intel Corporation | Virtualization event processing in a layered virtualization architecture |
-
1981
- 1981-06-05 JP JP8659181A patent/JPS57201951A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57201951A (en) | 1982-12-10 |
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