JPH03296998A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To erase a data properly in a short period by erasing a memory array by a pulse with a long pulse width when lots of unerased cells exist and with a short pulse width when the number of unerased cells reaches a prescribed number or below. CONSTITUTION:An erasing pulse generator 19 consist of a pulse generator 50, a pulse width changeover circuit 51, a high voltage switch circuit 53, an erasure control circuit 54 and the unerased cell number counter 55. When the number of storage elements in a 2nd logic state is less and the possibility of causing storage elements not normally operated due to the rewrite to the 2nd logic state is less, a rewrite pulse having a large pulse width is used for rewrite. Thus, most of storage elements are rewritten in a short period. On the other hand, when lots of storage elements in the 2nd logic state exist and the possibility of causing storage elements not normally operated due to the rewrite to the 2nd logic state is high, a rewrite pulse having a small pulse width is used for rewrite. Thus, the data is erased in a short period properly.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to nonvolatile semiconductor memory devices, and particularly relates to a method for erasing data in a bulk erase type electrically erasable nonvolatile semiconductor memory device. be.

[Prior art] Fig. 7 shows an l5SCC (International single
5olid-3tate C1rcuits C
2 is a block diagram of a nonvolatile semiconductor memory device described in Digest of Technical Papers (1990) pp. 6061. Referring to FIG. 7, a nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells arranged in a plurality of rows and columns.
The memory array 1 is arranged in the memory array 1, the address buffer 76 is connected to the address buffer 76 for buffering the address signals AO to AK of the memory array 1 applied from the outside, and the address signal is decoded to read one of the rows A row decoder 4 for selecting, and a column decoder 5 for likewise selecting one of the columns, connected to the column decoder 5 and the memory array 1, the bits of the memory array 1 are connected according to the decoded and selected column. a Y gate 2 for selecting one of the lines; a source line switch 3 connected to the memory array 1 for switching the voltage applied to the source line of the memory array 1; A write circuit 7 connected to the memory array 1, a sense amplifier 8 connected to the memory array 1 via the Y gate 2, and a sense amplifier 8 connected to the write circuit 7 and the sense amplifier 8 to buffer input/output signals with the outside. a human output buffer 9, and a mode control circuit 10 which is supplied with E, OE, and PGM by a signal EE from the outside and controls the operating mode of this device;
An erase control circuit 11 is connected to the mode control circuit 10, address buffer 76, row decoder 4, source line switch 3, and sense amplifier 8, and is used to control the operation of this device when erasing the stored contents of the memory array 1. including.

The address buffer 6 receives an address signal AO-A from the outside.
k is given. Human output buffer 9 is input/output signal line ■1
00 to 1107 exchange input/output signals with the outside.

FIG. 8 is a block diagram of memory array 1 and its peripheral circuits. Referring to FIG. 8, a memory array 1 is connected to a row decoder 4, a plurality of word lines WL1 to WL3 arranged in parallel to each other, and a Y gate 2.
A plurality of bit lines BLI to BL3 arranged in parallel to each other in a direction intersecting the word lines WLI to WL3, and memory cells such as memory cells MCI provided at each intersection of each word line and each bit line, Source lines SL1 to SL for connecting each memory cell and source line switch 3
3.28.

In FIG. 8, three word lines and three bit lines are drawn. However, this is just for convenience of explanation, and in reality, the number of these is larger.

The Y gate 2 is connected to the I10 line 27 to which the write circuit 7 and sense amplifier 8 are connected, and each bit line BL1 to BL3 and I
10 line 27 and transistors 26a to 26c for bit line selection. Each transistor 2
Gates 6a to 26c are connected to outputs Y1 to Y3 of column decoder 5, respectively.

FIG. 9 is a schematic cross-sectional structural diagram of the memory cell MC1 of FIG. 8. Referring to FIG. 9, memory cell MCI is provided on semiconductor substrate 24. Referring to FIG.

The memory cell MCI includes a source region 23 and a drain region 22 formed of impurity regions formed at a predetermined interval on the main surface of a semiconductor substrate 24, and a region between the source region 23 and the drain region 22 on the main surface. Formed film thickness: 100
A thin oxide film, a floating gate 21 for information storage formed on this thin oxide film, an oxide film formed on the floating gate 21, and an additional layer provided on the oxide film. control gate 20. Source region 23 is connected to source line SLI.

Drain region 22 is connected to bit line BLI. Control gate 20 is connected to word line WL1. Floating gate 21 is electrically insulated from others.

FIG. 10 is a more detailed block diagram of the erase control circuit 11. Referring to FIG. 10, an erase control circuit 11 is connected to a mode control circuit 10 and includes a command signal latch 12 for latching a command signal given from the mode control circuit 10, a mode control circuit 10, and a command signal latch 12. 12, a sequence control circuit 13 for controlling the source line switch 3, row decoder 4, address buffer 76, and sense amplifier 8, a verify voltage generator 14 for generating a specified voltage, and a sequence control circuit. 13 and the verify voltage generator 14, and is connected to the voltage switch 1 for switching the power supply voltage applied to the row decoder 4 and the sense amplifier 8 according to the operation mode.
5. The voltage switch 15 switches the power supply voltage applied to the row decoder 4 between 5V, 13V, and 3.4V. The voltage switch 15 also switches the power supply voltage applied to the sense amplifier 8 between 5V and 3.4V.

The sequence control circuit 13 is connected to the command signal latch 12, and includes an address counter 16 and a command signal latch for sequentially generating addresses of the target memory and providing them to the address buffer 6 when erasing the stored contents of the memory array 1. 12, is connected to the address counter 16 and sense amplifier 8, and is used to confirm erasing and erasing status (hereinafter referred to as "
(referred to as "erase verify") sequence control circuit 13
and an erase/erase verify control circuit 17 for controlling the operation of the source line switch. 3, an erase pulse generator 19 for supplying the erase pulse to the mode control circuit 10 and the erase/
It includes an erase verify control circuit 17 and a decoder control circuit 18 connected to the erase verify control circuit 17 .

The following describes the operation of nonvolatile semiconductor memory devices.
The explanation will be given in the order of successive addition and deletion.

(1) Write operation When data is written to the memory cell MC1 shown in FIGS. 8 and 9, the nonvolatile semiconductor memory device operates as follows. Write circuit 7 is activated and I1
A high voltage vpp is applied to the 0 line 27. Column decoder 5
is the bit line BLI to which the memory cell MC1 is connected.
In order to select , transistor 26a is turned on.

For this purpose, the column decoder 5 converts its output Y1 into a high voltage V
Boost the pressure to pp. Outputs Y2 and Y3 of column decoder 5 are kept at L level. The row decoder 4 has memory cells M
Select the word line WLI to which CI is connected, and
The level of LI is boosted to high voltage VppWL. The source line switch 3 grounds the source line 28. This results in
A high voltage VppBL is applied to the drain 22 of the memory cell MC1.
A high voltage vppwt is applied to the control gate 20, and the source 23 is grounded.

As a result, a current flows between the drain 22 and the source 23. By setting the channel structure so that a high electric field is generated near the drain 22, hot electrons are generated near the drain 22 due to an avalanche phenomenon. Most of the generated hot electrons flow to the drain 22. However, some hot electrons are absorbed by the high voltage Vp applied to the control gate 20.
Due to pWL, the energy gap between floating gate 21 and silicon substrate 24 is exceeded and stored in floating gate 21. As a result, the threshold value of the memory transistor of this memory cell MCI is shifted higher. It is assumed that information "0" is written in this state.

(2) Read operation When reading from the memory cell MCI shown in FIGS. 8 and 9, the device operates as follows. Column decoder 5 selects bit line BLI to which memory cell MCI is connected. For this purpose, column decoder 5 sets its output Y1 to "H" level and turns on transistor 26a.

Both outputs Y2 and Y3 of the column decoder 5 are kept at "L" level.

Similarly, row decoder 4 selects word line WLI to which memory cell MCI is connected, and sets its level to "H" level. The row decoder 4 is connected to other word lines WL2 and WL.
3 at L” level.

The source line switch 3 grounds the source line 28. Therefore, source lines SLI to SL3 are also at ground potential.

It is assumed that information "'0" is written in memory cell MCI in advance. In this case, the threshold value of the memory transistor of memory cell MCI is high. At the control gate 20 “
Even if the H'' level is applied, the memory transistor does not conduct. No current flows from the bit line BLI to the source line SLI.

It is assumed that memory cell MCI is in an erased state.

Memory transistors have low thresholds. Therefore, when an "H" level voltage is applied from word line WL1 to control gate 20, the memory transistor becomes conductive.

A current flows from the bit line BLI to the source line SL1 via the memory transistor. Therefore, word line WL1
When an "H" level voltage is applied to the control gate 20, the sense amplifier 8 detects whether or not a current flows through this memory cell, thereby changing the information stored in the memory cell MCI to "0". ” or “1”.

(3) Erasing operation During the erasing operation, high voltage Vpp5L is applied to the sources 23 of all memory cells by the source line switch 3. All control gates 20 are grounded. The drains 22 of all memory cells are kept floating. That is, all of the outputs of the column decoder 5 and row decoder 4 are set to "L".

A strong electric field is induced in the oxide film between floating gate 21 and source 23. Due to the tunneling phenomenon caused by this strong electric field, electrons are extracted from the floating gate 21 to the source 23. As a result, the threshold voltage of the memory transistor of the memory cell becomes lower.

Source line SL1 of all memory cells of memory array 1
~SL3 are connected to a common source line 28. Therefore, data is erased in all memory cells of memory array 1 at once.

In the following description, the "H" level refers to approximately the power supply voltage (5cm), and the "L" level refers to the ground potential.

By the way, due to the manufacturing process of semiconductor memory devices, variations occur in the characteristics of the devices. This variation may cause some memory cells to be easily erased and some memory cells to be less likely to be erased. If the erase pulse is set according to memory cells that are easily erased, those that are difficult to erase will remain unerased.

On the other hand, if the erase pulse is set according to what is difficult to erase, there is a risk that electrons will be extracted excessively from the floating gate of a memory cell that is easy to erase, and this memory cell will become depressed.

When an unselected memory cell is in a depletion state during successive selection, a current flows not only in the selected memory cell but also in the depleted unselected memory cell. A malfunction occurs in the fruiting device. Furthermore, even during so-called programming, in which data is written to each memory cell of the memory array 1, current flows to unselected cells that are in a depleted state. As a result, programming becomes impossible. In order to avoid such troubles, the following steps are taken when erasing memory cells.

In the erase mode, all memory cells are first written, and the threshold values of the memory transistors of all memory cells are raised. Address counter 16 sequentially generates address signals and supplies them to address buffer 6 in order to write to all memory cells of memory array 1 . The row decoder 4, column decoder 5, and write circuit 7 are erase/
It is controlled by erase verify control circuit 17 and writes to all memory cells of memory array 1.

After writing to all memory cells is completed, an erase/erase verify operation is started. First, a high voltage is applied to the sources of all memory cells by the source line switch 3. All word lines WL1-WL3 are grounded. As a result, all memory cells of memory array 1 are erased. Application of high voltage to the source by the source line switch 3 is carried out for a fixed period of time, for example, 10 m5. The source line 2 is set by the source line switch 3.
This potential change applied to 8 is called an erase pulse.

Thereafter, an erase verify operation is performed on memory array 1. Erase verify operation refers to memory array 1
The task is to check whether data has been erased from all memory cells. Address counter 16 sequentially generates address signals to select all memory cells and supplies them to address buffer 6. Each memory cell of memory array 1 is sequentially selected by row decoder 4 and column decoder 5. The sense amplifier 8 amplifies the output from this memory cell and supplies it to the erase/erase verify control circuit 17. Erase/erase verify control circuit 17
When it finds a memory cell with a high threshold, it stops the verify operation and repeats the erase operation. When it is determined that the threshold values of all memory cells have become low, the erase/erase verify control circuit 17 ends the erase/erase verify operation. When this erase operation is completed, the status signal output from the command signal latch 12 becomes "H" level.

By repeating the above erase/erase verify operation, the threshold values of the memory transistors of all memory cells are shifted to around 0. Electrons are removed from the floating gate of each memory cell in small amounts. Therefore, each memory cell never becomes depressed.

[Problems to be Solved by the Invention] In the conventional nonvolatile semiconductor memory device, the erase/erase verify operation is performed as described above. Therefore, the following problems arise. Due to the manufacturing process of non-volatile semiconductor memory devices, there may be large variations in the ease with which memory cells within a chip can be erased. As described above, memory cells that are easily erased may become depressed.

In order to avoid this, if erase is repeatedly performed using short pulses, depletion of the memory cell becomes less likely to occur, but the number of erase confirmations after erasing increases.

As a result, there is a problem in that the time required to complete erasing increases.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can erase data in a short time and appropriately.

[Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention includes a plurality of memory elements that can be rewritten between a first logic state and a second logic state. means, logic state detection means for detecting a number of storage elements in one of the first and second logic states, and a number of storage elements detected by the logic state detection means; and rewrite pulse generating means for generating a rewrite pulse having a pulse width for rewriting from a first logic state to a second logic state.

[Function] In the nonvolatile semiconductor memory device according to the present invention,
It is first detected how many of the storage elements are in the second logic state, for example.

The width of the pulse generated by the rewriting pulse generating means is changed depending on the number of detected storage elements.

Therefore, for example, when the majority of memory elements are in the second logic state and there is a risk that some memory elements may malfunction due to a write operation to the second state, the pulse width is small. If this is not the case, a rewrite pulse to the second state is generated with a large pulse width.

[Example 1] FIG. 1 shows an erase pulse generator 19 used in an erase control circuit 11 of a nonvolatile semiconductor memory device according to the present invention.
FIG. Referring to FIG. 1, an erase pulse generator 19 used in a nonvolatile semiconductor memory device according to the present invention includes an erase/erase verify control circuit 1.
7 and is connected to the erase control circuit 54 for controlling the entire operation of the erase pulse generator 19; connected to the cell number counter 55 and the erase control circuit 54;
Receiving a reset signal 56 from the erase control circuit 54, pulses 52a having mutually different pulse widths;
The pulse generator 50 is connected to the pulse generator 50 and the unerased cell counter 55, and is input from the pulse generator 50 in accordance with the pulse selection signal 46 given from the unerased cell counter 55. a pulse width switching circuit 51 for selecting one of a plurality of types of pulses 52a, 52b and outputting it as a pulse width regulation pulse Terase 45; connected to the pulse width switching circuit 51 and a high voltage external Vp; Pulse width regulation pulse Tera
has a pulse width similar to se, and whose amplitude is equal to that of external Vp
The erase pulse 1ntVp is a high voltage defined by
and a high voltage switch circuit 53 for outputting p.

FIG. 2 is a simplified block diagram of pulse generator 50. Referring to FIG. 2, pulse generator 50 includes an oscillator 70 for oscillating a clock signal having a fixed number of pulses.
and a frequency divider 71a connected to the output of the oscillator 70 for dividing and outputting the clock given from the oscillator 70.
and a frequency divider 71b connected to the output of the frequency divider 71a to further divide and output the output of the frequency divider 71a. The frequency dividers 71a and 71b are connected to the erase control circuit 5.
In response to the reset signal 56 given from 4, the circuit returns to the initial state and starts dividing the clock.

The pulse output from the frequency divider 71b is the first pulse 52
a, and the frequency divider 71. The pulse output from a is the second pulse 52b.

Referring to FIG. 3, the pulse width switching circuits 51 each have a first
The pulse 52a1 and the second pulse 52b are generated by the pulse generator 5.
0, and in response to the pulse selection signal 46 given from the unerased cell number counter 55, two switching devices for outputting the first pulse 52a1 and the second pulse 52b as the pulse width regulation pulse Terase45 in a complementary manner to each other. It includes circuits 4 Qa, 40b, and an inverter 43 for inverting a pulse selection signal 46 and applying it to the switching circuit 40a.

The switching circuit 40a includes an inverter 41a whose input is connected to the output 47a of the inverter 43, a p-channel side gate connected to the output of the inverter 41a, an n-channel side gate connected to the output 47a of the inverter 43, and a first It includes a transfer gate 42a to which a pulse 52a is applied as an input and whose output is a pulse width defining pulse Terase45.

Similarly, the switching circuit 40b is connected to a signal line 4 to which a pulse selection signal 46 from an unerased cell number counter 55 is applied.
An inverter 41b has an input connected to 7b, a p-channel side gate is connected to the output of the inverter 41b, an n-channel side gate is connected to a signal line 47b, a second pulse 52b is applied to the input, and the output has a pulse width specified. Pulse Tera
and a transfer gate 42b serving as se45.

Referring to FIG. 4, the high voltage switch circuit 53 has a source connected to the output of the pulse width switching circuit 51 and a gate connected to the power supply voltage V.
an n-channel transistor 63 connected to cc, a p-channel transistor whose source is connected to a high voltage external Vp, whose drain is connected to the drain of the transistor 63 at a node 66, and whose gate is applied with the output of the high voltage switch circuit 53. 61, a p-channel transistor 64 whose gate is connected to the node 66, whose source is connected to the high-voltage external Vp, and whose drain is the output of the high-voltage switch circuit 53; whose gate is connected to the node 66, and whose source is the p-channel transistor 64. and n-channel transistors 65 whose drains are connected to ground potential, respectively.

FIG. 5 is a waveform diagram for explaining the operation of the pulse generator 50, and FIG. 6 is a diagram showing the threshold voltage characteristics of the memory cell of the nonvolatile semiconductor memory device according to the present invention.

Note that the overall configuration of the nonvolatile semiconductor memory device according to the present invention is the same as that already explained with reference to FIGS. 7 to 10. Identical parts have been given the same reference numerals and designations.

Their functions are also the same. Therefore, a detailed explanation thereof will not be repeated here.

Erase pulse generator 19 operates as follows when erasing memory cells in memory cell array 1.

The erase control circuit 54 receives a command from the erase/erase verify control circuit 17 to erase data from memory cells included in the memory cell array 1, and resets the unerased cell number counter 55 and the pulse generator 50.

Referring to FIG. 2, oscillator 70 outputs a clock having a constant number of pulses as shown in FIG. 5(b).

Frequency dividers 71a and 71b each return to the initial state in response to the reset signal and begin frequency division of the signal provided from oscillator 70. Referring to FIG. 5(c), for example, the frequency divider 71a divides the output clock of the oscillator 70 to 1/2.
outputs a pulse having a pulse number of . Referring to FIG. 5(d), the frequency divider 71b further divides the output of the frequency divider 71a to give a quarter of the clock output from the oscillator 70.
outputs a pulse having a pulse number of . The pulse output from the frequency divider 71b becomes a first pulse 52a1, and the pulse output from the frequency divider 71a becomes a second pulse 52b and is applied to the pulse width switching circuit 51.

Initially, the number of unerased cells is 0, so the unerased cell number counter 55 sets the pulse selection signal 46 to "L" level.

Referring to FIG. 3, pulse selection signal 46 is applied to inverter 4
3, and applied to the switching circuit 40a.

In the switching circuit 40a, the output of the signal line 47a is “H”.
" level, so its input and output are short-circuited. On the other hand, the switching circuit 40b is in an open state because the "L" level of the pulse selection signal 46 is directly applied as a control voltage. Therefore, when the pulse Pulse width regulation pulse Te output from the width switching circuit 51
rase45 becomes the first pulse 52a.

Referring to FIG. 4, high voltage switch circuit 53 operates as follows. Input pulse width regulation pulse Tera
When se45 becomes "H" level, transistor 64 starts to turn on. The output Vp of the voltage switch circuit 53 is “L”
“It starts to get to the level.

However, the pulse width defining pulse Terase is of normal amplitude, and the source of transistor 64 is connected to the high voltage external VV.
Since the transistor 64 is connected to p, the transistor 64 cannot be completely turned off. Therefore, a through current flows between the external Vp to which the source of the transistor 64 is connected and the ground to which the drain of the transistor 65 is connected, and the output Vp of the high voltage switch circuit 53 cannot completely become "L". . In this case, the output of the high voltage switch circuit 53 becomes unstable, which is not preferable.

Therefore, the output of the high voltage switch circuit 53 is applied to the gate of the transistor 61. When the output Vp of the high voltage switch circuit 53 approaches the "L" level, the transistor 61
turns on. A high voltage of external Vp is applied to node 66. Therefore, transistor 64 is completely off and transistor 65 is completely on. The output of the high voltage switch circuit 53 becomes completely "L" level.

When the pulse width defining pulse Terase goes to L'' level, the node 66 also goes to 'L'' level.

Transistor 64 is turned on. Transistor 65 is turned off. The potential of the output Vp of the high voltage switch circuit 53 becomes equal to the potential of the external Vp. Transistor 61 is turned off.

Therefore, the high voltage switch circuit 53 inverts the phase of the input pulse width regulation pulse Terase and changes its amplitude from the normal amplitude (for example, 0-5V) to the external voltage
It is converted into a high voltage amplitude defined by p and output. The pulse output from the high voltage switch circuit 53 becomes an erase pulse 1ntVpp for erasing each memory cell of the memory cell array 1, and is applied to the memory cell array 1.

Erase pulse 1 ntV as described in the prior art section
After the contents stored in each memory cell of the memory cell array 1 are erased by pp, the erase/erase verify control circuit 17 notifies the start control circuit 54 of the start of the erase verify operation. The erase control circuit 54 is
In response to this signal, the unerased cell number counter 55 is reset.

Referring to FIG. 10, address counter 16 sequentially generates addresses for all memory cells and supplies them to address buffer 6 in order to check the erasure status of all memory cells in memory cell array 1. According to the designated address, the stored contents of all memory cells of memory cell array 1 are read by sense amplifier 8 and provided to erase/erase verify control circuit 17. The erase/erase verify control circuit 17 informs the erase control circuit 54 of the data read from the memory array 1, for example, in units of each bit, each byte, or each word, whether or not there is an unerased memory cell.

The erase control circuit 54 provides a pass/fail signal to the unerased cell number counter 55 depending on the presence or absence of unerased memory cells. The pass/fail signal is set to the "L" level when non-erasure of the memory cell is detected for each read unit, and is set to the "H" level when it is not detected.

Unerased cell number counter 55 counts the number of unerased cells included in memory array 1 according to the value of the pass/fail signal.

If the number of unerased cells is greater than or equal to a predetermined number, the unerased cell number counter 55 outputs the pulse selection signal 46 to "
In other cases, it is set to "H" level.

If the pulse selection signal 46 is at the "L" level, the pulse selected by the pulse width switching circuit 51 is the first pulse 52a.

However, when the pulse selection signal 46 becomes "H" level, the pulse selected by the pulse width switching circuit 51 is the second pulse 52b. Referring to FIG. 3, when pulse selection signal 46 is at "H" level, switching circuit 40a is turned off and switching circuit 40b is turned on. Therefore, the pulse width of the pulse width regulation pulse Terase output from the pulse width switching circuit 51 is equal to the pulse width of the second pulse 52b. That is, in this case, the pulse width of the pulse width defining pulse Terase is half of the previous pulse width.

The nonvolatile semiconductor memory device further performs an erase/erase verify operation of the contents stored in the memory array 1 using an erase pulse of 1 ntVpp having a short pulse width.

Then, when the number of unerased cells is no longer detected in the erase verify operation, the erase operation ends.

As described above, when the number of unerased cells exceeds a certain number, the erase pulse generator 19 used in the nonvolatile semiconductor memory device according to the present invention erases the memory array 1 with an erase pulse having a long pulse width. Delete the stored contents,
If the number of unerased cells is less than a certain number, the contents stored in the memory array 1 are erased using an erase pulse having a shorter pulse width. Therefore, as the number of erased cells increases, erasing is performed in smaller increments. Therefore, the memory cell is prevented from becoming depressed.

Referring to FIG. 6, the threshold value of each memory cell when logic "0" is written to all memory cells at the beginning of erasing is V.
Let it be O(V). If the threshold value of a memory cell exists in the range of voltages v1 to vO shown in FIG. 6, it is considered that the memory is programmed. on the other hand,
If a memory cell has only a low threshold value of 0 to v2, it is considered that the stored contents of that memory cell have been erased.

In FIG. 6, the first, second, and third erasures with long pulses are performed at times 0 to t1, t1 to t2, and t2 to t3, respectively, and the first erasure with short pulses is performed at times t3 to t4. FIG. 8 is a diagram showing a characteristic line 81 of the threshold value of a cell that is difficult to erase and a characteristic line 82 of the threshold value of a cell that is easy to erase.

At time t4, the threshold value of cells that are difficult to erase is
The value corresponds to the position indicated by point P.

Therefore, even the memory cell that is most difficult to erase can be considered to have been erased at time t4.

On the other hand, at time t4, the value of the threshold characteristic line 82 of the cell most likely to be erased is the value corresponding to the position indicated by point Q. The threshold value at point Q is within the range of 0 to v2, which is considered to be in an erased state and not in a depressed state. Therefore, time t4
By completing erasing at , it can be considered that all memory cells of memory array 1 have been completely erased without depletion.

As described above, by performing erasing with a long pulse while the number of unerased cells is large, it is possible to bring the majority of memory cells into the erased state in a short time. On the other hand, when the number of unerased cells falls below a certain number, depletion of the memory cells can be prevented by erasing the memory array with a short pulse. therefore,
A nonvolatile semiconductor memory device that can perform erasing appropriately in a short time can be obtained.

Although this invention has been described in detail based on one embodiment, the invention is not limited to this embodiment.

For example, the unerased cell number counter 55 may have any configuration as long as it outputs a pulse selection signal when a certain specified value is reached.

[Effects of the Invention] As described above, according to the present invention, the number of memory elements in the second logic state is small, and rewriting to the second logic state may cause some memory elements to become unable to operate normally. When the signal width is small, rewriting is performed using a rewriting pulse having a large pulse width. As a result, most of the memory elements can be rewritten from the first logic state to the second logic state in a short time. On the other hand, when there is a large number of memory elements in the second logic state, and there is a high possibility that some memory elements will no longer operate normally due to rewriting to the second logic state, a rewrite pulse with a small pulse width may be used. Rewriting is performed. As a result, all the memory elements are rewritten from the first logic state to the second logic state in a short time, and the possibility that some memory elements become unable to operate normally due to rewriting is reduced. can.

In other words, it is possible to provide a nonvolatile semiconductor memory device that can erase data in a short time and appropriately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an erase pulse generator used in a nonvolatile semiconductor memory device according to the present invention, FIG. 2 is a block diagram of the pulse generator, and FIG. 3 is a circuit diagram of a pulse width switching circuit. 4 is a circuit diagram of the high voltage switch circuit, FIG. 5 is a waveform diagram showing the operation of the pulse generator, and FIG. 6 is a diagram showing the threshold characteristics of the memory cell. , FIG. 7 is a block diagram of a nonvolatile semiconductor memory device, FIG. 8 is a block diagram of a memory array and its surrounding circuits, FIG. 9 is a schematic cross-sectional structure diagram of one memory cell, and FIG. The figure is a block diagram of the erase control circuit. In the figure, 1 is a memory array, 11 is an erase control circuit, 16 is an address counter, 17 is an erase/erase verify control circuit, 19 is an erase pulse generator, 40a and 40b are switching circuits, 41a and 41b are inverters, 42a, 4
2b is a transfer gate, 43 is an inverter, 50 is a pulse generator, 51 is a pulse width switching circuit, 53 is a high voltage switch circuit, 54 is an erase control circuit, and 55 is an unerased cell number counter. In addition, the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Non-volatile semiconductor storage means having a plurality of storage elements that can be rewritten between a predetermined first logic state and a second logic state different from the first logic state, The storage element in the second logical state may not operate normally due to further rewriting from the first logical state to the second logical state; logic state detection means for detecting the number of said storage elements in one of two logic states; and having a pulse width that varies as a function of the number of said storage elements detected by said logic state detection means. , a rewrite pulse generating means for generating a rewrite pulse for rewriting from the first logic state to the second logic state.