JPH03293841A - Input digital signal processing device - Google Patents

Abstract

PURPOSE:To standardize the device constitution and to easily set a time constant with a high precision by regularly performing the processing for each sampling of a signal and comparing the count result of sampling data and the time constant set value with each other by hardware. CONSTITUTION:A multiplexer (MPX) 1 successively selects a one-bit signal from an inputted N-bit signal in accordance with the output of a program counter 4 and samples the selected signal in accordance with a high-speed sampling clock outputted from a clock control part 3 and outputs the result to an arithmetic logic unit (ALU) 5. When the value of sampling data is different from the value of the preceding input signal, the number of sampling data is counted, and the counted value is compared with a preliminarily determined value, and the value of the input signal is determined based on the comparison result and is outputted to an electronic apparatus main body. Thus, the device constitution is standardized and the time constant is easily set with a high precision.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input digital signal processing device, and more particularly to an input digital signal processing device that removes noise contained in a digital signal inputted to a programmable controller or the like. It is.

[Conventional technology]

The digital signal input to the programmable controller includes noise caused by chatter or bounce of the contacts of the input device or noise induced by external wiring. Therefore, in order to remove these noises, conventional w1 child devices such as programmable controllers are equipped with filter devices as their input circuits.

FIG. 10 is a circuit diagram showing the configuration of a conventional analog filter device, where 11 is a power source for external input equipment, the hill is a switch for signal input, 13 is a resistor for current limiting, and 14 is a photocoupler. . The resistor 15 and capacitor 16 constitute a filter circuit, and their values are added to provide a time constant that can remove noise depending on the state of the noise contained in the signal.

However, such analog filter devices have the following problems.

■Various time constants are required depending on the characteristics of the input device and the state of noise, but in this method, the time constant is set based on the values of the components that make up the filter circuit, so the required FRf Every time the number changes, you must change the parts to appropriate values. That is, as an electronic equipment manufacturer, there was a problem in that it was not possible to standardize /...-ware.

(2) Users of electronic devices also require various filter circuit time constants depending on the usage status of the electronic device, and must purchase electronic devices with different filter time constants as appropriate.

There was a problem with the inability to standardize arrangements.

Since the time constant of the OT analog circuit is determined by the values of the resistor and capacitor, it is difficult to obtain a high mit time at low cost. Therefore, in order to obtain a high-quality time constant, it is necessary to use a high-quality resistor or capacitor, and as a result, there is a problem in that the price of the product increases.

Rather than using the time constant of the analog circuit as described above to remove noise, the microprocessor (hereinafter referred to as CPU) in the slave device samples the input signal and inputs it according to its software. Signal on/
There is also a conventional example in which the influence of noise is prevented by determining whether the device is off.

In such a system in which the CPU determines on/off of an input signal, the function corresponding to the time constant of the analog circuit described above can be changed by changing the software. However, the conventional example of such a system has the following problems.

■The microprocessor (CPU) samples the input signal according to the software, and after reading the sampled data for 2 summers and 3 summers, determines whether the data match or performs a majority vote to determine whether the input signal is on or off. Therefore, the amount of software increases and the number of items processed by the CPU increases. In particular, when the number of input points increases, the CPU becomes busy with input filter processing, and there is a risk that the original processing capacity within the electronic device will decrease.

■The wooden sword method has the following inherent problems that do not occur with the analog method due to the discrete method of sampling the input signal. In other words, when the repetition period of the noise component mixed into the input signal is close to the sampling synchronization.

There is a risk of misjudgment (erroneous input). this is.

This is a fundamental problem with digital processing, and does not occur with analog processing methods.

In order to avoid this, the sampling period can be made faster (sampling period = 0 is equivalent to analog processing, but there is a limit to sampling by the software of the CPU of the device itself.

For example, if the number of input points is 16, the sampling period is set to
00PS is the limit that can normally be achieved,
As explained above, when it comes to input devices for electronic devices that remove noise, it is often necessary to set an appropriate time constant depending on the noise state. However, there are problems in that the health of the device cannot be improved or that an excessive load is placed on the CPU of the electronic device itself.

An object of the present invention is to standardize the device configuration, and
In order to achieve the above objects, it is possible to easily set a highly accurate time constant, and to remove the influence of noise mixed into the input signal without putting a burden on the CPU of the electronic device itself. sampling means for sampling a digital signal at predetermined intervals; and counting the number of samples having a value different from the value of the digital signal currently being output by classifying the sample value fe of the sampled digital signal. a counting means; a comparison means for comparing the output of the counting means with a predetermined value;
The present invention is characterized by comprising a determination result output means for determining and outputting the value of the digital signal according to the comparison result of the comparison means.

[Effect]

In the present invention configured as described above, the sampling means samples the input signal at predetermined intervals, and when the value of the sampled data is different from the value of the previous input signal, the counting means calculates the number of the sampled data. Count. Then, the comparison means compares the number with a pre-added value, and the calculation means determines the value of the input signal based on the result and outputs it to the electronic device main body.

[Metal practice]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which a multiplexer (MPX) 1 selects one of the input Nb+t signals according to the output of the program counter 4.
bit signals are selected sequentially and the signals are sent to the clock controller 3.
Samples are prompted by the high-speed sampling clock output from the The data sampled in this manner is output to an arithmetic and logic unit (ALU) 5.

6 is a work memory l (RAM), which includes an off-time constant setting memory 6-1 and an off-time constant setting memory 6-2 corresponding to each bit of the input signal. Input counter current value memo IJ 6-
3. It is equipped with Nblt filter output result memories 6-4. Then, the output register 2 outputs an N-bit signal as a result of the processing described below to the main body of the electronic device. Here, the filter output result memory 6-4 is a memory for storing the output state of the output register 2. In addition, the input count setting value (time constant setting value) set in the ON time constant setting memory 6-1 and the OFF time constant setting memory 6-2 can be set by the user using an input device as appropriate by providing an external bus interface section. Alternatively, the setting may be made using an external setting bin.

The operation of this embodiment configured as described above will be explained focusing on the processing in the ALU 5.

First, the user sets the ON time constant setting memory 6-1 and the OFF time constant setting memory 6-2.

An input count setting value (time constant setting value), which is a reference for determining the value of an input signal, is inputted into the Nb account.

FIG. 11X2 is a flowchart showing an example of a procedure to be processed by the ALU 5, and the ALU 5 performs processing according to this procedure every time it samples each bit of the input signal of the Nb port. and within a predetermined time 1 b
tt is processed, and after that time, 1b+t is processed, and this processing is performed as N as shown in Fig. 3.
Repeat several times. Urge me.

This repetition period becomes the sampling period for a specific 1 brt signal.

In FIG. 2, first, in step S1, sampling data output from MPXI is input, and in step S2, the filter output currently being output from the output register 2 is read from the filter output result memory 6-4.

In step S3, which of the following processes to perform is determined depending on the values of the sampling data and the value of the filter output.

(If the 11 filter output is off (10") and the sampling data is off ("0'), proceed to step S4 and input counter current value memory 6-3.
Reset the current value of the input counter in 201 to 201.

(If the 21 filter output is off (“01”) and the sampling data is on (@tl), proceed to step S5, and input counter current value memory 6-
Input counter current value and ON time constant setting memory 6-
1, and if the ON time constant setting value has not been reached yet, the process advances to step S6, increments the input counter current value, and stores the value in the input counter current value memory 6-3. Store. If the on-time constant setting value has been reached in step S5, the process advances to step S7 and the output register 2 and filter output result memory 6-
Set the value in 4 to wlt.

Reset the current value of the input counter to 101.

13+ If the filter output is on ('1') and the sampling data is off (Iol), the process advances to step S8 and the input counter current value memory 6-
Input counter current value and off time constant setting memory 6-
2, and if the off time constant setting value has not been reached, proceed to step S6, increment the input counter current value, and use that value as the input counter current value. The input counter current value is stored in the memory 6-3. If the off time constant setting value has been reached in step S8, the process advances to step S9, and the values in the output register 2 and filter output result memory 6-4 are set to 101, and the current value of the input counter is set to Jl. Reset.

(If 41 filter output is on ('1') and sampling data is on ('1'), proceed to step 510 and input counter current value memory 6-
Set the current input value in 3 to 101st.

After completing any of the processes (1) to (4) above, A
The LU 5 returns to step S1, inputs the sampling data of the signal next to the currently processed signal output from the MPX 1, and repeats the above processing.

Therefore, when focusing on one signal, the repetition period in which the above-described processing is performed N times becomes the sampling period for that signal, as shown in FIG. That is, ALU
5 is a certain 1 btt signal, as shown in Figure 4, sampling data of a value different from the output value of the output register 2 is continuously @l.

When a signal is input, the number is counted and compared with a predetermined value, and as a result, the output value of the output register 2 is redundant, thereby being included in the signal. Remove noise.

Note that in this embodiment, when data of the same value is input continuously and a preset time constant value is reached, the output value of the output register is changed. A so-called majority voting method may be used in which the output value of the output register is changed if data of the same value is input a predetermined number of times or more within a time.

In this way, in the present invention, the processing for each sampling of the signal is regular, and the count result of the sampling data and the time constant setting value can be compared by hardware, so that the filter processing of the input signal can be performed at high speed. Can be done.

Therefore, it is easy to implement the above-described embodiment into an LSI, and in that case, the basic configuration may be as shown in FIG. In FIG. 5, 51 is an input multiplexer into which a signal containing noise is input, 52 is an arithmetic unit that processes the 1 bxt signal output from the input multiplexer 51, and 53 is the current input count value and filter output result. The piece is an output register for outputting the processed signal to the electronic device main body, and the piece is an output register for outputting the processed signal to the electronic device body. This is a control counter that supplies signals to various parts.

This LSI processes a 32btt input signal and outputs it to the main body of the electronic device.

FIG. 6 shows the configuration of the part related to 1bxt of the work memory s53, where DO-D6 is an area where the current input counter value is stored, and D7 is an area where the filter output result value is stored. ing.

In this way, since 1 byte of memory is provided corresponding to 1b of the input signal, the work memo IJ 53 as a whole has a memory for 32b of input signals, that is, 32 bytes.
There will be a memory of te.

FIG. 7 is a configuration diagram showing the external configuration of the LSI.

In this LSI, the ON time constant setting value and the OFF time constant setting value are not stored in the work memory section, but are set in an external setting bin as shown in FIG.

FIG. 8 shows an LS configured according to the basic configuration shown in FIG.
FIG. 2 is a block diagram showing the internal configuration of I. Moreover, FIG. 9 is a time chart showing the signal states of each part of this LSI, and shows the signal So/Sl output from the control counter 5b.
The timing of the rise or fall of 1 is synchronized with ψ
0 or ψlIC Therefore, this LSI sequentially processes the sampled data.

First, at timing ψ0, the SRG and WRG in the control unit 5 each take in the data added at the b1t address output to the input multiplexer 51 of the control counter □□□ and the work memory unit.

Then, the value of the input 1 btt signal for SRG is @O
The WRG outputs data DS indicating whether the signal is I or slm, and data D7 indicating the value currently output as the value of the signal among the captured data to the decoder.

At timing ψ1, the decoder determines which of the processes (11 to (4) shown in the second diagram) to perform based on the states of the two input data DSD7, and according to that determination, for example, the current value of the input counter ( After performing processing such as comparing the value obtained by adding 1 to DO-D6) and the time constant setting value, data in the work memory & and output registers are rewritten.

As shown in FIG. 9, the repetition period required to process an input signal of 32 b+t, that is, the sampling period for a certain 1 bt+ signal, is 3-2 (ps) x 32 (btt) = 102-4
(ps). Note that this period can be shortened by increasing the frequency of the crystal rooter.

In addition, this LSI allows you to select the time constant setting value using an external setting bin, but the setting value corresponding to one time constant of 3m5L is 32J (102,4ps x 3
2=3.2768rns), and the setting value corresponding to 10tns is %J (102,4F8X96 =9.8
304m5).

In order to be able to set an arbitrary time constant without using such an external setting bin, it is necessary to provide a memory for setting the time constant, and to access this memory from the data bus connected to the CPU of the electronic device. A bus interface may be provided so that it can be accessed.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to standardize the device configuration, easily set the time constant with 1ii6 precision, and eliminate noises mixed into the input signal without putting a burden on the CPU of the electronic device itself. It is possible to remove shadows.

[Brief explanation of drawings]

tIg1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a flowchart showing an example of the procedure to be processed by the ALU shown in FIG. 1, and FIG. 3 is the processing of the first embodiment shown in FIG. Theory 8EJ diagram showing the procedure, Section 4 is. FIG. 5 is an explanatory diagram for explaining the processing content of one signal in the embodiment shown in FIG. 1, and FIG. 5 is a diagram showing the basic configuration when the embodiment shown in FIG. FIG. 6 is an explanatory diagram for explaining the configuration of the work memory shown in FIG. 7, FIG. 7 is an explanatory diagram for explaining the external configuration of the LSI, and FIG. , No. 9
The figure shows a time chart for explaining the operation of the LSI,
FIG. 10 is a circuit diagram showing the configuration of a conventional example. 1...Multiplex? (MPX), 2...Output register, 3...Black control I! 1 part, 4... program counter, 5... arithmetic logic unit (ALU), 6
...Work Me Takukuku 2 Tai No. (2) Writing country I z 3 λ force f blt NiN 11brtijf Also, the 1st old file letter appears 0th sighting

Claims (1)

[Claims] 1) Sampling means for sampling an input digital signal at predetermined intervals, identifying the value of the sample of the sampled digital signal, and identifying the value of the sample of the digital signal that is different from the value of the digital signal currently being output. a counting means for counting the number of objects; a comparing means for comparing the output of the counting means with a predetermined value; and a determination result output means for determining and outputting the value of the digital signal according to the comparison result of the comparing means. An input digital signal processing device comprising: