JPH03290951A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To relieve a user of design burden and reduce the number of pins of a package by a method wherein a test signal from a test signal generator is switched to a signal to a basic block by an external control signal and inputted to the basic block. CONSTITUTION:A D/A converter block 13 is composed of a counter circuit 8 which generates a test signal of a D/A converter 3 and a selector circuit 2 which switches the test signal from the circuit 8 to a signal inputted from an I/O terminal 6 through a user circuit 1 and transmits the signal to the converter 3. If a control terminal 9 is set at a required state so as to have the block 13 in a test mode, the circuit a is reset simultaneously and all the outputs of the circuit 8 become '0'. In this state, a zero scale error is measured. Then a clock is inputted to a clock input terminal 10 and a full scale error and a linearity error are detected. With this constitution, the number of terminals can be reduced and design burden of test circuit insertion can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to an application-specific semiconductor integrated circuit (ASIC) manufactured by a building block method or a master slice method.

〔overview〕

The present invention provides a single-conductor integrated circuit (ASIC) for specific applications including basic blocks such as mega macros and analog macros, in which the basic block includes a test signal generation circuit of the basic block,
By including a selector circuit that switches the test signal from this test signal generation circuit with the signal to the basic block using an external control signal and inputs it to the basic block, it reduces the design burden on the user and reduces the number of pins on the package. This is to reduce the number.

[Conventional technology]

A circuit with a specific function is defined as a basic pro7,
Semiconductor integrated circuits manufactured using automatic placement and wiring based on such connection information are called standard cells or gate arrays, and are customized for specific applications.
Demand is steadily increasing as I (AS ic). In recent years, mega macros and analog macros have been developed in order to improve the functionality of these LSIs and to promote digital/analog compounding.

A megamacro is a circuit with hundreds to thousands of gates defined on a database like the basic blocks mentioned above, and since the hardware is already fixed and the input/output characteristics are guaranteed, the user's design L without too much burden
This realizes high functionality of SI. Analog macros define analog circuits, such as analog-to-digital conversion circuits and digital-to-analog conversion circuits, in the same way as mega macros, and users can create analog-digital mixed LSIs by simply including these blocks in the circuit connection information. can be realized.

Testing is a problem when using mega macros and analog macros. Even if the user is familiar with the input/output relationships of mega tuna and analog macros, they cannot see their internal logic and operation, and therefore cannot create test signals that will maximize the defect detection rate of these macros. Conventionally, in testing these macros, the circuit is designed so that its input/output terminals can be directly accessed from external pins, that is, in test mode, and in that state, pre-prepared macro test signals are input and various tests are performed. I was going.

FIG. 6 is an example of an LSI design incorporating a conventional 6-bit digital-to-analog conversion circuit (D/A) 3a. In FIG. 6, 1a is a customized circuit designed by the user (hereinafter referred to as user circuit), 6a is an input/output terminal for user circuit 1a, 7a is an output terminal of digital-to-analog conversion circuit 3a, and 4 is a test terminal. The terminal 2a is a selector circuit for selecting the signal from the test terminal 4 and the signal from the user circuit 1a and transmitting the selected signal to the digital-to-analog conversion circuit 3a, and 5 is a control terminal of the selector circuit 2a.

In designing such semiconductor integrated circuits, the user must:
It was necessary to insert the selector circuit 2a and to provide a test terminal 4 which is not required for use.

[Problem to be solved by the invention]

In a semiconductor integrated circuit based on a design method that incorporates a mega macro or an analog macro as described above, a user needs to insert a test circuit or add a test terminal for a test mode. This has the drawback of increasing the number of design steps for the user and raising the package cost due to the increase in the number of pins.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit for a specific application, which can reduce the number of design steps for a user and reduce the number of package bins by eliminating the above-mentioned drawbacks.

[Means to solve the problem]

The present invention provides a semiconductor integrated circuit for a specific application, which includes digital and analog basic blocks having a predetermined function and whose input/output characteristics are guaranteed in advance, including a plurality of input terminals necessary for the predetermined function, and a plurality of input terminals necessary for the predetermined function. A first circuit block that performs a function, a second circuit block that generates a test signal for the first circuit block, and switches between a signal from the input terminal and a test signal from the second circuit block. The present invention is characterized by comprising a basic block including a third circuit block that inputs data to the first circuit block, and at least one terminal for controlling the third circuit block.

[Effect]

The basic block includes a second circuit block for testing a first circuit block that performs the function of the basic block, and the test signal from the second circuit block is internally switched by a third circuit block. and then manually input to the first circuit block.

Therefore, there is no need for the user to insert a basic block test circuit again, and the number of design steps can be reduced.

Furthermore, since the test signal is manually input to the first circuit block by internal switching, there is no need for an external terminal for inputting the test signal, and normally only one is required, and only the control terminal of the third circuit block is required. , the number of package pins can be significantly reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which the present invention is applied to a semiconductor integrated circuit including a digital-to-analog conversion circuit, and FIG. 2 is a block diagram of the digital-to-analog conversion circuit. FIG. 3 is a block configuration diagram showing details.

The bookcase embodiment includes a user circuit 1 having a plurality of input/output terminals 6, and a digital-to-analog conversion circuit block (D/A) 13 having a control terminal 9, a clock input terminal 10, and an output terminal 7. There is.

The digital-to-analog conversion circuit block 13 is
A 6-bit digital-to-analog conversion circuit (D/A) as the first circuit block, which is a feature of the present invention.
3, a counter circuit 8 as a second circuit block that generates a test signal for this digital-to-analog conversion circuit 3, a test signal from the counter circuit 8, and a signal input from the input/output terminal 6 via the user circuit 1. and a selector circuit 2 as a third circuit block that switches between the two and transmits the data to the digital-to-analog conversion circuit 3, and the output of the digital-to-analog conversion circuit 3 is connected to an output terminal 7a to control the selector circuit 2 and the counter circuit 8. The terminal 9a is connected to the control terminal 9 in FIG. 1, the clock input terminal 10a of the counter circuit 8 is connected to the clock input terminal 10 in FIG. 1, and the digital input terminal 11 of the selector circuit 2 is connected to the user circuit in FIG. 1 output.

Next, a test of the digital-to-analog conversion circuit 3 in the bookcase embodiment will be explained.

First, the control terminal 9 is set to a desired state in order to put the digital-to-analog conversion circuit block 13 into test mode. At this time, the counter circuit 8 is reset at the same time, and all its outputs become "0". Measure the zero scale error in this state.

Then, a clock is applied to the clock input terminal 10, and all
Count up until it reaches 1 and measure the full scale error. Further, a clock is applied to again count up from all "0" to all "1", and the output of each step is measured to detect a linearity error.

In this way, the first embodiment shown in FIG. 1 can reduce the number of terminals by five compared to the conventional example shown in FIG. 6, and also eliminates the design burden of inserting a test circuit.

FIG. 3 is a block diagram showing a second embodiment of the present invention.
A case where the present invention is applied to a semiconductor integrated circuit including a cross-point switch circuit is shown, and FIG. 4 is a circuit diagram showing details of the cross-point switch circuit.

The second embodiment is characterized by a 4×4 cross point switch circuit 100 as a first circuit block and a test signal generation circuit as a second circuit block that generates the test signal. circuit 101 and a selector circuit 109 as a third circuit block that switches the test signal from the test signal generation circuit 101 with a signal input from the outside and inputs it to the crosspoint switch circuit 100.
Contains.

In addition, in FIG. 3, 106 and 102 to 105
108 is a selector circuit 1090 control terminal, and 107 is a clock input terminal of the test signal generation circuit 101, respectively.

According to FIG. 4, the cross-point switch circuit 100 includes a switch section consisting of 16 analog switches 111 of SLL-S44, a D latch circuit 110 with reset provided corresponding to each analog switch 111, and a NAND circuit 112. , buffer circuits 113 and 114, and an inverter circuit 115.

Next, a test of the crosspoint switch circuit 100 in the second embodiment will be explained.

First, the control terminal 108 is set to the "H" level in order to enter the test mode. At the same time, this signal is also guided to the TEST input of the test signal generation circuit 101, whereby the test signal generation circuit 101 generates a signal as shown in FIG. This test signal is applied to the 16 analog switches 111 (SL in FIG. 4) of the crosspoint switch circuit 100.
It enables simultaneous measurement of 4 units that can most efficiently measure S11.32 at timing a.
2.333 and S44 are measured, and at timing b, S12.323, S34 and S41 are measured, and so on.

When designing a circuit using the crosspoint switch circuit 100 shown in FIG. 3, only the clock input terminal 107 and the control terminal 108 need to be provided with external terminals for testing purposes. Other digital input terminals 102
105 may be connected to the user's own circuit, and there is no need to insert a test circuit between them.

Conventionally, when testing this crosspoint switch circuit 100, only two test terminals are required compared to the maximum of 34 test terminals required by the test circuit.

〔Effect of the invention〕

As described above, the present invention has the effect of solving problems such as insertion of test circuits for testing analog macros and megamacros and enlargement of the package due to an increase in the number of test terminals. Furthermore, the following effects can also be obtained.

First, the present invention makes it possible to unify test modes and control methods for transitioning to these modes, which differ depending on the product type, thereby facilitating the automatic creation of test programs.

Furthermore, test signals had to be prepared for each product due to the different control methods, and the generation of these signals required a lot of man-hours, but the present invention has the effect of almost eliminating the need for this. be.

As a result, according to the present invention, the turnaround time (TAT) can be shortened, which is very beneficial for ASICs whose selling point is short delivery times, and the effect is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block configuration diagram showing details of the digital-to-analog conversion circuit block. FIG. 3 is a block diagram showing a second embodiment of the present invention. FIG. 4 is a circuit diagram showing details of the cross-point switch circuit. FIG. 5 is a time chart of the test signal generation circuit. FIG. 6 is a block diagram showing a conventional example. 1.1a...User circuit, 2.2a, 109...Selector circuit, 3.3a...Digital-to-analog conversion circuit (D/A), 4-=test terminal, 5.9.9a, 1
08... Control terminal, 6.6a... Input/output terminal, 7.
7a...Output terminal,...Counter circuit, 10.10
a, 107...clock input terminal, 11.102
~105...Digital input terminal, 13...Digital-to-analog conversion circuit block (D/A block)
, 100... cross point switch circuit, 101...
- Analog input/output terminal, ... analog switch, 114 ... buffer circuit, test signal generation circuit, 106 ... 110 ... D latch circuit, 111 112 ... NAND circuit, 113. 115...Inverter circuit.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit for a specific application that includes digital and analog basic blocks that have a predetermined function and whose input/output characteristics are guaranteed in advance, a plurality of inputs necessary for the predetermined function. a terminal, a first circuit block that performs said function, a second circuit block that generates a test signal for said first circuit block, and a signal from said input terminal and a test signal from said second circuit block. A semiconductor characterized by comprising a basic block including a third circuit block that switches signals and inputs the signals to the first circuit block, and at least one terminal for controlling the third circuit block. integrated circuit.