JPH03288368A - Digital signal connection recording method and digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent abnormal tones at an editing point by controlling a RAM control means and a recording means while detecting whether the recording means is set at a recording stop enable position on a disk or not in stopping and restarting recording to the disk. CONSTITUTION:When temporarily stopping recording to a recordable disk 109, it is detected whether the recording means is set at the recording stop enable position on the disk 109 or not. When the means is set at the recording stop enable position, the control of a RAM control means 103 and the recording of the recording means is respectively stopped. In restarting the recording of digital signals, it is detected whether the recording means is set at the recording stop enable position or not, and the control of the RAM control means 103 and the recording of the recording means is started. Thus, even when the recordable disk continuously recording the data of the digital signals is repro duced by a general CD player, the abnormal sounds can be prevented from being generated at the editing point.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal splice recording method and a digital signal recording/reproducing apparatus.

[Conventional technology]

A normal compact disc (hereinafter referred to as CD) has
Sampling frequency 44.1kHz, quantization Bi.

A 16-bit PCM audio signal (digital signal) is recorded in a predetermined format. Also, the CD
Currently, CD players that play digital signals from
It is widely used as a playback-only audio device for consumer use.

Incidentally, in recent years, studies have been underway on discs that are compatible with this CD recording format and on which digital signals can be recorded (hereinafter referred to as recordable discs).

Regarding this key recordable disc, conventionally, for example,
JAS Conference 88 Proceedings, pages 48 to 51
As discussed in this article, types that can record only -degrees and rewritable types are being considered.

However, when recording a digital signal in the CD recording format, for example, as shown in Japanese Patent Laid-Open No. 574629, a correction code is first added to the digital signal, and then a simple delay type code is added to the digital signal. Interleaving is applied to the data, and a correction code is added again.

Therefore, when recording digital signals on a recordable disc in the CD recording format, it would be impossible to simply record, for example, by temporarily stopping recording at a point during recording, and then re-recording at that point (hereinafter referred to as , editing point) (hereinafter, such recording is referred to as spliced recording).
Since interleaving deviation occurs at the editing point, there is a problem in that when a digital signal recorded in such a spliced manner is played back, abnormal noise is generated at the editing point.

By the way, although it is not intended to deal with the occurrence of abnormal noise due to interleave deviation caused by such continuous recording, for example, conventionally, the JAS Conference "86 Proceedings (D
-3> On pages 90 to 93, regarding the occurrence of abnormal noise due to interleaving deviation due to track jump during cue review of a CD player. Countermeasures are listed.

In other words, in this proposed example, when the occurrence of a track jump during playback is detected, the data immediately before the detection is interpolated as is until the interleaving is resolved, and an error flag is set to correct the error. By preventing this, the occurrence of abnormal noise was suppressed.

[Problem to be solved by the invention]

However, the above-mentioned proposed examples are only for the generation of abnormal noise due to interleaving deviation caused by track jumps, and can be directly applied to the generation of abnormal noise due to interleaving deviation caused by splicing recording on recordable discs. Even if it is used against others, there are the following problems.

That is, in the previously proposed example described above, interleaving deviations can be detected by detecting the occurrence of track jumps during playback, but interleaving deviations due to spliced recording on recordable discs (i.e., edit point The interleaving shift that occurs at the border is
There is a problem in that it cannot be detected during playback unless some kind of detection means is considered.

Furthermore, even if the interleaving shift can be detected, as in the previously proposed example mentioned above, the data immediately before the detection is interpolated as is until the interleaving is solved, and an error flag is set to prevent erroneous correction. In the method of preventing this, there is also the problem that the quality of the reproduced sound inevitably deteriorates before and after the editing point.

Furthermore, even if a CD player that overcomes all of the above-mentioned problems, that is, a CD player that has a function to reduce the occurrence of abnormal noise due to interleave deviation caused by spliced recording, would still be able to record spliced recordings. The generation of abnormal noise can only be reduced when the disc is played on a CD player that has this key function, and the CDs that are currently widely used without such a function
When playing back on a player, the problem of abnormal noise still remains, so this does not solve the fundamental problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a digital signal splicing recording method for splicing and recording digital signals on a recordable disc without causing interleaving deviation.

Another object of the present invention is to provide a digital signal recording and reproducing apparatus that can record digital signals in a continuous manner using such a digital signal continuous recording method.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a RAM for storing digital signals and a RAM for controlling the RAM.
A control means, a correction means for adding first and second correction codes to a digital signal, a modulation means for modulating the digital signal, and a recording means for recording the digital signal on a disk. The digital signal is
After being written into the RAM under the control of the AM control means, the first correction code is added to the read digital signal by the correction means, and the first correction code is added to the read digital signal by the correction means.
The digital signal to which the correction code of
The digital signal is written into the RAM under the control of the control means, and the written digital signal is subjected to simple delay type interleaving under the control of the RAM control means, and then read, and the read digital signal is subjected to the interleaving by the correction means. 2, and the digital signal to which the second correction code has been added is written into the RAM under the control of the RAM control means, read out, and the read digital signal is modulated by the modulation means. In the digital signal recording and reproducing device capable of modulating the digital signal and recording it on the disk by the recording means, when temporarily stopping recording of the digital signal on the disk, the recording means can stop recording on the disk. If it is detected that the recording means is at the position where recording can be stopped, the RAM
The control by the control means and the recording by the recording means are respectively stopped, and when recording of a digital signal is started again, it is detected whether or not the recording means is at the position where recording can be stopped, and the recording means is stopped. When it is detected that the recording device is at the position where recording can be stopped, control by the RAM control means and recording by the recording means are respectively started.

[Effect]

As described above, when temporarily stopping the recording of a digital signal on the disk, it is detected whether or not the recording means is at a position on the disk where recording can be stopped, and the recording means is placed at a position where recording can be stopped. When it is detected that the room number is present, the control by the RAM control means and the recording by the recording means are respectively stopped. As a result, the digital signal data stored in the RAM but not yet recorded on the disk is held as is in the RAM while recording is stopped.

Thereafter, when starting recording of a digital signal again, it is detected whether or not the recording means is at the position where recording can be stopped, and when it is detected that the recording means is at the position where recording can be stopped, the recording means is at the position where recording can be stopped. Control by the RAM control means and recording by the recording means are respectively started.

As a result, the data of the new digital signal is transferred to the RA.
New data can be sequentially written into M and connected to the previously held data in the RAM. Furthermore, since the interleaving is performed after the two are connected, it is possible to record on the disk without causing an interleaving shift at the connection between the two, that is, at the editing point.

Therefore, even if a disc on which digital signals are recorded in this manner is played back by a general CD player that is currently widely used, no abnormal noise will be generated at the editing point due to interleaving deviation.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing the flow of recording operations in a digital signal recording and reproducing apparatus as a first embodiment of the present invention, and FIG. 2 is a block diagram showing a digital signal recording and reproducing apparatus as a first embodiment of the present invention. Figure.

In Figure 2, 1 is a frame synchronization signal, 2 is a subcode synchronization signal, 3 is a clock, and 4 is a random access signal.
Memory (hereinafter referred to as RAM) address generation long,
5 is a recording stop signal, 6 is a recording start signal, 7 is a clock control circuit, 101 is an analog/digital (hereinafter referred to as A/D)
102 is a RAM, 103 is a RAM control circuit for generating addresses, etc., 104 is an error correction circuit (ECV), 105 is a subcode processing circuit, 106
is Eight to Fourteen ° Modulation (
(hereinafter referred to as EFM) modulation circuit, 107 is a preamplifier;
108 is a laser diode, 109 is a recordable disk, 110 is a servo, 111 is a system control microcomputer, 112 is a data strobe, 113 is a synchronization signal detection protection circuit, 114 is a timing generation circuit, 115 is a crystal oscillator, 116 is an EFM demodulation 117 is an interpolation processing circuit, and 118 is a digital/analog (hereinafter referred to as D/A) converter. In addition, the part surrounded by the broken line is 1
This is the part of the chip that is integrated as an LSI.

Further, FIG. 3 is an explanatory diagram for explaining the recording operation in the digital signal recording/reproducing apparatus of FIG. 2.

That is, FIG. 3 shows that the digital signal is stored in the RAM 102, read out, and then stored on the recordable disc 109.
In order to explain the series of processing up to the time when the digital signal is recorded, the data of the digital signal is shown as a RAM map conveniently arranged in units of one symbol.

In FIG. 3, a circle indicates one symbol of data in a digital signal, and the address of each data is advanced in the right column. Further, A indicates data recorded before recording is stopped when continuous recording is performed, and B indicates data recorded after recording is resumed. Also, 20
Each of the arrows 1 to 204 indicates a specific process to be described later, and each process progresses from left to right for each piece of data as time passes.

Now, the operation during recording in this embodiment will be explained.

In FIG. 2, first, the input digital signal (if input as an analog signal, the A/D converter 1
The digital signal obtained by A/D conversion at 01) is R
The RAM is controlled by the AM control circuit 103.
102. At this time, as shown by the arrow 201 in FIG. 3, the digital signal data is composed of a total of 24 symbols of data (data in one vertical column in FIG. 3) of 12 channels of L and R6 samples as one block according to the CD format. , are stored in the RAM 102. In addition, the RAM 102 by the RAM control circuit 103
This control is performed by generating addresses in accordance with the RAM address generation check 4 from the clock control circuit 7.

Next, the digital signal data stored in the RAM 102 is read out under the control of the RAM control circuit 103 and input to the error correction circuit 104, where it is converted into four symbols as shown by the arrow 202 in FIG. 0
After 2 codes are added, RA is added as a new block.
Under the control of the M control circuit 103, the R
Stored in AMIO2.

Next, the digital signal data (28 symbols of data) stored in the RAM 102 is transferred to the arrow 203 in FIG.
As shown in FIG. 3, after simple delay interleaving processing is performed under the control of the RAM control circuit 103, the data is read out and input to the error correction circuit 104.
Therefore, after four symbols of C1 code are added, it is stored in the RAM 102 again under the control of the RAM control circuit 103 as a new apron.

Then, as shown by the arrow 204 in FIG.
The digital signal data (32 symbol data, that is, the data in one diagonal row in FIG. 3) stored in the RAM control circuit 103 is read out under the control of the RAM control circuit 103.

The above processing process is step 1 shown in FIG.

Next, the digital signal data read out from the RAM 102 is modulated by the EFM modulation circuit 106, amplified by the preamplifier 107, and then sent to the laser diode 10B.
is written on the recordable disc 109 by.

At this time, according to the output of the preamplifier 107, the servo 11
0 controls the rotation of the recordable disk 109 and the laser diode 108.

The above processing process is step 2 shown in FIG.

Next, when an instruction to stop recording is input to the system control microcomputer 111 from the outside, the system control microcomputer 111 outputs a recording stop signal 5 to the clock control circuit 7.

The above processing process is step 3 shown in FIG.

Next, upon receiving the recording stop signal 5 from the system control microcomputer 111, the clock control circuit 7 receives the subcode synchronization signal 2 obtained from the subcode processing circuit 105.
detects a position where recording can be stopped on the recordable disc 109 determined by the CD recording format, and when that position is detected, stops the RAM address generation circuit 4 outputting to the RAM control circuit 103. It works like that.

FIG. 4(a) is a timing diagram showing the timing of the subcode synchronization signal in FIG. 2, and FIG. 4(b) is a timing diagram showing the timing of the data of the digital signal on the recordable disc 109 in FIG. be.

That is, when the clock control circuit 7 receives the recording stop signal 5 and then obtains the subcode synchronization signal 2, the clock control circuit 7 receives, for example, six blocks of data from the subcode synchronization signal 2, as shown in FIG. The advanced position is detected as the position where recording can be stopped.

The above processing process is step 4 shown in FIG.

In this way, when the RAM address generation mechanism 4 from the clock control circuit 7 is stopped, the RAM control circuit 103 stops controlling the RAM 102, so that the RAM
Writing data to RAM 102 and reading data from RAM 102 are not performed. Therefore, RAM10
Data stored in the RAM 102 and not yet recorded on the recordable disc 109 is retained as is in the RAM 102, and is corrected by the error correction circuit 104.

Recordable disc 1 by adding C2 code, interleaving processing in RAM 102, and laser diode 10B.
Writing to 09 is also not performed.

In the manner described above, recording of digital signal data onto the recordable disc 109 can be temporarily stopped.

The above processing process is step 5 shown in FIG.

Next, when an instruction to start recording is input to the system control microcomputer 111 from the outside, the system control microcomputer 111 outputs a recording start signal 6 to the clock control circuit 7.

When the clock control circuit 7 receives the recording start signal 6 from the system control microcomputer 111, the clock control circuit 7 can stop the recording on the recordable disc 109 by using the subcode synchronization signal 2 obtained from the subcode processing circuit 105. Once the position is detected, the output of the RAM address generation circuit 4 to the RAM control circuit 103 is restarted.

The above processing process is step 6 shown in FIG.

In this way, when the input of the RAM address generation block 4 from the clock control circuit 7 is started, the RAM control circuit 103 starts controlling the RAM 102 again.
Writing data to RAM 102 and RAM 10
Data is read from 2. Therefore, C1. Addition of C2 code, RAM102
Interleaving processing at , writing to the recordable disk 109 by the laser diode 108, etc. are also performed, and the processing process returns to step 1 shown in FIG.

As described above, recording of digital signal data (i.e., data A shown in FIG. 3) on the recordable disk 109 is temporarily stopped, and then the data (i.e., data B shown in FIG. 3) is recorded again. Even if you start recording (data), if recording is stopped,
Since the data of A is held in RAMIO2, after resuming recording, the data of B is sequentially stored in the RAM 102.
data can be connected. Furthermore, since the interleaving process is performed after the two are connected, it is possible to record on the recordable disc 109 without interleaving deviation occurring at the connection between the two, that is, at the editing point.

Therefore, even if the recordable disc 109 on which digital signal data is recorded in this way is played back by a general CD player that is currently widely used, abnormal noise will be generated at the editing point due to interleaving deviation. Never.

The above is the operation during recording in this embodiment.

Next, the operation during reproduction in this embodiment will be explained.

The operation during playback is no different from the playback operation of general CD players that are currently widely used, so a brief explanation will be provided.

Disc 10 recordable by laser diode 108
The data of the digital signal reproduced from the preamplifier 107. It is input to the EFM demodulation circuit 116 via the data strobe 112, demodulated there, and then stored in the RAM.
RAM 1 is controlled by the control circuit 103.
It is stored in 02.

Next, the digital signal data stored in the RAM 102 is read out under the control of the RAM control circuit 1ff11iB103, inputted to the error correction circuit 104, where CI correction is performed, and then under the control of the RAM control circuit 103. , are stored in the RAM 102 again.

Next, the digital signal data stored in the RAM 102 is read out after being deinterleaved under the control of the RAM control circuit 11i103.
The data is input to the error correction circuit 104, where 02 correction is performed, and then stored in the RAMIO2 again under the control of the RAM control circuit 103.

Therefore, the digital signal stored in the RAM 102 is
It is read out under the control of the RAM control circuit 103, subjected to interpolation processing by the interpolation processing circuit 117, and then output (when outputting as an analog signal,
(D/A converter 118 performs D/A conversion before outputting)
.

The above is the operation during reproduction in this embodiment.

Next, the operation during recording in this embodiment is different from the operation described above, and is different from the operation described above. The operation will be explained.

The operations until recording stops are the same as those described above, so the subsequent operations will be explained first.

FIG. 5 is an explanatory diagram for explaining another recording operation in the digital signal recording/reproducing apparatus of FIG. 2.

That is, like FIG. 3, FIG. 5 shows a RAM map in which digital signal data is conveniently arranged in symbol units.

While recording is stopped, the data in the RAM 102 is not retained, so when recording starts again, the A/D converter 10
1, by muting the analog signal “
As shown in FIG. 5, the "0" data is stored in the RAM 102 only to the extent that no erroneous correction occurs.

Subsequently to the "0" data, data to be recorded (ie, B data) is stored in the RAM 102.

The subsequent operations are similar to those described above.

As described above, even if the digital signal data stored in the RAM 102 cannot be retained while recording is stopped, by inserting "0" data instead, it is possible to record without causing interleaving deviation at the editing point. It can be recorded on the disc 102.

Therefore, recordable discs recorded in this way,
Even when played back by a general CD player that is currently widely used, no abnormal noise is generated at the editing point due to interleaving deviation.

FIG. 6 is a block diagram showing a digital signal recording/reproducing apparatus as a second embodiment of the present invention.

In FIG. 6, 401 is the RAM 102 in FIG.
402 is a fade-in/fade-out processing circuit, and 4.3 is a data bus.

In this embodiment, when performing continuous recording of digital signals, fade-in/fade-out processing is performed on data before and after an editing point.

Further, FIG. 7 is an explanatory diagram for explaining the recording operation in the digital signal recording/reproducing apparatus of FIG. 6.

That is, like FIGS. 3 and 5 described above, FIG. 7 shows a series of processes from when a digital signal is stored in the RAM 401 until it is read out and recorded on the recordable disc 109. In order to explain this, a RAM map is shown in which digital signal data is conveniently arranged in units of one symbol.

Now, the operation during recording in this embodiment will be explained.

In FIG. 6, first, similar to the first embodiment described above,
The input digital signal (if input as an analog signal, the digital signal obtained by A/D conversion by the A/D converter 101) is sent to the RAM control circuit 1.
03, as shown by the arrow 201 in FIG.
It is stored in AM401.

Here, in order for the fade-in/fade-out processing circuit 402 to perform normal fade-in/fade-out processing, the RAM 401 needs to store a large amount of digital signal data, so the storage capacity is increased as shown in FIG. This is more than the RAM 102 in FIG.

Next, the digital signal data (24 symbols of data) stored in the RAM 401 is read out under the control of the RAM control circuit 103 and input to the fade-in/fade-out processing circuit 402 via the data bus 403. .

FIG. 8 is a block diagram showing a specific example of the fade-in/fade-out processing circuit 402 in FIG. 6.

In FIG. 8, 502 and 503 are 8-bit latches, 5
04 is a multiplication calculator, 505 is a read-only memory (
(hereinafter referred to as ROM), 506 is a 16-bit branch, 5
07 is a gate circuit.

Further, FIG. 9 is an explanatory diagram for explaining the fade-in/fade-out processing performed by the fade-in/fade-out processing circuit 402 of FIG. 6.

In FIG. 9, the vertical axis represents the level of the digital signal, and the horizontal axis represents time. Further, a solid line 901 indicates a temporal change in the level of a digital signal during fade-out processing of the fade-in/fade-out processing performed by the fade-in/fade-out processing circuit in FIG. shows the temporal change in the level of the digital signal.

Digital signal data input to the fade-in/fade-out processing circuit 402 (24 symbols of data)
As shown in FIG. 8, the 8 bits are sequentially latched in 8 bit launches 502 and 503 in a time-division manner.

The 8-pin data latched in the 8-bit latches 502 and 503 is a total of 16 bits.

The multiplication is manually entered into the calculator 504, where it is integrated using a constant value read out from the ROM 505. The obtained integrated value is input to the gate circuit 507 via the 16-bit transistor 506, where it is converted to 8-bit data and output as output data from the fade-in/fade-out processing circuit 402.

The data output from the fade-in/fade-out processing circuit 402 is sent to the RAM again via the data bus 403 under the control of the RAM control circuit 103.
It is stored in M102.

Next, the digital signal data stored in the RAM 102 is read out again under the control of the RAM control circuit 103, and inputted to the error correction circuit 104.
The subsequent operations are similar to those of the first embodiment described above.

During recording, when an instruction to stop recording is input to the system control microcomputer 111 from the outside, the system control microcomputer 111 outputs a fade-out start signal (not shown) to the fade-in/fade-out processing circuit 402.

When the fade-in/fade-out processing circuit 402 receives a fade-out start signal from the system control microcomputer 111, the value read out from the ROM 505 shown in FIG. Level is 9th
As shown by a solid line 901 in the figure, it attenuates over time. The amount of attenuation at this time is different from the amount of attenuation in the antenna processing indicated by *902, and changes linearly, so that the auditory sense of discomfort is suppressed.

In this way, the fade-in/fade-out processing circuit 40
At step 2, the digital signal is subjected to fade-out processing.

After that, the system control microcomputer 111 outputs the recording stop signal 5 to the black/7 line control circuit 7, and the subsequent operation is the same as that of the first embodiment described above.

Next, when an instruction to start recording is input to the system control microcomputer 111 from outside while recording is stopped, the system control microcomputer 111 outputs a recording start signal 6 to the clock control circuit 7 and also outputs a recording start signal 6 to the fade-in/fade-out processing circuit 402. Then, a fade-in start signal (not shown) is output.

When the clock control circuit 7 receives the recording start signal 6 from the system control microcomputer 111, the clock control circuit 7 can stop the recording on the recordable disc 109 by using the subcode synchronization signal 2 obtained from the subcode processing circuit 105. Once the position is detected, the output of the RAM address generation circuit 4 to the RAM control circuit 103 is restarted.

On the other hand, when the fade-in/fade-out processing circuit 402 receives a fade-in start signal from the system control microcomputer 111, the ROM 502 shown in FIG.
The value read out gradually increases over time,
The level of the digital signal output from gate circuit 507 increases with time.

In this way, the fade-in/fade-out processing circuit 40
2, fade-in processing is performed on the digital signal.

As described above, according to this embodiment, when performing continuous recording of digital signals, fade-in/fade-out processing is applied to the data before and after the edit point. It is possible to obtain reproduced sound that does not generate any abnormal noise and also does not give a sense of discomfort.

FIG. 10 is a block diagram showing a digital signal recording/reproducing apparatus as a third embodiment of the present invention.

In FIG. 1O, 8 is a reproduction stop signal, 9 is a reproduction start signal, 10 is a RAM address generation check, 701 is a recording system RAM, 702 is a reproduction system RAM, and 703 is a recording system RA.
M control circuit, 704 a reproduction system RAM control circuit, and 705 a clock control circuit.

In this embodiment, during recording on the recordable disc 109, recording is temporarily stopped as a continuous recording of digital signals, and
At that time, the data of the digital signal recorded up to that point is reproduced, the recording state is confirmed, and then recording is started again.

Now, the operation during recording in this embodiment will be explained.

First, a manually input digital signal (in the case of input as an analog signal, a digital signal obtained by A/D conversion by the A/D converter 101) is sent to the recording system under the control of the recording system RAM control circuit 703. RAM70
It is stored in 1.

At this time, the recording system RAM 701 is controlled by the recording system RAM control circuit 703 by generating addresses in accordance with the RAM address generation check 4 from the clock control circuit 705.

Next, the digital signal data stored in the recording system RAM 701 is read out under the control of the recording system RAM control circuit 703, and subsequent operations are similar to those of the first embodiment described above.

Thereafter, when an instruction to stop recording is input to the system control microcomputer 111 from the outside during recording, the system control microcomputer 111 outputs a recording stop signal 5 to the clock control circuit 705.

The clock control amount 1W 705 is a subcode synchronization signal 2 obtained from the subcode processing circuit 105 when the recording stop signal 5 is received from the system control microcomputer 111.
As a result, a position where recording can be stopped on the recordable disk 109 is detected, and once the position is detected, the RAM address generation circuit 4 outputting to the recording system RAM control circuit 703 is stopped.

In this way, when the RAM address generation check 4 from the clock control circuit 705 is stopped, the recording system RAM control circuit 703 stops controlling the recording system RAM 701, so that writing of data to the recording system RAM 701,
Also, data is not read from the recording system RAM 701. Therefore, data stored in the recording system RAM 701 that has not yet been recorded on the recordable disc 109 is held as is in the recording system RAM 701, and the data is not affected by the addition of CI and C2 codes by the error correction circuit 104. Also, interleaving processing in the recording system RAM 701 and writing to the recordable disk 109 by the laser diode 108 are not performed.

Next, in order to check the recording status, an instruction to start playback is input to the system control microcomputer 111 from the outside.
The system control microcomputer 111 outputs a reproduction start signal 9 to the clock control circuit 705. When the clock control circuit 705 receives the reproduction start signal 9 from the system control microcomputer 111, it operates to start outputting the RAM address production signal IO to the reproduction RAM control circuit 704.

As a result, the reproduction system RAM control circuit 704
A reproducing operation is performed by controlling the reproducing RAM 702 by generating an address according to the RAM address generation lock 10 from the clock control circuit 705.

When the playback operation is performed in this way and the recording state of the data of the previously recorded digital signal is confirmed, an instruction to stop playback is input from the outside to the system control microcomputer 111, and the system control microcomputer 111 performs clock control. A reproduction stop signal 8 is output to the circuit 705. When the clock control circuit 705 receives the reproduction stop signal 8 from the system control microcomputer 111, the clock control circuit 705 starts the reproduction system RA.
It operates to stop the RAM address generation lock 10 outputting to the M control circuit 704.

When the RAM address generation lock 10 from the clock control circuit 705 is stopped, the reproducing RAM control circuit 704 stops controlling the reproducing RAM 702, thereby stopping the reproducing operation.

Next, in order to start recording again, when an instruction to start recording is input to the system control microcomputer 111 from the outside, the system control microcomputer 111 outputs a recording start signal 6 to the clock control circuit 705. The clock control circuit 705 is a system control microcomputer Ill.
When the recording start signal 6 is received from the subcode processing circuit 105, the subcode synchronization signal 2 obtained from the subcode processing circuit 105 is used to detect the recordable stop position on the recordable disc 109 where recording was previously stopped. Then, the output of the RAM address generation signal 4 to the recording system RAM control circuit 703 is started again.

In this way, when the clock control circuit 705 starts inputting the RAM address generation lock 10, the recording system RA
The M control circuit 703 starts controlling the recording system RAM 701 again, and the recording operation is started.

As described above, according to this embodiment, during recording on the recordable disc 109 as continuous recording of digital signals,
Even if you stop recording once, reproduce the previously recorded digital signal data, check the recording status, and then start recording again, the previous data will be lost to the recording system RA while recording is stopped.
Since the data is held in M701, subsequent data is sequentially stored in the recording system RAM 701 after recording is restarted, so that the subsequent data can be connected to the previous data in the recording system RAM 701.

Therefore, similarly to the first embodiment described above, the recordable disc 1
09, and even when played back by a CD player on a boat, there will be no abnormal noise caused by interleaving deviation at the editing point.

〔Effect of the invention〕

As explained above, according to the present invention, recording of digital signal data on a recordable disk is temporarily stopped, and
After that, even if you start recording data again, the previous data is held in the RAM while recording is stopped, so after restarting recording, the later data is stored in the RAM sequentially, so that the data is stored in the RAM. It is possible to connect the previous data with the subsequent data, and since the two data are interleaved after being connected, there is no interleaving difference between the two, that is, at the editing point. , can be recorded on recordable discs.

Therefore, even if a recordable disc on which digital signal data is recorded in this way is played back by a general CD player that is currently widely used, abnormal noises may occur due to interleaving deviation at the editing point. Therefore, it has the effect of reducing auditory discomfort caused by the generation of abnormal noise.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the flow of recording operations in a digital signal recording and reproducing apparatus as a first embodiment of the present invention, and FIG. 2 is a block diagram showing a digital signal recording and reproducing apparatus as a first embodiment of the present invention. 3 is an explanatory diagram for explaining the recording operation in the digital signal recording and reproducing apparatus of FIG. 2, FIG. 4(a) is a timing diagram showing the timing of the subcode synchronization signal in FIG.
Figure (b) is a timing diagram showing the timing of digital signal data on the recordable disk 109 in Figure 2, and Figure 5 is an explanation for explaining other recording operations in the digital signal recording and reproducing apparatus in Figure 2. 6 is a block diagram showing a digital signal recording/reproducing apparatus as a second embodiment of the present invention, and FIG. 7 is an explanation for explaining the recording operation in the digital signal recording/reproducing apparatus of FIG. 6. 8 is a block diagram showing an example of the fade-in/fade-out processing circuit 402 in FIG. 6, and FIG.
The figure shows the fade-in/fade-out processing circuit 4 in Figure 6.
FIG. 10 is a block diagram showing a digital signal recording and reproducing apparatus as a third embodiment of the present invention. Explanation of symbols 2...Subcode synchronization signal, 4.10...RAM address generation check, 5...Record stop signal, 6...
Recording start signal, 7,705... Clock control circuit, 8
... Playback stop signal, 9... Playback start signal, 102,
401...RAM, 103...RAM control circuit, 104...Error correction circuit, 106...EFM
Modulation circuit, 108...Laser diode, 109...
- Recordable disc, 111... System control microcomputer, 402... Fade-in/fade-out processing circuit, 701... Recording system RAM, 702...
Reproduction system RAM, 703...Recording system RAM control circuit, 704...Reproduction system RAM control circuit. Figure 1

Claims (1)

[Claims] 1. Random access memory (hereinafter referred to as RAM) that stores digital signals, and R that controls the RAM.
comprising an AM control means, a correction means for adding first and second correction codes to the digital signal, a modulation means for modulating the digital signal, and a recording means for recording the digital signal on a disk; writing the digital signal into the RAM under the control of the RAM control means, and then reading it;
The first correction code is added to the read digital signal by the correction means, and the digital signal to which the first correction code is added is written into the RAM under the control of the RAM control means. The read digital signal is subjected to simple delay interleaving under the control of the RAM control means, and then read out, and the correction means adds the second correction code to the read digital signal. A digital signal to which a correction code has been added is written into the RAM under the control of the RAM control means, and then read out, and the read digital signal is modulated by the modulation means,
In a digital signal recording/reproducing device capable of recording onto the disc by the recording means, temporarily stopping recording of the digital signal onto the disc;
After that, in the digital signal splice recording method in which recording of the digital signal is started again, when recording the digital signal on the disk is temporarily stopped, it is necessary to check whether the recording means is at a position on the disk where recording can be stopped. When it is detected that the recording means is in the position where recording can be stopped, the control by the RAM control means and the recording by the recording means are respectively stopped, and when starting recording of the digital signal again, ,
Detecting whether or not the recording means is at the position where recording can be stopped, and when detecting that the recording means is at the position where recording can be stopped, control by the RAM control means and recording by the recording means are respectively started. A digital signal splicing recording method characterized by the following. 2. A RAM that stores a digital signal, a RAM control means that controls the RAM, a correction means that adds first and second correction codes to the digital signal, a modulation means that modulates the digital signal, and a RAM that controls the RAM. recording means for recording on a disk, and reading the input digital signal after writing it into the RAM under the control of the RAM control means;
The first correction code is added to the read digital signal by the correction means, and the digital signal to which the first correction code is added is written into the RAM under the control of the RAM control means. The read digital signal is subjected to simple delay interleaving under the control of the RAM control means, and then read out, and the correction means adds the second correction code to the read digital signal. A digital signal to which a correction code has been added is written into the RAM under the control of the RAM control means, and then read out, and the read digital signal is modulated by the modulation means,
A digital signal recording and reproducing apparatus capable of recording on the disk by the recording means, further comprising: a detection means for detecting whether or not the recording means is at a position on the disk where recording can be stopped; and control means for controlling a control operation and a recording operation by the recording means, respectively, and when temporarily stopping recording of a digital signal on the disk, the detecting means detects when the recording means is at the position where recording can be stopped. When the control means detects that the
When the control by the RAM control means and the recording by the recording means are respectively stopped and recording of the digital signal is started again, the detection means detects that the recording means is at the position where recording can be stopped. When I did,
A digital signal recording and reproducing apparatus, wherein the control means starts control by the RAM control means and recording by the recording means, respectively.