JPH03280528A - Formation of polycrystalline semiconductor thin film - Google Patents
Formation of polycrystalline semiconductor thin filmInfo
- Publication number
- JPH03280528A JPH03280528A JP8204990A JP8204990A JPH03280528A JP H03280528 A JPH03280528 A JP H03280528A JP 8204990 A JP8204990 A JP 8204990A JP 8204990 A JP8204990 A JP 8204990A JP H03280528 A JPH03280528 A JP H03280528A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- semiconductor thin
- crystal
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000013078 crystal Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 abstract description 28
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 238000000137 annealing Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract 5
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000007787 solid Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000002425 crystallisation Methods 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 239000007790 solid phase Substances 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野]
本発明は、薄膜トランジスタの製造等に用いられる多結
晶半導体薄膜の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a polycrystalline semiconductor thin film used for manufacturing thin film transistors and the like.
(発明の概要〕
本発明は、上記の様な多結晶半導体薄膜の形成方法にお
いて、非晶質半導体薄膜の所望部分に形成した結晶化領
域を種として結晶成長を行わせることによって、結晶粒
径が大きく結晶粒径のばらつきも少ない多結晶半導体薄
膜を形成することができる様にしたものである。(Summary of the Invention) The present invention provides a method for forming a polycrystalline semiconductor thin film as described above, in which crystal grain size is This makes it possible to form a polycrystalline semiconductor thin film with a large grain size and little variation in crystal grain size.
[従来の技術]
液晶デイスプレィや積層CMO3型O3AM等では薄膜
トランジスタが用いられており、薄膜トランジスタは多
結晶半導体薄膜に形成されるのが一般的である。[Prior Art] Thin film transistors are used in liquid crystal displays, stacked CMO3 type O3AMs, and the like, and thin film transistors are generally formed in polycrystalline semiconductor thin films.
従って、移動度を大きくしたりサフスレソショルドスイ
ングを小さくじたりして薄膜トランジスタを高性能化す
るためには、多結晶半導体薄膜の結晶粒径を大きくする
必要がある。Therefore, in order to improve the performance of a thin film transistor by increasing the mobility or decreasing the threshold swing, it is necessary to increase the crystal grain size of the polycrystalline semiconductor thin film.
そこで、多結晶半導体薄膜にSi”等をイオン注入する
ことによって一旦非晶質化し、この非晶質半導体薄膜に
600°C程度の比較的低温の固相成長アニールを施す
方法が行われている(例えば特開昭61−127118
号公報)。Therefore, a method is used in which a polycrystalline semiconductor thin film is temporarily made amorphous by ion-implanting Si'' or the like, and then this amorphous semiconductor thin film is subjected to solid phase growth annealing at a relatively low temperature of about 600°C. (For example, JP-A-61-127118
Publication No.).
しかし上述の従来の方法は、非晶質半導体薄膜中にラン
ダムに発生した核を種として結晶成長を行わせているだ
けである。このため、結晶粒径は大きくても2μm前後
であり、しかも結晶粒径自体がばらついている。However, the above-mentioned conventional method merely causes crystal growth using randomly generated nuclei in an amorphous semiconductor thin film as seeds. Therefore, the crystal grain size is around 2 μm at most, and the crystal grain size itself varies.
一方、Si”のドーズ量を多くして非晶質化の程度を高
くすれば、ランダムな核発生を抑制して、結晶粒径を大
きくすることができる。しかし、今度は核発生の時間自
体が極度に長くなって、実用的ではない。On the other hand, if the degree of amorphization is increased by increasing the dose of Si'', random nucleation can be suppressed and the crystal grain size can be increased.However, this time the nucleation time itself is extremely long and is not practical.
[課題を解決するための手段]
本発明による多結晶半導体薄膜の形成方法では、非晶質
半導体薄膜15の所望部分に結晶化領域17を形成し、
前記結晶化領域17を種として前記非晶質半導体薄膜1
5で結晶成長を行わせる様にしている。[Means for Solving the Problems] In the method for forming a polycrystalline semiconductor thin film according to the present invention, a crystallized region 17 is formed in a desired portion of an amorphous semiconductor thin film 15,
The amorphous semiconductor thin film 1 is grown using the crystallized region 17 as a seed.
5 to cause crystal growth.
[作用]
本発明による多結晶半導体薄膜の形成方法では、非晶質
半導体薄膜15の所望部分に形成した結晶化領域17を
結晶成長の種としており、結晶成長の種をランダムには
発生させていないので、結晶粒径の制御が可能である。[Function] In the method for forming a polycrystalline semiconductor thin film according to the present invention, the crystallized region 17 formed in a desired portion of the amorphous semiconductor thin film 15 is used as a seed for crystal growth, and the seeds for crystal growth are not randomly generated. Therefore, the crystal grain size can be controlled.
以下、本発明の一実施例を、第1図及び第2図を参照し
ながら説明する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
本実施例では、第1A図に示す様に、石英等の基板11
上にCVDによって厚さ5000人程度程度iOz膜1
2を堆積させ、更にこのSiO□膜12′りに厚さ80
0人程大の多結晶Si膜13を堆積させる。In this embodiment, as shown in FIG. 1A, a substrate 11 made of quartz or the like is used.
On top, apply an iOz film 1 to a thickness of about 5000 by CVD.
2 is deposited, and a thickness of 80 mm is further deposited on this SiO□ film 12'.
A polycrystalline Si film 13 about the size of 0 people is deposited.
そして、Si”14を40keV程度の工♀ルギと5
X 1015cl”以上のドーズ量とで多結晶Si膜1
3の全面へイオン注入することによって、第1B図に示
す様に、この多結晶Si膜13を非晶質Si膜15にす
る。Then, Si”14 was heated to about 40 keV and 5
Polycrystalline Si film 1 with a dose of 1015 cl” or more
By implanting ions into the entire surface of the polycrystalline Si film 13, the polycrystalline Si film 13 is transformed into an amorphous Si film 15, as shown in FIG. 1B.
次に、第1B図に示す様に、非晶質Si膜15が溶融し
ない程度のエネルギのエキシマレーザ光16を、非晶質
Si膜15の所望部分にのみ選択的に照射する。Next, as shown in FIG. 1B, only desired portions of the amorphous Si film 15 are selectively irradiated with excimer laser light 16 having an energy level that does not melt the amorphous Si film 15.
この様な照射を行うには、ステップアンドリピートによ
って間引きショットを行えばよい。エキシマレーザ光1
6としては、波長308nmのXeCl等を用いること
ができる。To perform such irradiation, thinning shots may be performed by step-and-repeat. Excimer laser light 1
6, XeCl or the like having a wavelength of 308 nm can be used.
この結果、非晶質Si膜15のうちでエキシマレーザ光
16が照射された部分のみが再結晶化し、微小な結晶化
領域17が形成される。As a result, only the portion of the amorphous Si film 15 irradiated with the excimer laser beam 16 is recrystallized, and a minute crystallized region 17 is formed.
次に、600°C程度の温度で非晶質Si膜15の固相
成長アニールを行う。第2図は、この固相成長アニール
におけるSi’14のドーズ量と結晶化との関係を示し
ている。第2図の継軸は、紫外線波長域における反射率
のピークを、単結晶Siを100とした割合で示してい
る。Next, solid phase growth annealing of the amorphous Si film 15 is performed at a temperature of about 600°C. FIG. 2 shows the relationship between the Si'14 dose and crystallization in this solid phase growth annealing. The joint axis in FIG. 2 shows the peak of the reflectance in the ultraviolet wavelength range as a ratio of 100 to that of single crystal Si.
この第2図から明らかな様に、且つ既述の様に、Si”
14のドーズ量が多ければ、ランダムな核発生までの時
間が長く、その結果、結晶粒径が太きくて結晶化の割合
も高い。As is clear from this FIG. 2 and as stated above, Si”
If the dose of No. 14 is large, the time until random nucleation is long, and as a result, the crystal grain size is large and the rate of crystallization is high.
本実施例では、上述の様にSi”14のドーズ量を5
X 1015cin−”以上にしたので、ランダムな核
発生までの時間が極めて長い。しかし、非晶質Si膜1
5中には結晶化領域17を予め形成しである。In this example, the dose of Si"14 was set to 5 as described above.
X 1015 cin-" or more, the time until random nucleation is extremely long. However, the amorphous Si film 1
5, a crystallized region 17 is formed in advance.
従って、600°C程度の温度の固相成長アニルを行え
ば、結晶化領域17を種として結晶粒が成長し、しかも
隣の結晶化領域17を種として成長してきた結晶粒と接
するまでの時間には、結晶化領+ti17同士の間で核
が発生しない様にすることが可能である。Therefore, if solid-phase growth annealing is performed at a temperature of about 600°C, crystal grains will grow using the crystallized region 17 as a seed, and it will take time until they come into contact with the crystal grains that have grown using the adjacent crystallized region 17 as a seed. In this case, it is possible to prevent the generation of nuclei between the crystallized regions +ti17.
この結果、第1C図に示す様に、結晶化領域17のみに
対応して結晶粒18が形成され、これらの結晶粒18は
結晶粒径が大きく結晶粒径のばらつきも少ない。As a result, as shown in FIG. 1C, crystal grains 18 are formed corresponding only to the crystallized region 17, and these crystal grains 18 have large crystal grain sizes and little variation in crystal grain size.
従って、この様な結晶粒18から成る多結晶5iH19
を活性層として用いて薄膜トランジスタを形成すれば、
この薄膜トランジスタは高性能で且つ特性のばらつきが
少ない。Therefore, polycrystalline 5iH19 consisting of such crystal grains 18
If a thin film transistor is formed using as an active layer,
This thin film transistor has high performance and less variation in characteristics.
なお、本実施例ではSi”14のドーズ量を5×10”
ell−”以上としたが、lX101S〜1×10”C
11−”程度であれば同様な効果を得ることが可能であ
る。In addition, in this example, the dose amount of Si"14 was set to 5×10"
ell-" or more, but lX101S~1x10"C
Similar effects can be obtained if the distance is about 11-''.
また、本実施例ではSi”14をイオン注入することに
よって多結晶5ill13を非晶質5ill15にした
が、非晶質Si膜15と同程度の非晶質化の非晶質Si
膜をSing膜12上に直接に形成することができれば
、Si”14のイオン注入は必ずしも必要ではない。Further, in this embodiment, the polycrystalline 5ill13 was made amorphous 5ill15 by ion implantation of Si''14, but the amorphous Si film 15 is
If the film can be formed directly on the Sing film 12, ion implantation of Si'' 14 is not necessarily necessary.
本発明による多結晶半導体薄膜の形成方法では、結晶粒
径の制御が可能であるので、結晶粒径が大きく結晶粒径
のばらつきも少ない多結晶半導体薄膜を形成することが
できる。In the method for forming a polycrystalline semiconductor thin film according to the present invention, since the crystal grain size can be controlled, a polycrystalline semiconductor thin film with a large crystal grain size and little variation in crystal grain size can be formed.
第1図は本発明の一実施例を順次に示す側断面図、第2
図は多結晶Si膜に対するSi”のドーズ量とこの多結
晶Si膜の結晶化との関係を示すグラフである。
なお図面に用いられた符号において、
15 − ・−−−m−−・−−−−−一−−−−−−
・−非晶質5il117−・−・−−−一−−−−−−
・−・・−結晶化領域19−−−−−−−−−−−−−
−−・・−・・−多結晶Si膜である。Fig. 1 is a side sectional view sequentially showing one embodiment of the present invention;
The figure is a graph showing the relationship between the dose of Si" for a polycrystalline Si film and the crystallization of this polycrystalline Si film. In the symbols used in the drawing, 15 - ・---m---・- −−−−1−−−−−−
・-Amorphous 5il117−・−・−−−1−−−−−
・−・・−Crystallization region 19−−−−−−−−−−−
---...--Polycrystalline Si film.
Claims (1)
成長を行わせる多結晶半導体薄膜の形成方法。[Scope of Claims] A method for forming a polycrystalline semiconductor thin film, comprising forming a crystallized region in a desired portion of an amorphous semiconductor thin film, and growing crystals in the amorphous semiconductor thin film using the crystallized region as a seed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8204990A JPH03280528A (en) | 1990-03-29 | 1990-03-29 | Formation of polycrystalline semiconductor thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8204990A JPH03280528A (en) | 1990-03-29 | 1990-03-29 | Formation of polycrystalline semiconductor thin film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03280528A true JPH03280528A (en) | 1991-12-11 |
Family
ID=13763657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8204990A Pending JPH03280528A (en) | 1990-03-29 | 1990-03-29 | Formation of polycrystalline semiconductor thin film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03280528A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5803965A (en) * | 1995-10-17 | 1998-09-08 | Lg Electronics, Inc. | Method and system for manufacturing semiconductor device |
-
1990
- 1990-03-29 JP JP8204990A patent/JPH03280528A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5803965A (en) * | 1995-10-17 | 1998-09-08 | Lg Electronics, Inc. | Method and system for manufacturing semiconductor device |
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