JPH03276631A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH03276631A
JPH03276631A JP7607390A JP7607390A JPH03276631A JP H03276631 A JPH03276631 A JP H03276631A JP 7607390 A JP7607390 A JP 7607390A JP 7607390 A JP7607390 A JP 7607390A JP H03276631 A JPH03276631 A JP H03276631A
Authority
JP
Japan
Prior art keywords
metal wiring
deposited
metal
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7607390A
Other languages
Japanese (ja)
Inventor
Soichi Nishida
西田 宗一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP7607390A priority Critical patent/JPH03276631A/en
Publication of JPH03276631A publication Critical patent/JPH03276631A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control the remarkable protrusion of an overlapping part of a first metal wiring and a second metal wiring, and improve the step coverage of a protective film of this part, by a method wherein, at an intersecting part of the first and the second metal wirings, the film thickness of at least one of the metal wirings is thinly formed. CONSTITUTION:After a first metal wiring 13 is formed, a photoresist mask 1 is patterned by using a negative-positive inversion mask for patterning a second metal wiring, and a part of the first metal wiring 13 is etched halfway. After the photoresist mask 1 is exfoliated, an interlayer insulating film 2 is deposited by CVD method, and through holes 3 are formed at necessary parts. Second metal wiring material is deposited by sputtering method, and a second metal wiring 4 is patterned. Finally, a protective film 5 is deposited by CVD method.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、微細な2層金属配線を有する半導体装置およ
びその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having fine two-layer metal wiring and a method for manufacturing the same.

従来の技術 半導体装置は高集積化へと限りな(進化しているが、最
近ではデバイスの高速化、高機能化が強く要望されてき
ている。このため2層金属配線形成技術は非常に重要な
ものとなってきた。−船釣な2層金属配線の形成方法に
は大きく分けて絶縁膜のエッチバックによる方法と5O
G(スピンオンガラス)を用いた方法の2種類がある。
Conventional technology Semiconductor devices are constantly evolving toward higher integration, but recently there has been a strong demand for higher speed and higher functionality of devices.For this reason, two-layer metal wiring formation technology is extremely important. - There are two main methods for forming two-layer metal interconnections: etch-back of the insulating film, and 5O
There are two methods using G (spin-on glass).

以下、その構成について第3図および第4図を参照しな
がら説明する。第3図(a)〜(e)はエッチバック法
による2層金属配線形成における断面工程図を示したも
のである。同図(a)に示すように、半導体基板11上
の絶縁膜12上に第1金属配線材料をスパッタリング法
で蒸着し、第1金属配線13のパターニングを行い、同
図(b)に示すようにCVD法で絶縁膜14を堆積し、
フォトレジスト膜15を回転塗布する。次に同図(C)
に示すようにRIE(リアクティブイオンエツチング)
法を用いたエッチバックを行い、さらに同図(d)に示
すようにCVD法で絶縁膜16を堆積し、スルーホール
17を形成した後、第2金属配線材料をスパッタリング
法で蒸着し、第2金属配線18のパターニングを行う。
The configuration will be explained below with reference to FIGS. 3 and 4. FIGS. 3(a) to 3(e) show cross-sectional process diagrams in forming two-layer metal wiring by the etch-back method. As shown in Figure (a), a first metal wiring material is deposited on the insulating film 12 on the semiconductor substrate 11 by sputtering, and the first metal wiring 13 is patterned, as shown in Figure (b). An insulating film 14 is deposited by CVD method on
A photoresist film 15 is spin-coated. Next, the same figure (C)
RIE (reactive ion etching) as shown in
Then, as shown in FIG. 3(d), an insulating film 16 is deposited using a CVD method to form a through hole 17, and then a second metal wiring material is deposited using a sputtering method. 2. Patterning of the metal wiring 18 is performed.

最後に同図(e)に示すようにCVD法で保護膜19を
堆積する。次に第4図(a)〜(d)はSOG法による
2層金属配線形成における断面工程図を示したものであ
る。同図(a)は第3図(a)と全く同じであるので同
一番号を付し、説明を省略する。次に同図(b)に示す
ようにCVD法で絶縁膜21を堆積し、SOG膜22を
回転塗布する。SOG膜を乾燥、ガラス化した後、同図
(C)に示すようにCVD法で絶縁膜23を堆積し、ス
ルーホール24を形成した後、第2金属配線材料をスパ
ッタリング法で蒸着し、第2金属配線25のパターニン
グを行う。最後に同図(d)に示すようにCVD法で保
護膜26を堆積する。
Finally, a protective film 19 is deposited by the CVD method, as shown in FIG. 4(e). Next, FIGS. 4(a) to 4(d) show cross-sectional process diagrams in forming two-layer metal wiring by the SOG method. Since FIG. 3(a) is exactly the same as FIG. 3(a), the same reference numerals are given and the explanation will be omitted. Next, as shown in FIG. 4B, an insulating film 21 is deposited by CVD, and an SOG film 22 is spin-coated. After drying and vitrifying the SOG film, an insulating film 23 is deposited by CVD as shown in FIG. 2. Patterning of the metal wiring 25 is performed. Finally, a protective film 26 is deposited by CVD as shown in FIG. 2D.

発明が解決しようとする課題 このような従来の半導体装置では、エッチバック法の第
1金属配線と第2金属配線とがオーバーラツプする箇所
の平坦化は十分に行われるが、オーバーラツプしない箇
所にも第2金属配隷から半導体基板までの間に厚い層間
絶縁膜が形成され第2金属配線から半導体基板へのコン
タクトホールの形成が困難となっており、また5OG(
スピンオンガラス)法の第1金属配線と第2金属配線と
のオーバーラツプ部分がかさばむため上方向に大きく膨
らみ、上層膜である保護膜のステップカバレージを悪化
させ、信頼性面での問題が発生しやすい。
Problems to be Solved by the Invention In such conventional semiconductor devices, the areas where the first metal wiring and the second metal wiring overlap are sufficiently planarized by the etch-back method, but the areas where the first metal wiring and the second metal wiring overlap are also flattened. A thick interlayer insulating film is formed between the second metal wiring and the semiconductor substrate, making it difficult to form a contact hole from the second metal wiring to the semiconductor substrate.
The overlapping part of the first metal wiring and the second metal wiring in the spin-on glass (spin-on glass) method becomes bulky and bulges upwards, which worsens the step coverage of the upper protective film and causes reliability problems. It's easy to do.

本発明は上記課題を解決するもので、信頼性の高い小型
の半導体装置およびその製造方法を提供することを目的
としている。
The present invention solves the above problems, and aims to provide a highly reliable small-sized semiconductor device and a method for manufacturing the same.

課題を解決するための手段 本発明は上記目的を達成するために、半導体基板の一主
面上に、少なくともスルーホールを有する層間絶縁膜を
はさんで形成された第1金属配線および第2金属配線を
有する半導体装置において、第1金属配線と第2金属配
線が交差する箇所の少なくとも一つの前述の金属配線の
膜厚が薄くなっている構成による。
Means for Solving the Problems In order to achieve the above object, the present invention provides a first metal wiring and a second metal wiring formed on one main surface of a semiconductor substrate with an interlayer insulating film having at least a through hole in between. In a semiconductor device having wiring, at least one of the aforementioned metal wirings has a thinner film thickness at a location where the first metal wiring and the second metal wiring intersect.

作用 本発明は上記した構成により、第1金属配線と第2金属
配線が交差する箇所で第2金属配線の極端な盛り上がり
がなくなり、比較的平坦な保護膜形成が可能となる。ま
た、従来例のエッチバック法での欠点であった第2金属
配線から半導体基板との間の厚い眉間絶縁膜の形成が不
用となり、第2金属配線から基板へのコンタクトホール
の形成が可能となる。
Effect of the Invention With the above-described configuration, the present invention eliminates extreme swells of the second metal wiring at the intersections of the first metal wiring and the second metal wiring, making it possible to form a relatively flat protective film. In addition, the formation of a thick glabellar insulating film between the second metal wiring and the semiconductor substrate, which was a drawback of the conventional etch-back method, is no longer necessary, and it is now possible to form contact holes from the second metal wiring to the substrate. Become.

実施例 以下、本発明の一実施例について第1図および第2図を
用いて従来例の第3図および第4図と同じ部分には同一
番号を付し、説明を省略し、本発明の特徴となる部分に
ついて説明を行う。すなわち第1図および第2図(a)
における第1金属配置13を形成した後、第2図(b)
に示すように第2金属配線パターニング用マスクのネガ
−ポジ反転マスクを用い、フォトレジスト膜1のパター
ニングを行い、同図(C)に示すように第1金属配線1
3の一部を途中までエツチングする。そしてフォトレジ
スト膜1を剥離した後、同図(d)に示すように眉間絶
縁膜2をCVD法で0.2μm蒸着し、必要箇所にスル
ーホール3を形成する。さらに同図(e)に示すように
第2金属配線材料をスパッタリング法で0.8μm蒸着
し、第2金属配線4のパターニングを行う。最後に同図
げ)に示すように保2N@5をCVD法で堆積する。な
お、本実施例では第1金属配線の膜厚を薄くする場合に
ついて述べたが、第2金属配線の膜厚を薄くすることも
可能であり、また両者とも薄くすることもできる。
EXAMPLE Hereinafter, an embodiment of the present invention will be described using FIGS. 1 and 2, and the same parts as in FIGS. 3 and 4 of the conventional example will be given the same numbers, explanations will be omitted, and the present invention will be explained. We will explain the distinctive parts. That is, FIG. 1 and FIG. 2(a)
After forming the first metal arrangement 13 in FIG. 2(b)
As shown in Figure (C), the photoresist film 1 is patterned using a negative-positive reversal mask of the second metal wiring patterning mask, and as shown in Figure (C), the first metal wiring 1
Etch part of 3 halfway. After peeling off the photoresist film 1, a glabellar insulating film 2 with a thickness of 0.2 μm is deposited using the CVD method, and through holes 3 are formed at necessary locations, as shown in FIG. Furthermore, as shown in FIG. 4E, a second metal wiring material is deposited to a thickness of 0.8 μm by sputtering, and the second metal wiring 4 is patterned. Finally, as shown in Figure 1), 2N@5 is deposited by CVD. In this embodiment, a case has been described in which the thickness of the first metal wiring is made thin, but it is also possible to make the thickness of the second metal wiring thin, or both can be made thin.

発明の効果 以上の実施例から明らかなように本発明によれば、第1
金属配線と第2金属配線とのオーバーラツプ部分の顕著
な盛り上がりが抑制され、この部分の保護膜ステップカ
バレージが向上する。また従来の2層金属配線形成技術
で困難とされていた第2金属配線から半導体基板へのコ
ンタクトホール形成が容易にでき、チップレイアウトの
自由度か向上し、小型で信頼性の高い半導体装置および
その製造方法を提供できる。
Effects of the Invention As is clear from the above embodiments, according to the present invention, the first
A significant bulge in the overlapping portion of the metal wiring and the second metal wiring is suppressed, and the protective film step coverage in this portion is improved. In addition, it is now possible to easily form a contact hole from the second metal wiring to the semiconductor substrate, which was difficult with conventional two-layer metal wiring formation technology, and the degree of freedom in chip layout has been improved, resulting in compact and highly reliable semiconductor devices and A manufacturing method thereof can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の半導体装置の外観斜視図、
第2図(a’)〜(f)は同半導体装置の製造工程を説
明するための断面工程図、第3図(a)〜(e)および
第4図(a)〜(d)は従来のエッチバック法およびS
OG法による半導体装置去≠チ平の製造方法を説明する
ための断面工程図である。 2・・・・・・層間絶縁膜、3・・・・・・スルーホー
ル、4・・・・・・第2金属配線、5・・・・・・保護
膜、11・・・・・・半導体基板、12・・・・・・絶
縁膜、13・・・・・・第1金属配線。
FIG. 1 is an external perspective view of a semiconductor device according to an embodiment of the present invention;
Figures 2(a') to (f) are cross-sectional process diagrams for explaining the manufacturing process of the same semiconductor device, and Figures 3(a) to (e) and 4(a) to (d) are conventional Etchback method and S
FIG. 3 is a cross-sectional process diagram for explaining a method for manufacturing a semiconductor device by the OG method. 2...Interlayer insulating film, 3...Through hole, 4...Second metal wiring, 5...Protective film, 11... Semiconductor substrate, 12... Insulating film, 13... First metal wiring.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の一主面上に、層間絶縁膜をはさんで
交差させて形成された第1金属配線と第2金属配線を有
し、前記第1、第2金属配線の交差部分において少なく
ともいずれか一方の金属配線の膜厚が薄く形成されてい
る半導体装置。
(1) A first metal wiring and a second metal wiring are formed on one main surface of a semiconductor substrate so as to intersect with each other with an interlayer insulating film in between, and at an intersection of the first and second metal wiring, A semiconductor device in which at least one of the metal interconnections has a thin film thickness.
(2)半導体基板の一主面上に第1金属配線を形成する
工程と、前記第1金属配線の第2金属配線と交差すべき
部分または前記第1金属配線の層間絶縁膜のスルーホー
ルを介して第2金属配線と接続されるべき部分をエッチ
ング除去して膜厚を薄く形成する工程と、前記第2金属
配線を形成する工程と、保護膜を形成する工程とを有す
る半導体装置の製造方法。
(2) forming a first metal wiring on one principal surface of the semiconductor substrate; forming a portion of the first metal wiring that intersects with a second metal wiring or a through hole in an interlayer insulating film of the first metal wiring; manufacturing a semiconductor device, comprising: etching away a portion to be connected to a second metal wiring through the film to reduce the film thickness; forming the second metal wiring; and forming a protective film. Method.
JP7607390A 1990-03-26 1990-03-26 Semiconductor device and its manufacture Pending JPH03276631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7607390A JPH03276631A (en) 1990-03-26 1990-03-26 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7607390A JPH03276631A (en) 1990-03-26 1990-03-26 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH03276631A true JPH03276631A (en) 1991-12-06

Family

ID=13594627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7607390A Pending JPH03276631A (en) 1990-03-26 1990-03-26 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH03276631A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8231644B2 (en) 2009-08-05 2012-07-31 Olympus Medical Systems Corp. Torque wrench and ultrasonic surgical device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8231644B2 (en) 2009-08-05 2012-07-31 Olympus Medical Systems Corp. Torque wrench and ultrasonic surgical device

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