JPH03270225A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03270225A
JPH03270225A JP7089690A JP7089690A JPH03270225A JP H03270225 A JPH03270225 A JP H03270225A JP 7089690 A JP7089690 A JP 7089690A JP 7089690 A JP7089690 A JP 7089690A JP H03270225 A JPH03270225 A JP H03270225A
Authority
JP
Japan
Prior art keywords
openings
layer
laminate
opening
resist layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7089690A
Other languages
Japanese (ja)
Inventor
Tomiyasu Saito
富康 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7089690A priority Critical patent/JPH03270225A/en
Publication of JPH03270225A publication Critical patent/JPH03270225A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid the positional slips between mutual openings by a method wherein shallow openings are formed in all regions to form the openings using the first laminated body, next the second laminated body is formed so as to repeat the excavating process of the regions to form the deep openings. CONSTITUTION:Shallow openings are formed in all regions to form the openings using the first laminated body 10 comprising the first flattened layer 8 formed on the first layers 7 and the first resist layer 9. Next, the second laminated body 16 comprising the second flattened layer 14 and the second resist layer 15 is formed so as to repeat the excavating process of the shallow openings in the regions to form the deep openings one by one using the second laminated body 16 and the first laminated body 10. Through these procedures, the positional slips between mutual openings can be avoided.

Description

【発明の詳細な説明】 (概要〕 深さの異なる複数の開口を開口相互間に位置ずれが生じ
ないように形成するエツチング方法に関し、 膜厚が一様でない層の膜厚の異なる領域にそれぞれ深さ
の異なる開口を形成するにあたり、深さの異なる開口相
互間に位置ずれが生しないようにするエツチング方法を
提供することを目的とし、第1の層上に第1の平坦化層
と第1のレジスト層との第1の積層体を形成し、開口を
形成するすべてのti域に、前記の第1の積層体を使用
して浅い開口を形成し、次いで、第2の平坦化層と第2
のレジスト層との第2の積層体を形成し、この第2の積
層体と前記の第1の積層体とを使用して逐次深い開口を
形成する領域の前記の浅い開口を堀進して逐次深い開口
を形成する工程を繰り返すことによって深さの異なる開
口を形成するように構成する。
[Detailed Description of the Invention] (Summary) Regarding an etching method for forming a plurality of apertures with different depths without positional deviation between the apertures, each of the etching method forms a plurality of apertures with different depths in regions of different film thicknesses of a layer with an uneven film thickness. The purpose of the present invention is to provide an etching method that prevents misalignment between openings with different depths when forming openings with different depths. Form a first laminate with a resist layer of 1, form shallow openings in all Ti areas where openings are to be formed using the first laminate, and then apply a second planarization layer. and second
forming a second laminate with a resist layer, and using the second laminate and the first laminate to sequentially excavate the shallow opening in the region where the deep opening is to be formed; The configuration is such that openings with different depths are formed by repeating the process of sequentially forming deep openings.

〔産業上の利用分野〕[Industrial application field]

本発明は、深さの異なる複数の開口を開口相互間に位置
ずれが生しないように形成するエツチング方法に関する
The present invention relates to an etching method for forming a plurality of openings having different depths without causing positional deviation between the openings.

(従来の技術〕 半導体装置の高集積化、微細化にともなって、その製造
方法は複雑化してきており、その複雑な製造過程におい
て、膜厚が一様でない層の膜厚の異なる領域をそれぞれ
エツチングして、それぞれに深さの異なる開口を形成す
ることが必要になる場合がある。
(Prior art) As semiconductor devices become more highly integrated and miniaturized, their manufacturing methods have become more complex. It may be necessary to etch the openings to different depths.

例えば、第8図に示すように、半導体層1上に形成され
た絶縁膜2上に第1の導1!膜3と第2の導電膜4と第
3の導電WA5とが相互に層間絶縁膜6を介して積層さ
れている第1の層7があり、第1の導電WXa上と第2
の導1]1]4上と第3の導電WIS上とに形成されて
いる厚さの異なる眉間絶縁!!16に、それぞれ深さの
異なる開口を形成する場合の従来技術に係る工程につい
て以下に説明する。
For example, as shown in FIG. 8, a first conductor 1! is formed on an insulating film 2 formed on a semiconductor layer 1! There is a first layer 7 in which a film 3, a second conductive film 4, and a third conductive WA5 are laminated with each other with an interlayer insulating film 6 interposed therebetween.
Glabellar insulation with different thicknesses formed on the conductor 1] 1] 4 and the third conductor WIS! ! The steps according to the prior art for forming openings with different depths in the holes 16 will be described below.

第9図に示すように、第1のレジスト層9を形成し、こ
れをパターニングして第1の導1#3、第2の導電膜4
及び第3の導電膜5の上の開口形成領域に、それぞれ開
口1].12、及び13を形成し、開口1].12、及
び13の形成されたレジスト層9をマスクとして層間絶
縁II6をエツチングし、第3の導電M5に到達する深
さまで堀進する。
As shown in FIG. 9, a first resist layer 9 is formed and patterned to form a first conductive film 1#3 and a second conductive film 4.
and the opening 1] in the opening formation region on the third conductive film 5, respectively. 12 and 13, and the opening 1]. The interlayer insulation II6 is etched using the resist layer 9 with the resist layers 12 and 13 formed thereon as a mask, and the etching is performed to a depth that reaches the third conductive layer M5.

第1のレジスト層9を除去し、第10図に示すように第
2のレジスト層15を形成し、新たなマスクを使用して
フォトリソグラフィー法を使用してパターニングし、開
口1]と開口12との上から第2のレジスト層15を除
去し、この開口の形成された第2のレジスト層15をマ
スクとしてエツチングをなし、第2の導電膜4に到達す
る深さまで開口1]と開口12とを堀進する。
The first resist layer 9 is removed, a second resist layer 15 is formed as shown in FIG. The second resist layer 15 is removed from above, and etching is performed using the second resist layer 15 in which the opening is formed as a mask to form the opening 1 and the opening 12 to a depth that reaches the second conductive film 4. To dig deeper.

以下、同様の工程を繰り返し、第1]rf!Jに示すよ
うに第1の導電II3に到達する開口1]を形成し、第
12図に示すように、レジスト層を除去して第4の導1
]WX1Bを形成し、これをパターニングして第1の導
を膜3と第2の導m1]1!4と第3の導電膜5とに接
続する第4の導を膜18を形成する。
Hereinafter, the same process is repeated, and the first] rf! As shown in FIG. 12, an opening 1 reaching the first conductor II3 is formed, and as shown in FIG.
] WX1B is formed and patterned to form a fourth conductive film 18 that connects the first conductive to the film 3, the second conductive m1]1!4, and the third conductive film 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

深さの異なる複数の開口を形成するには、深さの異なる
開口の種類に相当する数のマスクを使用して、フォトリ
ソグラフィー工程を実行しなければならない、この場合
、マスク相互間の位置合わせが必要になるが、一つのマ
スクの位置合わせ精度が±0.3 nであるとすると、
例えば深さの異なる2種類の開口を形成する場合には、
二つの開口の間に最大0.6nの位置ずれが生ずる可能
性がある。
To form multiple apertures of different depths, a photolithographic process must be performed using a number of masks corresponding to the types of apertures of different depths, in which case the alignment between the masks is required, but if the alignment accuracy of one mask is ±0.3 n,
For example, when forming two types of openings with different depths,
A maximum displacement of 0.6n may occur between the two apertures.

本発明の目的は、この欠点を解消することにあり、膜厚
が一様でない層の膜厚の異なる領域にそれぞれ深さの異
なる開口を形成するにあたり、深さの異なる開口相互間
に位置ずれが生じないようにするエツチング方法を提供
することにある。
An object of the present invention is to eliminate this drawback, and when forming apertures with different depths in regions of different film thicknesses of a layer with an uneven film thickness, positional deviations occur between the apertures with different depths. It is an object of the present invention to provide an etching method that prevents the occurrence of.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的は、第1の層(7)上に第1の平坦化層(8
)と第1のレジスト層(9)との第1の積層体(10)
を形成し、開口を形成するすべての領域に、前記の第1
の積層体(10)を使用して浅い開口を形成し、次いで
、第2の平坦化層(14)と第2のレジスト層(15)
との第2の積層体(16)を形成し、この第2の積層体
(16)と前記の第1の積層体(10)とを使用して逐
次深い開口を形成する領域の前記の浅い開口を堀進して
逐次深い開口を形成する工程を繰り返すことをeraと
する深さの異なる開口を形成する工程を含む半導体装置
の製造方法によって連成される。なお、前記の第1のレ
ジスト層(9)及び第2のレジスト層(15)は多層レ
ジスト層としてもよい、また、前記の第1の層(7)は
、パターニングされた導電膜(3)(4)(5)と層間
絶縁膜!I(6)との積層体であってもよい。
The above purpose is to apply a first planarization layer (8) on the first layer (7).
) and a first resist layer (9).
and apply the above-mentioned first
A shallow opening is formed using the laminate (10), and then a second planarization layer (14) and a second resist layer (15) are formed.
forming a second laminate (16) with the first laminate (16), and using the second laminate (16) and the first laminate (10) to sequentially form a deep opening; This is coupled by a semiconductor device manufacturing method including a process of forming openings with different depths, the era of which is repeating the process of digging an opening and sequentially forming deep openings. Note that the first resist layer (9) and the second resist layer (15) may be multilayer resist layers, and the first layer (7) may be a patterned conductive film (3). (4) (5) and interlayer insulation film! It may also be a laminate with I(6).

〔作用〕[Effect]

本発明に係る深さの異なる開口の形成方法においては、
第1の層7上に第1の平坦化層8と第1のレジスト層9
との第1の積層体10を形成し、深さの異なるすべての
開口形ti領領域対応する領域の第1の積層体10に開
口を形成し、この第1の積層体10をマスクとして、先
ず一番浅い開口の深さまで第1の層7を堀進し、次いで
、さらに深い開口を形成する領域を除< 61域に第2
の平坦化層14と第2のレジスト層16との第2の積層
体16を形成し、第2の積層体16と第1の積層体10
とをマスクとして、次に°深い開口の深さまで前記の浅
い開口を堀進する工程を逐次繰り返すことによって、深
さの異なるすべての開口を形成するので、深さの異なる
開口相互間の位置は第1の積層体lOに一番最初に形成
された開口の位置によって決定されることになり、開口
相互間に位Iずれが生ずることがなくなる。
In the method for forming openings with different depths according to the present invention,
A first planarization layer 8 and a first resist layer 9 on the first layer 7
A first stacked body 10 is formed with a first stacked body 10, and openings are formed in the first stacked body 10 in areas corresponding to all the open-shaped Ti regions having different depths, and this first stacked body 10 is used as a mask. First, the first layer 7 is excavated to the depth of the shallowest opening, and then the second layer 7 is excavated in the area where a deeper opening is to be formed.
A second laminate 16 is formed of the planarization layer 14 and the second resist layer 16, and the second laminate 16 and the first laminate 10 are formed.
As a mask, all the openings with different depths are formed by sequentially repeating the process of digging the shallow openings to the depth of the deep opening, so the positions between the openings with different depths are This is determined by the position of the first opening formed in the first stacked body IO, and no positional deviation occurs between the openings.

〔実施例〕〔Example〕

以下、図面を参照しつ\、本発明の一実施例に係る深さ
の異なる複数の開口を形成する方法について説明する。
Hereinafter, a method for forming a plurality of openings having different depths according to an embodiment of the present invention will be described with reference to the drawings.

第2図参照 半導体層1上に形成された絶縁膜2上に、第1の導電1
]13と第2の導電膜4と第3のat膜5とが二酸化シ
リコンよりなる眉間絶縁膜6を介して積層されている第
1の層7があり、この第1の導電1]3と第2の導電膜
4と第3の導電膜5との上に形成されている厚さの異な
る層間絶縁膜6に、それぞれ深さの異なる開口を形成す
る場合を例として説明する。
Referring to FIG. 2, a first conductive layer 1 is formed on an insulating film 2 formed on a semiconductor layer 1.
] 13, a second conductive film 4, and a third AT film 5 are laminated with a glabella insulating film 6 made of silicon dioxide interposed therebetween. A case where openings with different depths are formed in interlayer insulating films 6 of different thicknesses formed on the second conductive film 4 and the third conductive film 5 will be described as an example.

第3図参照 ノボラック系樹脂、例えば長瀬産業製のNPR−820
よりなる第1の平坦化層8とシリコンを含む第1のレジ
スト層9との第1の積層体lOを形成し、フォトリソグ
ラフィー法を使用して第1のレジスト層9をバターニン
グし、第1の導電1]13上に開口1]を形成し、第2
の導電膜4上に開口12を形成し、第3の導電膜5上に
開口13を形成する。
See Figure 3 Novolac resin, such as NPR-820 manufactured by Nagase Sangyo.
A first stacked body 10 of a first flattening layer 8 made of silicon and a first resist layer 9 containing silicon is formed, and the first resist layer 9 is patterned using a photolithography method. An opening 1] is formed on the conductor 1] of the second conductor 1.
An opening 12 is formed on the third conductive film 4 , and an opening 13 is formed on the third conductive film 5 .

第4図参照 バターニングされた第1のレジスト層9をマスクとして
、酸素プラズマエツチングをなして第1の平坦化層8を
エツチングし、引き続き四フフ化炭素等を使用して層間
絶縁膜6をプラズマエツチングし、開口1].12及び
13をそれぞれ第3の導電膜5に到達する深さまで堀進
する。
Refer to FIG. 4. Using the patterned first resist layer 9 as a mask, the first flattening layer 8 is etched by oxygen plasma etching, and then the interlayer insulating film 6 is etched using carbon tetrafluoride or the like. Plasma etching and opening 1]. 12 and 13 are excavated to a depth that reaches the third conductive film 5, respectively.

第1図参照 第2の平坦化層14と第2のレジスト層15との第2の
積層体16を形成し、フォトリソグラフィー法を使用し
てパターニングし、第1の導電1]3上に形成されてい
る開口1]と第2の導電膜上に形成されている開口12
とをカバーする領域上から除去して開口17を形成する
。この開口17と第1の導電膜上に開口1]及び第2の
導電膜上の開口12との位I合わせ精度は緩くてよい。
Refer to FIG. 1 A second laminate 16 of a second flattening layer 14 and a second resist layer 15 is formed, patterned using a photolithography method, and formed on the first conductive layer 1]3. opening 1 formed on the second conductive film and opening 12 formed on the second conductive film.
The opening 17 is formed by removing the area covering the area. The alignment accuracy between this opening 17 and the opening 1 on the first conductive film and the opening 12 on the second conductive film may be loose.

第5図参照 酸素プラズマエツチングをなして開口17に露出する第
2の平坦化層14をエツチング除去し、引き続き、第1
の積層体lOをマスクとして四フッ化炭素を使用して層
間絶縁膜6をプラズマエツチングし、第2の導電膜に到
達する深さまで開口1]と開ロエ2とを堀進する。
Referring to FIG. 5, the second planarization layer 14 exposed in the opening 17 is removed by oxygen plasma etching, and then the first planarization layer 14 is etched away.
The interlayer insulating film 6 is plasma etched using carbon tetrafluoride using the laminate IO as a mask, and the opening 1 and the opening 2 are dug to a depth that reaches the second conductive film.

第6図参照 以下、同様の工程を繰り返して、開口1]を第1の導電
膜3に到達する深さまで堀進する。
Referring to FIG. 6, the same steps are repeated to dig the opening 1 to a depth that reaches the first conductive film 3.

第7図参照 すべての平坦化層とレジスト層とを酸素プラズマエツチ
ングをなして除去し、第4の導tl1]8を形成し、こ
れをパターニングして第1の導1]3と第2の導電1]
E4と第3の導9M5とに接続する第4の導電1]i1
8を形成する。
Refer to FIG. 7. All planarization layers and resist layers are removed by oxygen plasma etching to form a fourth conductor tl1]8, which is patterned to form a first conductor 1]3 and a second conductor. Conductivity 1]
Fourth conductor 1]i1 connected to E4 and third conductor 9M5
form 8.

なお、シリコンを含む第1のレジスト層9及び第2のレ
ジスト層15に代えて、シリコン系樹脂、例えば東京応
化製OCDよりなる中間層とノボラック系樹脂、例えば
長瀬産業製N P R−2505Σよりなるレジスト層
との積層体を使用してもよい。
Note that instead of the first resist layer 9 and the second resist layer 15 containing silicon, an intermediate layer made of a silicone resin such as OCD manufactured by Tokyo Ohka Co., Ltd. and a novolac resin such as NPR-2505Σ manufactured by Nagase Sangyo Co., Ltd. are used. A laminate with a resist layer may also be used.

また、上記の工程をさらに繰り返すことによって、3種
類以上の深さの異なる開口を形成しうろことは云うまで
もない。
It goes without saying that by further repeating the above steps, three or more types of openings with different depths can be formed.

〔発明の効果〕〔Effect of the invention〕

以上説明せるとおり、本発明に係る半導体装置の製造方
法においては、第1の層上に第1の平坦化層と第1のレ
ジスト層との第1の積層体を形成し、′W41の積層体
をマスクとして使用して深さの異なる開口を形成するす
べての領域に浅い開口を形成し、次に、この浅い開口を
堀進して、さらに深い開口を形成する領域を除く領域に
第2の平坦化層と第2のレジスト層との第2の積層体を
形成し、先にバターニングされている第1の積層体と第
2の積層体とをマスクとして、次に深い開口の深さまで
前記の浅い開口を堀進する工程を逐次繰り返すことによ
って、深さの異なるすべての開口を形成するので、深さ
の異なる開口相互間の位置は、深さの異なる開口を形成
するすべての領域に最初に形成された浅い開口の位置に
よって決定されるので、深さの異なる開口相互間の位置
ずれは生しない。
As explained above, in the method for manufacturing a semiconductor device according to the present invention, a first laminate of a first planarization layer and a first resist layer is formed on a first layer, and a laminate of ``W41'' is formed. Form shallow openings in all areas using the body as a mask to form openings of different depths, and then drill this shallow opening to form a second opening in any area except the area where you want to form an even deeper opening. A second laminate of a flattening layer and a second resist layer is formed, and using the previously patterned first laminate and second laminate as a mask, the depth of the next deep opening is determined. All the openings with different depths are formed by sequentially repeating the step of excavating the shallow openings described above, so the positions between the openings with different depths are the same as in all the areas where openings with different depths are formed. Since the depth is determined by the position of the shallow aperture initially formed in the depth, no misalignment occurs between apertures of different depths.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第7図は、本発明の一実施例に係る深さの異な
る開口を形成する方法を説明する工程図である。 第8図〜第12図は、従来技術に係る深さの異なる開口
を形成する工程図である。 1 ・ ・ ・ 2 ・ ・ ・ 3 ・ ・ ・ 4 ・ ・ ・ 5 ・ ・ ・ 6 ・ ・ ・ 7 ・ ・ ・ 8 ・ ・ ・ 9 ・ ・ ・ 10・ ・ ・ 1].12゜ 14・ ・ ・ 15・ ・ ・ 半導体層、 絶縁膜、 第1のH/A!膜、 第2の導電膜、 第3の導電膜、 眉間絶縁膜、 第1の層、 第1の平坦化層、 第1のレジスト層、 第1の積層体、 13・・・開口、 第2の平坦化層、 第2のレジスト層、 16・・・第2の積層体、 17・・・開口、 18・・・第4の導電膜。
1 to 7 are process diagrams illustrating a method of forming openings with different depths according to an embodiment of the present invention. 8 to 12 are process diagrams for forming openings with different depths according to the prior art. 1 ・ ・ ・ 2 ・ ・ ・ 3 ・ ・ 4 ・ ・ 5 ・ ・ 6 ・ ・ 7 ・ ・ ・ 8 ・ ・ ・ 9 ・ ・ ・ 10 ・ ・ 1]. 12゜14・ ・ ・ 15・ ・ ・ Semiconductor layer, insulating film, first H/A! film, second conductive film, third conductive film, glabellar insulating film, first layer, first planarization layer, first resist layer, first laminate, 13... opening, second planarization layer, second resist layer, 16... second stacked body, 17... opening, 18... fourth conductive film.

Claims (1)

【特許請求の範囲】 [1]第1の層(7)上に第1の平坦化層(8)と第1
のレジスト層(9)との第1の積層体(10)を形成し
、 開口を形成するすべての領域に、前記第1の積層体(1
0)を使用して浅い開口を形成し、第2の平坦化層(1
4)と第2のレジスト層(15)との第2の積層体(1
6)を形成し、該第2の積層体(16)と前記第1の積
層体(10)とを使用して逐次深い開口を形成する領域
の前記浅い開口を堀進して逐次深い開口を形成する工程
を繰り返すことを特徴とする深さの異なる開口を形成す
る工程を含む ことを特徴とする半導体装置の製造方法。 [2]前記第1のレジスト層(9)及び第2のレジスト
層(15)は多層レジスト層とすることを特徴とする請
求項1記載の半導体装置の製造方法。 [3]前記第1の層(7)は、パターニングされた導電
膜(3)(4)(5)と層間絶縁膜(6)との積層体で
あることを特徴とする請求項1及び2記載の半導体装置
の製造方法。
[Claims] [1] A first flattening layer (8) on the first layer (7) and a first flattening layer (8) on the first layer (7).
forming a first laminate (10) with a resist layer (9) of the first laminate (10);
0) to form a shallow opening and a second planarization layer (1
4) and the second resist layer (15).
6), and by using the second laminate (16) and the first laminate (10) to excavate the shallow openings in the region where deep openings are to be formed successively. 1. A method of manufacturing a semiconductor device, comprising a step of forming openings with different depths, the step of forming openings being repeated. [2] The method of manufacturing a semiconductor device according to claim 1, wherein the first resist layer (9) and the second resist layer (15) are multilayer resist layers. [3] Claims 1 and 2, wherein the first layer (7) is a laminate of patterned conductive films (3), (4), and (5) and an interlayer insulating film (6). A method of manufacturing the semiconductor device described above.
JP7089690A 1990-03-20 1990-03-20 Manufacture of semiconductor device Pending JPH03270225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7089690A JPH03270225A (en) 1990-03-20 1990-03-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7089690A JPH03270225A (en) 1990-03-20 1990-03-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03270225A true JPH03270225A (en) 1991-12-02

Family

ID=13444755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7089690A Pending JPH03270225A (en) 1990-03-20 1990-03-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03270225A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661193A (en) * 1992-04-16 1994-03-04 Micron Technol Inc Method for treatment of semiconductor wafer
JPH07201992A (en) * 1993-12-27 1995-08-04 Nec Corp Manufacture of semiconductor device
JP2012174892A (en) * 2011-02-22 2012-09-10 Toshiba Corp Semiconductor storage device and manufacturing method of the same
JP2012227328A (en) * 2011-04-19 2012-11-15 Sony Corp Semiconductor device, semiconductor device manufacturing method, solid state image pickup device and electronic apparatus
JP2012244180A (en) * 2011-05-24 2012-12-10 Macronix Internatl Co Ltd Multi-layer structure and manufacturing method for the same
JP2013251511A (en) * 2012-06-04 2013-12-12 Macronix Internatl Co Ltd Method for manufacturing 3d stacked multichip module
US9269660B2 (en) 2009-10-14 2016-02-23 Macronix International Co., Ltd. Multilayer connection structure

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661193A (en) * 1992-04-16 1994-03-04 Micron Technol Inc Method for treatment of semiconductor wafer
JPH07201992A (en) * 1993-12-27 1995-08-04 Nec Corp Manufacture of semiconductor device
US9269660B2 (en) 2009-10-14 2016-02-23 Macronix International Co., Ltd. Multilayer connection structure
JP2012174892A (en) * 2011-02-22 2012-09-10 Toshiba Corp Semiconductor storage device and manufacturing method of the same
JP2012227328A (en) * 2011-04-19 2012-11-15 Sony Corp Semiconductor device, semiconductor device manufacturing method, solid state image pickup device and electronic apparatus
US9236412B2 (en) 2011-04-19 2016-01-12 Sony Corporation Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus
US11948833B2 (en) 2011-04-19 2024-04-02 Sony Group Corporation Multilayer light detecting device and electronic apparatus
JP2012244180A (en) * 2011-05-24 2012-12-10 Macronix Internatl Co Ltd Multi-layer structure and manufacturing method for the same
JP2013251511A (en) * 2012-06-04 2013-12-12 Macronix Internatl Co Ltd Method for manufacturing 3d stacked multichip module

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