JPH03269744A - Cache memory control system - Google Patents

Abstract

PURPOSE:To make hardware of an address calculating part to quickly calculate the access address by calculating the access address of a cache memory on the side of a cache memory access control means. CONSTITUTION:An address updating means 14 accesses a cache memory 21 by the start address set to an address register 11 and compares the discrimination number of a read-out record and that of the access object record set to an ID register 12 with each other. If they do not coincide with each other, the value of the address register 11 is updated to the address of the next record by the key length and the data length taken out from the count part of the read-out record, and this operation is repeated till discrimination numbers coincide with each other. Thus, the address calculating part is easily made into hardware to quickly calculate the address because the access address of the cache memory 21 is calculated on the side of a cache memory access control means 10.

Description

[Detailed Description of the Invention] [Summary] Regarding the cache memory control method of a disk cache type disk control device, the purpose of this invention is to make the cache memory control part hard and speed up the cache memory control. In a cache memory control method of a disk control device equipped with a cache memory access control means for controlling a cache memory, an address register for setting an access address of the cache memory, an ID register for setting an identification number of a record to be accessed, and an access source command. means to analyze the access address of the cache memory, set the access address in the address register, and set the identification number of the access record in the ID register, analyze the count part read from the cache memory, and set the identification number of the record and the ID register. until the identification numbers match.
The cache memory access control means is configured to include means for updating the address of the address register based on the data of the count section.

[Industrial application field]

The present invention provides a disk cache type disk control device equipped with a cache memory shared by a plurality of access sources and a cache memory access control means for controlling data transfer to the cache memory. This invention relates to a cache memory control method when accessing cache memory according to commands.

[Conventional technology]

In a disk control device that controls data read/write to an external storage device such as a magnetic disk device according to commands from an access source such as a higher-level CPU, in order to speed up read/write to the external storage device, A disk cache method with internal cache memory is often used.

In this disk cache method, a cache memory with a higher speed and lower capacity than the external storage device is provided in the disk control device, and when reading data, the read data from the external storage device is temporarily stored in the cache memory, and the CPU reads data at an appropriate timing (e.g. , when there is no other processing), the data on this cache memory is read.

Furthermore, when writing, the write data is temporarily stored in the cache memory, and the write data is transferred to the external storage device and written at an appropriate timing.

FIG. 5 is a block diagram showing the basic configuration of a cache memory type disk control device.

In the disk control device 20 of FIG.
A cache memory is a high-speed, low-capacity memory in which data transferred between an access source such as a CPU (not shown) and an external storage device (not shown) such as a magnetic disk device is stored in record format.

A cache memory access control means 22 controls access to the cache memory 21.

231 to 23n are channel adapters, and the corresponding C
Connection control between an access source (not shown) such as a PU and the disk control device 20, analysis of commands from the access source, calculation of addresses for accessing the cache memory 21, and determination of the data length of each data to be read/written. Performs processing such as settings.

Device adapters 24 and 24n control connections with corresponding external storage devices (magnetic disk devices).

25 is a common lotus, which includes cache memory access control means 22, channel adapter 23. 23n and the device adapters 241 to 24n, data and addresses are transferred between them.

FIG. 4 shows the format of data stored in the cache memory 21 in record format, and each record is composed of a count section, a key section, and a data section as shown.

The count part has a fixed length (28 bytes) and contains:
An identification number ID that identifies the record, a key length KL that specifies the length of the key part, and a data length DL that specifies the length of the data part are stored.

The key part stores a physical index for searching the record, and the data part stores the data of the user to be transferred.

Next, FIG. 6 is a detailed explanatory diagram of the internal configuration of the cache memory access control means 22 of FIG. 5.

In FIG. 6, 221 is an address register in which an address for accessing the cache memory 21 is set.

222 is a data byte counter, and the number of bytes of data to be read/written to the cache memory 21 is set.

223 is a command register in which a command transferred from an access source is stored.

224 is a command analysis section, and the command register 22
Processing to analyze the command stored in 3 and identify either read/write, processing to set the start address for accessing the cache memory 21 in the address register 221, and data length of various data to be read/written. Processing to set the byte counter 222 is performed.

225 is a data register, and the cache memory 21
The data to be read/written is temporarily stored.

A data transfer control unit 226 controls the transfer of data read/written to the cache memory 21 and updates the contents of the address register 221 and data byte counter 222 in connection with data transfer.

In this configuration, from an access source such as a CPU (not shown), a start address for accessing the memory, a read/write address, etc.
Commands instructing write distinction, data length to be read/written, etc. are issued to the channel adapter (23). In order to simplify the explanation, it is assumed that the cache memory 21 is hit and read/write is possible.

The channel adapter 23+ analyzes the command from the access source, performs processing to obtain the addresses of the count part, key part, and data part of the record with data to be accessed, and the data length of each part, and sequentially accesses the cache memory along with the command. It is sent to the control means 22.

In this case, the address of the count section is notified by the access source as a start address, and the data length CL of the count section is fixed at 28 bytes.

On the other hand, the address of the key part is found by adding the data length (28 bytes) of the count part to the start address, and the data length of the key part is found from the key length KL in the count part.

The address of the data section is obtained by adding the key length KL in the count section to the start address, and the data length of the data section is determined by adding the data length DL in the count section.
More demanded.

Furthermore, the start address of the next record is found by adding the key length KL and data length DL in the count section to the start address.

The command transferred from the channel adapter 21+ is stored in the command register 223 of the cache memory access control means 22.

The command analysis unit 224 analyzes the command stored in the command register 223, identifies read/write, sets the start address for accessing the cache memory 21 in the address register 221, and further specifies the number of bytes. The specified data length is set in the data byte counter 222.

At the time of memory write, the data transfer control unit 226 accesses the cache memory 21 using the address set in the address 221, and writes the data to the channel adapter 22. Write data transferred from the access source via the data register 225 is written to the cache memory 21 via the data register 225.

Next, the data transfer control unit 226 adds the address value of the address register 221 by the number of bytes of data received from the access source, and subtracts the number of bytes of the data byte counter 222 by the number of bytes of data received. Perform the update process.

Similarly, data received from the access source is stored in the cache memory 221 at the address of the address register 221.
1, and the receiver updates the contents of the address register 221 and data byte counter 222 by the number of data received.

When the value of the data byte counter 222 becomes 0 and the end of the write process for all data instructed by the access source is detected, the channel adapter 221 notifies the access source of the end of the memory write process.

Next, when reading memory, the data transfer control unit 2
26 accesses the cache memory 21 using the address set in the address register 221, stores a predetermined number of bytes of data read from the cache memory 21 in the -time data register 225, and then outputs the data via the channel adapter 22°. , forward to the access source.

At the same time, the data transfer control unit 226 performs an update process of adding the address value of the address register 221 by the number of bytes of the read data and subtracting the number of bytes of the data byte counter 222 by the number of bytes of the read data.

Thereafter, in the same manner, data read from the cache memory 21 using the address of the address register 221 is transferred to the data register 225 and the channel adapter 22. and updates the contents of the address register 221 and data byte counter 222 by the number of bytes of read data.

When the value of the data byte counter 222 becomes O and the end of the read process for all data instructed by the access source is detected, the channel adapter 22. notifies the access source of the end of memory read processing.

In the manner described above, data is read/written to the cache memory 2I. When the format of a record is changed, such as with a format write, the count section, key section, and data section of each record should be changed.
These addresses are calculated and the above-mentioned read/write processing is performed.

By doing the above, the CPU can read and write to the external storage device at high speed in the same way as normal memory, without being aware of the processing speed difference with the external storage device or the current operating state of the external storage device. can be done.

[Problem to be solved by the invention]

In the conventional cache memory control method in a disk cache system, as described above, the channel adapter side calculates the address on the cache memory to be accessed.

The address calculation performed on the channel adapter side is difficult to implement in hardware, so it is performed in firmware. Therefore, it is difficult to speed up address calculation, and there is a problem that it is difficult to speed up read/write to cache memory. Ta.

Particularly in the case of format writing, it is necessary to calculate the addresses of the count section, key section, and data section of each record, making it difficult to increase the speed of reading/writing from and to the cache memory.

Furthermore, since all address calculations for accessing the cache memory are performed on the channel adapter side, the load on the channel adapter increases, which also poses a problem in that high-speed processing is hindered.

The present invention allows the cache memory access control means to calculate the address for accessing the cache memory, thereby making the address calculation part hardware, speeding up the calculation of the access address, and reducing the load on the channel adapter side. An object of the present invention is to provide an improved cache memory control method that speeds up read/write processing for the entire cache memory.

[Means to solve the problem]

The means adopted by the present invention to solve the above-mentioned problems are as follows:
This will be explained with reference to FIG. The present invention is illustrated in FIGS. 5 and 6.
This is an improvement of the cache memory access control means 22 of the disk control device explained in the figure, and the configuration other than the cache memory access control means is the same as the configuration of FIG. 5.

FIG. 1 is a block diagram showing the basic configuration of the present invention, that is, the basic configuration of cache memory access control means (2)0.

In the cache memory access control means 10 shown in FIG. 1, 11 is an address register in which an address for accessing the cache memory is set.

Reference numeral 12 is an ID register, in which the identification number of the record to be accessed is set.

Reference numeral 13 denotes a command analysis means, which analyzes the command from the access source, performs read/write identification processing, sets the start address for accessing the cache memory 21 in the address register 11, and identifies the identification number of the record to be accessed using the ID. Processing such as setting in the register 12 is performed.

14 is an address updating means, and the address register 11
The cache memory 21 is accessed at the address of , the count part of the record read from the cache memory 21 is analyzed, and the above-mentioned process is performed until the identification number of the read record matches the identification number set in the ID register 12. A process of repeatedly updating the address of the address register based on the read data of the count section and reading the record is performed.

[For production]

A channel adapter (not shown) sends the command from the access source to the command analysis section 13 of the cache memory access control means 10.

The command analysis means 13 analyzes the command from the access source, identifies whether the command is for reading or writing, sets the start address for accessing the cache memo I 721 in the address register 11, and identifies the record to be accessed. ID register number 12
Set to .

The address update means 14 accesses the cache memory 21 with the address of the address register 11, analyzes the count part of the record read from the cache memory 21, and extracts the key length KL and data length DL from the read count part. Then, the identification number of the read record is compared with the identification number set in the ID register 12.

If the two do not match, the value of the address register is updated to the address of the next record using the key length KL and data length DL taken out from the count section, and the cache memory 21 is accessed with this updated address, and the cache memory 21 is accessed using the updated address. The identification number in the count section of the record read from the memory 21 is compared with the identification number set in the ID register 12.

Thereafter, in the same manner, the identification number of the count section of the record read from the cache memory 21 and the ID register 12
The updating of the address in the address register based on the read data in the count section and the reading of the record are repeated until the set identification numbers match.

When the identification number in the count section of the record read from the cache memory 21 and the identification number set in the ID register 12 match, that record is the record to be accessed, and henceforth the illustration will be performed in the same manner as in the past. A data transfer control unit that does not perform read/write operations on the cache memory 21 according to commands from the access source.

As described above, the cache memory access control means 10
Since the address for accessing the cache memory 21 is calculated on the side, the address calculation part can be easily made into hardware, making it possible to speed up the address calculation.

Additionally, the channel adapter side only needs to send the start address and the identification number ID of the access handling record to the cache memory access control means 10.
The load on the channel adapter is reduced, making it possible to speed up read/write processing for the entire cache memory.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is an explanatory diagram of the configuration of one embodiment of the present invention, and FIG.
The figure is an operation flowchart of the same embodiment.

(A) Configuration of embodiment In FIG. 2, cache memory access control means 1
0, address register 11, ID register 12, command analysis means 13 and address update means 14,
This is as explained in FIG. Further, each configuration other than the cache memory access control means 10 in the disk control device is common to each configuration explained in FIG.

In the command analysis means 13, 131 is a command register in which a command transferred from an access source via a channel adapter (not shown) is stored.

132 is a command analysis section, and the command register 13
Analyze the command from the access source stored in 1,
Processing to identify read/write, cache memory 21
Set the start address to access address register 1
1, the identification number of the record to be accessed is set in the ID register 12, and the data length specified by the access source or to be read/written at one time is set in the data byte counter.

In the address updating means 14, 141 is a count length register, and the count length CL of the count section of the record
is set. 142 is a key length register in which the key length KL of the key part of the record is set. 143 is a data length register in which the data length DL of the data portion of the record is set.

Further, 144 is an address adder, which adds the values of the count length register 141, key length register 142, and data length register 143 as appropriate in accordance with the instructions from the counting section analysis section to calculate the address for accessing the cache memory 21. and set it in the address register 11.

145 is a counting section analysis section, and address register 1
The cache memory 21 is accessed with address 1, the count part of the record read from the cache memory 21 is analyzed, and the identification number and ID of the read record are obtained.
Until the identification numbers set in register 12 match,
A process of repeatedly updating the address of the address register based on the read data of the count section and reading the record is performed.

15 is a data byte counter, and the number of bytes of data to be read/written to the cache memory 21 is set.

16 is a data register, and cache memory IJ2
Data to be read/written is temporarily stored in 1.

A data transfer control unit 17 controls the transfer of data to be read/written to the cache memory 21 and updates the contents of the data byte counter 222 in conjunction with the data transfer.

(B) Operation of the Embodiment The operation of the embodiment will be explained according to its processing steps with reference to the flowchart of FIG. 4.

Note that the following embodiment is for the case of format writing, and other processing can be easily understood from this format writing processing operation. When writing format,
The access source issues -times search ID and write CKD commands.

(1) Step SI The access source issues a search ID command and instructs the disk control device about the read/write distinction, the start address for accessing the cache memory 21, and the identification number ID of the record to be accessed.

The channel adapter of the disk control device receives and analyzes this command, and if it detects that it is a search ID command, it sends this search ID along with the command.
The command is transferred to the command register 131 of the cache memory access control means 10 and stored therein.

(2) Step S2 The command analysis unit 132 analyzes the command of the search ID from the access source stored in the command register 131, identifies whether it is a read or write command, and accesses the cache memory 21. The start address is set in the address register 11, and the identification number of the record to be accessed is set in the ID register 12.

(3) Step S3, Step S4 The command analysis unit 145 accesses the cache memory 21 with the address of the address register 11, and analyzes the count part of the record read from the cache memory 21. The key length KL and data length DL taken out from the count section are set in the key length register 142 and data length register 143, respectively (step S4). Note that since the data length DL of the count section is constant at 28 bytes, it is set in the count length register 141 in advance.

(4) Step S5 The command analysis unit 145 compares the identification number of the read record with the identification number written in the ID register 12.

(5) Step Sb When the two do not match, the command analysis unit 145 instructs the address adder 144 to input the key length KL stored in the key length register 142 and data length register 143.
and data length DL, and the value of the address register 11 is updated to the start address value of the next record.

(6) Below, the command analysis unit 145 performs the above-mentioned step S2.
- Repeat the process of step S6 until the identification number of the count section of the record read from the cache memory 21 and the identification number set in the ID register 12 match, based on the data of the read count section. Update of the address in the address register 11 and reading of the record are repeated.

(7) Step S.

When the identification number in the count section of the record read from the cache memory 21 and the identification number set in the ID register 12 match, the access source is notified of the end of the search ID command and waits for the next command. .

(8) Step SB The access source issues a write CKD command when performing a format write that writes to the count section, key section, and data section of the record.

The channel adapter of the disk control device receives and analyzes this command, and when detecting that it is a write CKD command, transfers this write CKD command to the command register 131 of the cache memory access control means 10 and stores it therein.

The command analysis unit 132 analyzes the command of the search ID from the access source stored in the command register 131, and determines which part of the record (count part, key part, data part, count part of the next record, key part). data section, data section, etc.).

(9) When the write CKD command is to write the count section, the command analysis section 132
The data length DL in the count length register 141 is set in the data byte counter 15.

00) Step SIO When writing data in the count section, the command analysis section 145 uses the key length KL and data length DL extracted from the count section in the same way as the process in step S4 described above.
, key length register 142 and data length register 143
Set each.

Thereafter, in the same way as in the conventional method explained in FIGS. 5 and 6, the data register 16 and the data transfer control section 17 perform the write process of the data in the count section, and the value of the data byte counter 15 becomes 0. When it becomes
The write processing of the count section ends.

(11) Step Sl+ When performing a partial write, the command analysis unit 132 sets the key length KL in the key length register 142 to the data byte counter 15.

Thereafter, write processing of data in the key section is performed in the same manner as in the case of the count section.

02) Step 312 When writing the data section, the command analysis section 132
sets the data length DL in the data length register 143 to the data byte counter 15.

Thereafter, write processing of data in the data section is performed in the same manner as in the case of the count section.

In either case, when the value of the data byte counter 15 becomes 0, the write processing of each part ends.

Although the embodiment in the case of format writing has been described above, write processing of only a portion of the key or write processing of only the data portion is performed in the same manner. When writing a portion of the data section, a search ID and write KD command are issued, and when writing a data section, a search ID and write D command are issued.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) Since the address for accessing the cache memory 21 is calculated on the cache memory access control means 10 side, the address calculation part can be easily made into hardware, making it possible to speed up the address calculation. .

(2) The load on the channel adapter side is reduced, making it possible to speed up read/write processing for the entire cache memory.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the basic configuration of the present invention, Fig. 2 is an explanatory diagram of the configuration of an embodiment of the present invention, Fig. 3 is an operational flowchart of the embodiment, and Fig. 4 is an explanatory diagram of the record format. , FIG. 5 is an explanatory diagram of a conventional disk control device, and FIG. 6 is an explanatory diagram of cache memory access control means of the conventional disk control device. In FIG. 1 and FIG. 2, 10...cache memory access control means, 11.
... Address register, 12 ... ID register, 13
. . . Command analysis means, 14 . . Address updating means, 21 . . . Cache memory.

Claims (1)

[Claims] Cache memory shared by multiple access sources (21)
and cache memory access control means (21) for controlling access to this cache memory (21).
10) In a cache memory control method of a disk control device equipped with (a) an address register (11) in which an address for accessing the cache memory (21) is set, and (b) an identification number of a record to be accessed, (c) Analyzes the command from the access source, sets the start address for accessing the cache memory in the address register (11), and sets the identification number of the record to be accessed in the ID register (11). (d) analyzes the count part of the record read from the cache memory (11), and sets the identification number and ID register (11) of the read record; The cache memory access control means (10) is provided with an address update means (14) for updating the address of the address register based on the read data of the count section until the identified identification numbers match. Characteristic cache memory control method.